Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7033	1			T1	20		T3	20		T5	70
testmodes[AdcCtrlTestmodeNormal]	5813	1			T2	1		T5	61		T8	2
testmodes[AdcCtrlTestmodeLowpower]	6045	1			T3	1		T4	17		T5	61
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3657	1			T1	19		T3	19		T5	27
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1844	1			T5	27		T10	7		T28	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1434	1			T5	16		T10	17		T23	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1857	1			T5	23		T10	10		T28	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2146	1			T5	19		T8	1		T10	9
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1459	1			T5	18		T10	9		T23	25
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1406	1			T3	1		T5	20		T10	14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1486	1			T5	14		T10	12		T23	24
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2910	1			T4	16		T5	27		T7	15