Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23275

1

T1

20

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3046

1

T3

25

T8

35

T20

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20887

1

T1

20

T3

20

T4

17

auto[1]

5434

1

T2

1

T3

25

T8

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	328	1			T118	19		T127	5		T183	1
values[1]	797	1			T8	15		T16	45		T133	1
values[2]	753	1			T3	25		T21	5		T22	28
values[3]	675	1			T8	20		T20	11		T34	3
values[4]	581	1			T14	26		T34	1		T35	25
values[5]	2620	1			T2	1		T9	11		T12	23
values[6]	550	1			T11	15		T123	5		T21	10
values[7]	538	1			T20	18		T123	8		T134	6
values[8]	805	1			T20	2		T22	3		T163	7
values[9]	693	1			T14	26		T16	20		T134	14
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	707	1			T8	15		T16	16		T17	9
values[1]	809	1			T3	25		T20	11		T21	5
values[2]	590	1			T8	20		T14	26		T143	6
values[3]	2671	1			T2	1		T9	11		T12	23
values[4]	485	1			T123	14		T133	1		T144	1
values[5]	511	1			T11	15		T21	10		T118	11
values[6]	693	1			T20	20		T123	8		T134	6
values[7]	678	1			T22	3		T163	7		T35	15
values[8]	768	1			T14	26		T16	20		T118	19
values[9]	151	1			T205	18		T183	1		T225	27
minimum	18258	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T16	13		T17	3		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	7		T146	25		T125	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T20	6		T156	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	12		T21	5		T22	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	16		T143	1		T202	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T8	12		T135	1		T19	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T2	1		T9	11		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T191	1		T136	1		T125	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T123	2		T144	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T133	1		T145	3		T18	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	7		T21	10		T124	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T118	5		T17	1		T125	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T20	8		T134	6		T124	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T20	2		T123	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T163	5		T35	11		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	3		T119	15		T228	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T14	12		T16	10		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T134	14		T18	4		T158	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T183	1		T229	5		T230	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T205	1		T225	15		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17930	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T133	1		T158	1		T227	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T16	3		T17	6		T231	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T8	8		T146	5		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T20	5		T226	12		T232	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	13		T22	14		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	10		T143	5		T202	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T8	8		T19	11		T233	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T12	21		T129	19		T130	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T136	13		T125	2		T54	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T123	12		T234	15		T235	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T145	6		T18	2		T59	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	8		T124	8		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T118	6		T125	1		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T20	10		T124	14		T136	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T123	7		T195	2		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T163	2		T35	4		T182	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T119	10		T228	3		T54	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	14		T16	10		T118	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T18	2		T67	2		T70	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T229	6		T230	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T205	17		T225	12		T175	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T16	14		T118	2		T119	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T227	7		T159	7		T237	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T118	1		T127	3		T183	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T67	1		T238	1		T239	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T16	28		T190	1		T226	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	7		T133	1		T146	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T17	3		T226	1		T232	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	12		T21	5		T22	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T20	6		T156	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T8	12		T34	2		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	16		T34	1		T35	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T19	6		T191	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T2	1		T9	11		T12	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T133	1		T145	3		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	7		T123	1		T21	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T118	5		T17	1		T125	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T20	8		T134	6		T124	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T123	1		T138	1		T195	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T163	5		T35	11		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T20	2		T22	3		T119	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	12		T16	10		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T134	14		T18	4		T205	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T118	18		T127	2		T159	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T67	2		T238	13		T240	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T16	17		T190	6		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T8	8		T146	5		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T17	6		T226	12		T232	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	13		T22	14		T35	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T20	5		T143	5		T202	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T8	8		T34	1		T19	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	10		T35	14		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T19	6		T136	13		T125	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T12	21		T129	19		T123	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T145	6		T18	2		T59	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	8		T123	4		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T118	6		T125	1		T167	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T20	10		T124	8		T136	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T123	7		T195	2		T241	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T163	2		T35	4		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T119	10		T236	12		T228	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	14		T16	10		T182	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T18	2		T205	17		T70	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T16	4		T17	8		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	9		T146	7		T125	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T20	6		T156	1		T226	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	14		T21	1		T22	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	11		T143	6		T202	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	9		T135	1		T19	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T2	1		T9	1		T12	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T191	1		T136	14		T125	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T123	14		T144	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	1		T145	7		T18	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	9		T21	1		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T118	7		T17	1		T125	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	11		T134	1		T124	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T20	1		T123	8		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T163	3		T35	5		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T22	1		T119	11		T228	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T14	15		T16	11		T118	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T134	1		T18	5		T158	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T183	1		T229	7		T230	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T205	18		T225	13		T175	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18071	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T133	1		T158	1		T227	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T16	12		T17	1		T231	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	6		T146	23		T125	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T20	5		T232	4		T137	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	11		T21	4		T22	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	15		T202	8		T242	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T8	11		T19	7		T233	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T9	10		T15	14		T132	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T125	5		T166	7		T54	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T234	3		T243	4		T244	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T145	2		T59	15		T245	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	6		T21	9		T124	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T118	4		T125	1		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T20	7		T134	5		T124	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T20	1		T195	1		T166	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T163	4		T35	10		T246	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T22	2		T119	14		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	11		T16	9		T127	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T134	13		T18	1		T70	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T229	4		T230	15		T247	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T225	14		T248	11		T249	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T16	14		T226	11		T166	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T237	9		T39	11		T250	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T118	19		T127	3		T183	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T67	3		T238	14		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T16	19		T190	7		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	9		T133	1		T146	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	8		T226	13		T232	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	14		T21	1		T22	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T20	6		T156	1		T143	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T8	9		T34	2		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	11		T34	1		T35	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	7		T191	1		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T2	1		T9	1		T12	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T133	1		T145	7		T18	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	9		T123	5		T21	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T118	7		T17	1		T125	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T20	11		T134	1		T124	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T123	8		T138	1		T195	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T163	3		T35	5		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T20	1		T22	1		T119	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	15		T16	11		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T134	1		T18	5		T205	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T127	2		T152	2		T197	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T239	11		T248	11		T251	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T16	26		T226	11		T231	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	6		T146	23		T234	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	1		T232	4		T137	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	11		T21	4		T22	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	5		T202	8		T128	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T8	11		T34	1		T19	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T14	15		T35	10		T242	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T19	5		T125	5		T166	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T9	10		T15	14		T132	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T145	2		T59	15		T245	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	6		T21	9		T140	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T118	4		T125	1		T167	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T20	7		T134	5		T124	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T195	1		T166	13		T234	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T163	4		T35	10		T124	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	1		T22	2		T119	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	11		T16	9		T242	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T134	13		T18	1		T70	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23487

1

T1

20

T2

1

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

2834

1

T8

35

T11

15

T14

52

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20890

1

T1

20

T3

45

T4

17

auto[1]

5431

1

T2

1

T9

11

T11

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T252	30		-	-		-	-
values[0]	107	1			T239	13		T253	13		T254	13
values[1]	552	1			T34	3		T135	1		T144	1
values[2]	599	1			T8	20		T14	26		T123	5
values[3]	625	1			T118	19		T119	25		T17	9
values[4]	2797	1			T2	1		T9	11		T12	23
values[5]	665	1			T16	29		T20	11		T21	10
values[6]	779	1			T16	20		T22	28		T34	1
values[7]	685	1			T3	25		T20	2		T118	11
values[8]	606	1			T14	26		T16	16		T20	18
values[9]	895	1			T8	15		T11	15		T21	5
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T34	3		T134	6		T135	1
values[1]	588	1			T8	20		T14	26		T123	5
values[2]	662	1			T123	17		T133	1		T35	25
values[3]	2755	1			T2	1		T9	11		T12	23
values[4]	793	1			T16	49		T143	29		T17	1
values[5]	698	1			T3	25		T22	28		T34	1
values[6]	742	1			T14	26		T16	16		T20	2
values[7]	446	1			T20	18		T133	1		T190	7
values[8]	672	1			T8	15		T21	5		T133	1
values[9]	187	1			T11	15		T166	14		T158	1
minimum	18055	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	2		T135	1		T18	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	6		T144	1		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T123	1		T156	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	12		T14	16		T119	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T123	2		T133	1		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T35	11		T118	1		T125	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T2	1		T9	11		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T21	10		T35	11		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T16	10		T143	15		T19	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T16	15		T17	1		T125	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	12		T34	1		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T22	14		T134	14		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T182	1		T139	14		T140	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	12		T16	13		T20	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T20	8		T133	1		T190	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T136	1		T148	1		T255	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T133	1		T163	5		T35	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T8	7		T21	5		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T158	1		T184	3		T256	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T11	7		T166	14		T257	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17891	1			T1	20		T3	20		T4	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T34	1		T18	2		T127	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T205	17		T258	4		T196	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T123	4		T143	5		T124	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	8		T14	10		T119	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T123	15		T17	6		T241	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T35	14		T118	18		T125	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T12	21		T20	5		T129	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T35	4		T228	1		T59	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T16	10		T143	14		T19	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	14		T125	12		T232	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	13		T231	12		T159	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T22	14		T226	12		T238	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T182	8		T140	12		T212	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	14		T16	3		T118	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T20	10		T190	6		T70	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T136	14		T255	14		T238	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T163	2		T35	15		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T8	8		T136	4		T54	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T184	2		T256	14		T259	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T11	8		T257	9		T175	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T118	2		T119	2		T17	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T252	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T239	13		T253	13		T250	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T254	6		T260	3		T261	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	2		T135	1		T18	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T144	1		T206	1		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T123	1		T156	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	12		T14	16		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	3		T191	1		T236	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T118	1		T119	15		T125	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T2	1		T9	11		T12	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	22		T232	5		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	6		T22	3		T125	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T16	15		T21	10		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T16	10		T34	1		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T22	14		T226	1		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	12		T146	12		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T20	2		T118	5		T134	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T20	8		T190	1		T262	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	12		T16	13		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T133	2		T163	5		T35	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	7		T11	7		T21	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T252	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T263	11		T264	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T254	7		T260	2		T261	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	1		T18	2		T127	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T205	17		T67	2		T258	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T123	4		T143	5		T124	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T8	8		T14	10		T238	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T17	6		T236	3		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T118	18		T119	10		T125	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1075	1			T12	21		T129	19		T123	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T35	18		T232	10		T59	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	5		T125	2		T137	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T16	14		T125	12		T265	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	10		T143	14		T19	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T22	14		T226	12		T179	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	13		T182	8		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T118	6		T228	3		T167	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T20	10		T190	6		T70	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	14		T16	3		T136	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T163	2		T35	15		T124	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	8		T11	8		T136	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6