Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23187

1

T1

20

T2

1

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3134

1

T8

20

T16

36

T20

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20922

1

T1

20

T3

20

T4

17

auto[1]

5399

1

T2

1

T3

25

T9

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T54	14		T196	6		T336	2
values[0]	45	1			T128	10		T235	5		T152	5
values[1]	478	1			T35	25		T136	5		T138	1
values[2]	618	1			T20	2		T163	7		T34	1
values[3]	656	1			T21	10		T191	1		T146	12
values[4]	562	1			T14	26		T16	16		T21	5
values[5]	2772	1			T2	1		T8	15		T9	11
values[6]	662	1			T16	20		T20	11		T123	5
values[7]	654	1			T14	26		T16	29		T143	29
values[8]	766	1			T3	25		T123	8		T133	1
values[9]	1105	1			T8	20		T20	18		T123	9
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	683	1			T35	25		T136	5		T137	20
values[1]	577	1			T20	2		T21	10		T163	7
values[2]	732	1			T14	26		T22	28		T191	1
values[3]	2684	1			T2	1		T9	11		T11	15
values[4]	611	1			T8	15		T20	11		T143	6
values[5]	659	1			T14	26		T16	20		T123	5
values[6]	717	1			T16	29		T123	8		T35	15
values[7]	676	1			T3	25		T8	20		T133	1
values[8]	772	1			T20	18		T123	9		T133	1
values[9]	224	1			T70	10		T54	21		T234	13
minimum	17986	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T265	10		T128	5		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T35	11		T136	1		T137	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T163	5		T144	1		T140	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T20	2		T21	10		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	12		T146	12		T128	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T22	14		T191	1		T55	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T2	1		T9	11		T11	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T16	13		T21	5		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	7		T143	1		T19	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T20	6		T134	20		T166	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	16		T118	5		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T16	10		T123	1		T22	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T16	15		T123	1		T124	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T35	11		T118	1		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	12		T119	15		T145	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	12		T133	1		T18	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T123	1		T133	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T20	8		T135	2		T124	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T70	6		T234	11		T289	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T54	10		T159	1		T286	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T337	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T265	14		T128	5		T27	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	14		T136	4		T137	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T163	2		T308	8		T311	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T205	17		T167	1		T238	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	14		T128	2		T234	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	14		T304	11		T257	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T11	8		T12	21		T129	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T16	3		T18	2		T125	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	8		T143	5		T19	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T20	5		T228	1		T227	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	10		T118	6		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T16	10		T123	4		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	14		T123	7		T124	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T35	4		T118	18		T232	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	13		T119	10		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T8	8		T18	2		T182	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T123	8		T202	9		T190	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	10		T124	8		T17	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T70	4		T234	2		T289	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T54	11		T159	10		T266	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T196	4		T336	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T54	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T128	5		T235	1		T152	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T296	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T265	10		T158	1		T27	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T35	11		T136	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T163	5		T144	1		T140	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T20	2		T34	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T146	12		T128	14		T338	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	10		T191	1		T304	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	12		T17	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T16	13		T21	5		T22	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T2	1		T8	7		T9	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T134	6		T166	8		T228	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T118	5		T143	1		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	10		T20	6		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	16		T16	15		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T143	15		T146	13		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	12		T123	1		T124	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T133	1		T35	11		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T123	1		T133	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T8	12		T20	8		T135	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T196	2		T336	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T54	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T128	5		T235	4		T152	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T265	14		T27	2		T257	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T35	14		T136	4		T228	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T163	2		T289	14		T311	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T137	15		T205	17		T140	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T128	2		T234	6		T151	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T304	11		T257	9		T238	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T14	14		T179	3		T242	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T16	3		T22	14		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T8	8		T11	8		T12	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T228	1		T227	7		T295	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T118	6		T143	5		T226	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	10		T20	5		T123	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	10		T16	14		T303	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T143	14		T146	5		T233	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	13		T123	7		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T35	4		T118	18		T18	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T123	8		T119	10		T202	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	8		T20	10		T124	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T265	15		T128	6		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T35	15		T136	5		T137	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T163	3		T144	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T20	1		T21	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	15		T146	1		T128	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	15		T191	1		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T2	1		T9	1		T11	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	4		T21	1		T18	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	9		T143	6		T19	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T20	6		T134	2		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	11		T118	7		T226	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	11		T123	5		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T16	15		T123	8		T124	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T35	5		T118	19		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	14		T119	11		T145	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	9		T133	1		T18	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T123	9		T133	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T20	11		T135	2		T124	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T70	5		T234	3		T289	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T54	12		T159	11		T286	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T337	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T265	9		T128	4		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T35	10		T137	4		T140	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T163	4		T140	10		T245	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T20	1		T21	9		T139	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	11		T146	11		T128	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	13		T55	4		T304	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T9	10		T11	6		T15	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T16	12		T21	4		T125	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T8	6		T19	2		T195	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T20	5		T134	18		T166	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	15		T118	4		T303	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T16	9		T22	2		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	14		T124	9		T140	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	10		T232	4		T127	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	11		T119	14		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	11		T18	1		T226	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T202	8		T59	4		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T20	7		T124	10		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T70	5		T234	10		T289	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T54	9		T286	6		T266	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T337	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T196	4		T336	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T54	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T128	6		T235	5		T152	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T296	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T265	15		T158	1		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T35	15		T136	5		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T163	3		T144	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T20	1		T34	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T146	1		T128	3		T338	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T21	1		T191	1		T304	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	15		T17	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T16	4		T21	1		T22	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T2	1		T8	9		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T134	1		T166	1		T228	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T118	7		T143	6		T226	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T16	11		T20	6		T123	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	11		T16	15		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T143	15		T146	6		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	14		T123	8		T124	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T133	1		T35	5		T118	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T123	9		T133	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T8	9		T20	11		T135	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T196	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T54	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T128	4		T152	2		T229	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T296	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T265	9		T27	1		T257	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T35	10		T228	2		T70	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T163	4		T140	10		T289	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	1		T137	4		T139	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T146	11		T128	13		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T21	9		T304	7		T257	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	11		T166	11		T242	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T16	12		T21	4		T22	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T8	6		T9	10		T11	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T134	5		T166	7		T228	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T118	4		T195	1		T236	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T16	9		T20	5		T22	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	15		T16	14		T303	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T143	14		T146	12		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	11		T124	9		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	10		T18	1		T226	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T119	14		T202	8		T70	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	11		T20	7		T124	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10