Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23153

1

T1

20

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3168

1

T3

25

T14

26

T16

49

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20516

1

T1

20

T3

45

T4

17

auto[1]

5805

1

T2

1

T8

20

T9

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	212	1			T133	1		T138	1		T182	9
values[0]	45	1			T268	26		T308	10		T277	1
values[1]	766	1			T3	25		T16	16		T123	5
values[2]	2646	1			T2	1		T8	20		T9	11
values[3]	807	1			T8	15		T16	20		T20	18
values[4]	523	1			T20	2		T163	7		T135	1
values[5]	523	1			T118	11		T119	1		T124	19
values[6]	715	1			T14	26		T21	5		T22	3
values[7]	700	1			T133	1		T35	56		T143	6
values[8]	655	1			T14	26		T123	9		T22	28
values[9]	748	1			T11	15		T16	29		T123	8
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	732	1			T3	25		T16	16		T20	11
values[1]	2622	1			T2	1		T8	35		T9	11
values[2]	821	1			T16	20		T20	18		T144	1
values[3]	524	1			T20	2		T163	7		T135	1
values[4]	483	1			T21	5		T34	3		T118	11
values[5]	873	1			T14	26		T22	3		T133	1
values[6]	496	1			T35	31		T143	6		T195	7
values[7]	663	1			T14	26		T123	9		T22	28
values[8]	729	1			T11	15		T16	29		T123	8
values[9]	127	1			T19	16		T140	11		T147	10
minimum	18251	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T16	13		T123	1		T21	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	12		T20	6		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T2	1		T8	19		T9	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T17	3		T19	6		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T20	8		T191	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	10		T144	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T20	2		T19	3		T231	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T163	5		T135	1		T124	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T21	5		T34	2		T118	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T119	1		T191	1		T67	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	11		T135	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	12		T22	3		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T35	16		T126	4		T26	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T143	1		T195	5		T265	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	16		T22	14		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T123	1		T17	1		T146	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	7		T18	3		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T16	15		T123	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T19	9		T147	1		T238	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T140	11		T316	10		T296	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T133	1		T118	1		T136	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	3		T123	4		T143	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	13		T20	5		T119	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T8	16		T12	21		T129	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	6		T19	6		T128	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T20	10		T136	13		T232	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	10		T303	15		T167	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T19	5		T231	12		T127	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T163	2		T124	8		T190	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T34	1		T118	6		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T67	2		T147	12		T255	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T35	14		T136	4		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	14		T124	14		T205	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	15		T242	10		T311	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T143	5		T195	2		T265	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	10		T22	14		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T123	8		T228	1		T59	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	8		T18	2		T182	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T16	14		T123	7		T202	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T19	7		T147	9		T238	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T312	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T118	2		T119	2		T17	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T118	18		T136	14		T257	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T182	1		T236	3		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T133	1		T138	1		T140	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T277	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T268	11		T308	1		T310	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T16	13		T123	1		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	12		T133	1		T118	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T2	1		T8	12		T9	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T20	6		T119	15		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	7		T20	8		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	10		T17	3		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T20	2		T19	3		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T163	5		T135	1		T190	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T118	5		T127	3		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T119	1		T124	11		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T21	5		T34	2		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	12		T22	3		T124	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T35	27		T144	1		T126	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T133	1		T143	1		T195	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	16		T22	14		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T123	1		T17	1		T146	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	7		T18	3		T19	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T16	15		T123	1		T202	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T182	8		T236	3		T147	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T279	10		T306	17		T329	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T268	15		T308	9		T310	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	3		T123	4		T143	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	13		T118	18		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T8	8		T12	21		T129	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T20	5		T119	10		T128	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	8		T20	10		T35	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T16	10		T17	6		T19	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T19	5		T231	12		T289	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T163	2		T190	6		T228	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T118	6		T127	2		T227	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T124	8		T67	2		T257	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T34	1		T136	4		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	14		T124	14		T205	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T35	29		T242	10		T183	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T143	5		T195	2		T265	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	10		T22	14		T145	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T123	8		T59	8		T289	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	8		T18	2		T19	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	14		T123	7		T202	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T16	4		T123	5		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	14		T20	6		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T2	1		T8	18		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	8		T19	7		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T20	11		T191	1		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T16	11		T144	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T20	1		T19	6		T231	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T163	3		T135	1		T124	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T21	1		T34	2		T118	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T119	1		T191	1		T67	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T35	15		T135	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	15		T22	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T35	16		T126	4		T26	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T143	6		T195	6		T265	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	11		T22	15		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T123	9		T17	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	9		T18	5		T182	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T16	15		T123	8		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T19	8		T147	10		T238	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T140	1		T316	1		T296	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18005	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T133	1		T118	19		T136	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T16	12		T21	9		T143	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	11		T20	5		T134	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T8	17		T9	10		T15	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T17	1		T19	5		T128	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T20	7		T232	4		T70	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T16	9		T166	20		T303	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T20	1		T19	2		T231	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T163	4		T124	10		T166	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T21	4		T34	1		T118	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T255	11		T306	10		T302	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T35	10		T125	8		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	11		T22	2		T124	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T35	15		T242	3		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T195	1		T265	9		T283	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	15		T22	13		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T146	11		T226	11		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	6		T236	1		T70	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	14		T202	8		T146	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T19	8		T238	2		T293	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T140	10		T316	9		T296	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T125	5		T55	4		T343	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T257	9		T268	10		T321	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T182	9		T236	5		T147	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T133	1		T138	1		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T277	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T268	16		T308	10		T310	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T16	4		T123	5		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	14		T133	1		T118	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T2	1		T8	9		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T20	6		T119	11		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T8	9		T20	11		T35	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T16	11		T17	8		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T20	1		T19	6		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T163	3		T135	1		T190	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T118	7		T127	3		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T119	1		T124	9		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T21	1		T34	2		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	15		T22	1		T124	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T35	31		T144	1		T126	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T133	1		T143	6		T195	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	11		T22	15		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T123	9		T17	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	9		T18	5		T19	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T16	15		T123	8		T202	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T236	1		T256	11		T293	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T140	10		T279	10		T306	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T268	10		T310	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	12		T143	14		T125	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	11		T134	13		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T8	11		T9	10		T15	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T20	5		T119	14		T128	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	6		T20	7		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T16	9		T17	1		T19	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T20	1		T19	2		T231	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T163	4		T166	13		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T118	4		T127	2		T54	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T124	10		T166	11		T257	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T21	4		T34	1		T125	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	11		T22	2		T124	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T35	25		T242	3		T212	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T195	1		T265	9		T283	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	15		T22	13		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T146	11		T226	11		T139	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	6		T19	8		T70	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T16	14		T202	8		T146	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10