Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23011

1

T1

20

T2

1

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3310

1

T8

35

T16

36

T20

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20641

1

T1

20

T3

20

T4

17

auto[1]

5680

1

T2

1

T3

25

T8

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	280	1			T20	18		T123	9		T190	7
values[0]	26	1			T128	10		T235	5		T296	11
values[1]	501	1			T35	25		T136	5		T138	1
values[2]	604	1			T20	2		T163	7		T34	1
values[3]	713	1			T14	26		T21	10		T191	1
values[4]	478	1			T16	16		T21	5		T22	28
values[5]	2782	1			T2	1		T8	15		T9	11
values[6]	711	1			T16	20		T20	11		T123	5
values[7]	681	1			T14	26		T16	29		T123	8
values[8]	699	1			T3	25		T133	1		T35	15
values[9]	865	1			T8	20		T133	1		T156	1
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	480	1			T137	20		T138	1		T265	24
values[1]	607	1			T20	2		T21	10		T163	7
values[2]	736	1			T14	26		T22	28		T191	1
values[3]	2681	1			T2	1		T9	11		T11	15
values[4]	621	1			T8	15		T20	11		T143	6
values[5]	629	1			T14	26		T16	20		T123	5
values[6]	711	1			T16	29		T123	8		T35	15
values[7]	732	1			T3	25		T8	20		T133	1
values[8]	796	1			T20	18		T123	9		T133	1
values[9]	177	1			T19	12		T70	10		T54	21
minimum	18151	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T138	1		T265	10		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T137	5		T344	1		T255	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	10		T163	5		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	2		T205	1		T139	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	12		T146	12		T128	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T22	14		T191	1		T304	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T2	1		T9	11		T11	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T16	13		T21	5		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T20	6		T19	3		T195	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	7		T143	1		T134	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	16		T118	5		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	10		T123	1		T22	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T16	15		T123	1		T124	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T35	11		T118	1		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	12		T145	3		T275	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	12		T133	1		T119	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T123	1		T133	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T20	8		T135	1		T124	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T70	6		T159	1		T279	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T19	6		T54	10		T234	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17889	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T35	11		T136	1		T228	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T265	14		T27	2		T235	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T137	15		T255	2		T174	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T163	2		T308	8		T311	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T205	17		T140	19		T167	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	14		T128	2		T234	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T22	14		T304	11		T257	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T11	8		T12	21		T129	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T16	3		T18	2		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T20	5		T19	5		T195	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	8		T143	5		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	10		T118	6		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	10		T123	4		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	14		T123	7		T124	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	4		T118	18		T232	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	13		T145	6		T327	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	8		T119	10		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T123	8		T202	9		T190	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T20	10		T124	8		T17	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T70	4		T159	10		T279	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T19	6		T54	11		T234	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T118	2		T119	2		T17	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T35	14		T136	4		T228	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T123	1		T190	1		T159	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T20	8		T54	16		T331	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T128	5		T235	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T296	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T138	1		T265	10		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T35	11		T136	1		T228	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T163	5		T34	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	2		T137	5		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	12		T21	10		T146	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T191	1		T304	12		T257	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T17	1		T144	1		T125	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T16	13		T21	5		T22	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T2	1		T9	11		T11	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	7		T134	6		T166	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T20	6		T118	5		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	10		T123	1		T22	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	16		T16	15		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T143	15		T146	13		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	12		T124	10		T145	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T133	1		T35	11		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T133	1		T156	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	12		T135	1		T119	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T123	8		T190	6		T159	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T20	10		T54	19		T331	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T128	5		T235	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T265	14		T27	2		T257	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T35	14		T136	4		T228	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T163	2		T311	5		T345	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T137	15		T205	17		T140	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	14		T128	2		T234	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T304	11		T257	9		T238	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T125	2		T179	3		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T16	3		T22	14		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T11	8		T12	21		T129	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	8		T228	1		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T20	5		T118	6		T226	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T16	10		T123	4		T143	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	10		T16	14		T123	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T143	14		T146	5		T233	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	13		T124	14		T145	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T35	4		T118	18		T18	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T202	9		T136	14		T183	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	8		T119	10		T124	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T138	1		T265	15		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T137	16		T344	1		T255	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T21	1		T163	3		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	1		T205	18		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	15		T146	1		T128	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T22	15		T191	1		T304	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T2	1		T9	1		T11	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T16	4		T21	1		T18	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T20	6		T19	6		T195	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	9		T143	6		T134	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	11		T118	7		T226	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	11		T123	5		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T16	15		T123	8		T124	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T35	5		T118	19		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	14		T145	7		T275	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	9		T133	1		T119	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T123	9		T133	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T20	11		T135	1		T124	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T70	5		T159	11		T279	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T19	7		T54	12		T234	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18012	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T35	15		T136	5		T228	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T265	9		T27	1		T184	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T137	4		T255	7		T322	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T21	9		T163	4		T140	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T20	1		T139	5		T140	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	11		T146	11		T128	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	13		T304	7		T257	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T9	10		T11	6		T15	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T16	12		T21	4		T231	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T20	5		T19	2		T195	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	6		T134	18		T166	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T14	15		T118	4		T303	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	9		T22	2		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T16	14		T124	9		T167	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T35	10		T232	4		T127	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	11		T145	2		T327	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	11		T119	14		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T202	8		T59	4		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T20	7		T124	10		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T70	5		T279	13		T60	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T19	5		T54	9		T234	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T128	4		T70	3		T257	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T35	10		T228	2		T181	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T123	9		T190	7		T159	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T20	11		T54	21		T331	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T128	6		T235	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T296	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T138	1		T265	15		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	15		T136	5		T228	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T163	3		T34	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T20	1		T137	16		T205	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	15		T21	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T191	1		T304	16		T257	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T17	1		T144	1		T125	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	4		T21	1		T22	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T2	1		T9	1		T11	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	9		T134	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T20	6		T118	7		T226	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T16	11		T123	5		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	11		T16	15		T123	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T143	15		T146	6		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	14		T124	15		T145	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T133	1		T35	5		T118	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T133	1		T156	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	9		T135	1		T119	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T238	2		T279	13		T196	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T20	7		T54	14		T331	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T128	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T296	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T265	9		T27	1		T70	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T35	10		T228	2		T255	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T163	4		T140	10		T311	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T20	1		T137	4		T139	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	11		T21	9		T146	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T304	7		T257	8		T245	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T125	5		T166	11		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	12		T21	4		T22	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T9	10		T11	6		T15	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	6		T134	5		T166	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T20	5		T118	4		T195	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	9		T22	2		T134	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	15		T16	14		T242	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T143	14		T146	12		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	11		T124	9		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	10		T18	1		T226	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T202	8		T70	5		T59	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	11		T119	14		T124	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10