Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23200

1

T1

20

T2

1

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3121

1

T8

35

T16

20

T123

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20684

1

T1

20

T3

45

T4

17

auto[1]

5637

1

T2

1

T8

20

T9

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	191	1			T134	6		T145	9		T136	5
values[0]	29	1			T236	6		T300	1		T200	1
values[1]	595	1			T8	15		T20	18		T29	1
values[2]	707	1			T123	8		T35	31		T118	19
values[3]	676	1			T16	36		T123	5		T21	10
values[4]	588	1			T20	11		T35	25		T118	11
values[5]	598	1			T14	52		T133	1		T135	1
values[6]	535	1			T133	1		T125	29		T138	1
values[7]	693	1			T3	25		T16	29		T135	1
values[8]	708	1			T8	20		T20	2		T34	1
values[9]	3020	1			T2	1		T9	11		T11	15
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	524	1			T8	15		T123	8		T35	31
values[1]	638	1			T118	19		T134	14		T126	4
values[2]	720	1			T16	36		T123	5		T21	10
values[3]	668	1			T14	26		T20	11		T143	6
values[4]	465	1			T14	26		T133	1		T119	1
values[5]	632	1			T3	25		T16	29		T133	1
values[6]	2866	1			T2	1		T9	11		T12	23
values[7]	520	1			T8	20		T20	2		T124	24
values[8]	857	1			T123	9		T21	5		T22	31
values[9]	147	1			T11	15		T134	6		T146	12
minimum	18284	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T35	16		T29	1		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	7		T123	1		T191	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T118	1		T126	4		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T134	14		T205	1		T128	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T16	13		T123	1		T21	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T16	10		T133	1		T118	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	16		T20	6		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T143	1		T135	1		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	12		T119	1		T19	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T133	1		T231	15		T166	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	12		T16	15		T119	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T133	1		T135	1		T125	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T2	1		T9	11		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	1		T18	4		T338	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T20	2		T232	5		T265	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T8	12		T124	10		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T21	5		T22	3		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T123	1		T22	14		T163	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T11	7		T134	6		T146	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T128	5		T242	12		T67	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17905	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T236	3		T54	6		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T35	15		T136	13		T234	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T8	8		T123	7		T127	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T118	18		T70	4		T212	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T205	17		T128	2		T241	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T16	3		T123	4		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T16	10		T118	6		T202	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T14	10		T20	5		T257	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T143	5		T17	6		T146	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T14	14		T19	7		T183	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T231	12		T242	10		T289	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	13		T16	14		T119	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T125	14		T327	10		T174	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1136	1			T12	21		T129	19		T130	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T18	2		T147	12		T238	28
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T232	10		T265	14		T303	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T8	8		T124	14		T19	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T143	14		T145	6		T19	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T123	8		T22	14		T163	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T11	8		T236	12		T228	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T128	5		T67	2		T197	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T20	10		T118	2		T119	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T236	3		T54	8		T161	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T134	6		T145	3		T136	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T67	1		T238	3		T196	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T171	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T236	3		T300	1		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T20	8		T29	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	7		T191	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T35	16		T118	1		T126	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T123	1		T134	14		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	13		T123	1		T21	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T16	10		T133	1		T202	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T20	6		T35	11		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T118	5		T143	1		T18	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T14	28		T119	1		T19	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T133	1		T135	1		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T138	1		T166	14		T257	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T133	1		T125	15		T231	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	12		T16	15		T119	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T135	1		T18	4		T245	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T20	2		T35	11		T232	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	12		T34	1		T124	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T2	1		T9	11		T11	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T123	1		T22	14		T163	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T145	6		T136	4		T179	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T67	2		T238	1		T196	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T171	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T236	3		T342	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T20	10		T136	13		T140	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	8		T54	8		T346	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T35	15		T118	18		T70	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T123	7		T127	2		T128	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	3		T123	4		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	10		T202	9		T195	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T20	5		T35	14		T255	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T118	6		T143	5		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	24		T19	7		T183	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T17	6		T289	15		T174	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T257	9		T308	8		T311	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T125	14		T231	12		T242	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	13		T16	14		T119	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T18	2		T173	19		T322	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T35	4		T232	10		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	8		T124	14		T140	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1128	1			T11	8		T12	21		T129	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T123	8		T22	14		T163	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	16		T29	1		T136	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T8	9		T123	8		T191	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T118	19		T126	4		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T134	1		T205	18		T128	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T16	4		T123	5		T21	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T16	11		T133	1		T118	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	11		T20	6		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T143	6		T135	1		T17	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	15		T119	1		T19	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T133	1		T231	13		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	14		T16	15		T119	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T133	1		T135	1		T125	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T2	1		T9	1		T12	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T34	1		T18	5		T338	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T20	1		T232	11		T265	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T8	9		T124	15		T19	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T21	1		T22	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T123	9		T22	15		T163	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T11	9		T134	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T128	6		T242	1		T67	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18060	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T236	5		T54	9		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T35	15		T234	10		T149	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T8	6		T127	2		T245	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T70	5		T212	14		T184	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T134	13		T128	13		T59	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T16	12		T21	9		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T16	9		T118	4		T202	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	15		T20	5		T267	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T17	1		T146	12		T226	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T14	11		T19	8		T140	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T231	14		T166	7		T242	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	11		T16	14		T119	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T125	13		T166	11		T327	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T9	10		T15	14		T132	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T18	1		T55	4		T245	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T20	1		T232	4		T265	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T8	11		T124	9		T19	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T21	4		T22	2		T143	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T22	13		T163	4		T124	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T11	6		T134	5		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T128	4		T242	11		T197	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T20	7		T140	14		T304	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T236	1		T54	5		T239	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T134	1		T145	7		T136	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T67	3		T238	2		T196	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T171	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T236	5		T300	1		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T20	11		T29	1		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	9		T191	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T35	16		T118	19		T126	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T123	8		T134	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T16	4		T123	5		T21	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T16	11		T133	1		T202	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T20	6		T35	15		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T118	7		T143	6		T18	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	26		T119	1		T19	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T133	1		T135	1		T17	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T138	1		T166	1		T257	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T133	1		T125	16		T231	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	14		T16	15		T119	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T135	1		T18	5		T245	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T20	1		T35	5		T232	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	9		T34	1		T124	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1487	1			T2	1		T9	1		T11	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T123	9		T22	15		T163	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T134	5		T145	2		T236	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T238	2		T196	2		T197	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T171	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T20	7		T140	14		T234	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	6		T54	5		T245	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	15		T70	5		T212	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T134	13		T127	2		T128	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	12		T21	9		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	9		T202	8		T195	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T20	5		T35	10		T255	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T118	4		T146	12		T139	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	26		T19	8		T267	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T17	1		T226	11		T166	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T166	13		T257	8		T311	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T125	13		T231	14		T166	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	11		T16	14		T119	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T18	1		T245	12		T283	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T20	1		T35	10		T232	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T8	11		T124	9		T140	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T9	10		T11	6		T15	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T22	13		T163	4		T124	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10