Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23505

1

T1

20

T2

1

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

2816

1

T8

35

T11

15

T14

52

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20904

1

T1

20

T3

45

T4

17

auto[1]

5417

1

T2

1

T9

11

T11

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	245	1			T21	5		T135	1		T166	12
values[0]	65	1			T206	1		T286	7		T266	6
values[1]	610	1			T34	3		T135	1		T144	1
values[2]	577	1			T8	20		T14	26		T123	5
values[3]	607	1			T123	9		T118	19		T17	9
values[4]	2788	1			T2	1		T9	11		T12	23
values[5]	687	1			T16	29		T20	11		T21	10
values[6]	730	1			T16	20		T22	28		T34	1
values[7]	758	1			T3	25		T20	2		T118	11
values[8]	606	1			T14	26		T16	16		T20	18
values[9]	667	1			T8	15		T11	15		T133	2
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	557	1			T34	3		T134	6		T135	1
values[1]	600	1			T8	20		T14	26		T123	5
values[2]	670	1			T123	9		T35	25		T118	19
values[3]	2797	1			T2	1		T9	11		T12	23
values[4]	725	1			T16	29		T21	10		T143	29
values[5]	694	1			T16	20		T22	28		T34	1
values[6]	752	1			T3	25		T14	26		T16	16
values[7]	473	1			T20	18		T133	1		T144	1
values[8]	677	1			T8	15		T11	15		T133	1
values[9]	165	1			T21	5		T166	14		T158	1
minimum	18211	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	2		T135	1		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T134	6		T144	1		T67	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T123	1		T156	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	12		T14	16		T119	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T123	1		T17	3		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T35	11		T118	1		T125	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T2	1		T9	11		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T35	11		T125	9		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T143	15		T19	9		T146	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	15		T21	10		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T16	10		T34	1		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T22	14		T134	14		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	12		T182	1		T139	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	12		T16	13		T20	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T20	8		T133	1		T190	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T144	1		T136	1		T195	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T133	1		T163	5		T35	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T8	7		T11	7		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T158	1		T256	12		T259	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T21	5		T166	14		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17935	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T206	1		T266	6		T60	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T34	1		T205	17		T127	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T67	2		T258	4		T196	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T123	4		T143	5		T124	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T8	8		T14	10		T119	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T123	8		T17	6		T241	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T35	14		T118	18		T125	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T12	21		T20	5		T129	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T35	4		T125	12		T265	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T143	14		T19	7		T146	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T16	14		T232	10		T128	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T16	10		T231	12		T159	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T22	14		T226	12		T238	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	13		T182	8		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	14		T16	3		T118	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T20	10		T190	6		T70	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T136	14		T195	2		T255	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T163	2		T35	15		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T8	8		T11	8		T136	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T256	14		T259	14		T237	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T175	13		T347	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T118	2		T119	2		T17	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T60	2		T254	7		T348	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T147	1		T246	15		T259	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T21	5		T135	1		T166	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T286	7		T263	6		T222	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T206	1		T266	6		T348	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T34	2		T135	1		T18	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T144	1		T67	1		T245	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T123	1		T156	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	12		T14	16		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T123	1		T17	3		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T118	1		T125	2		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T2	1		T9	11		T12	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	22		T138	1		T59	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T20	6		T22	3		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T16	15		T21	10		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T16	10		T34	1		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T22	14		T226	1		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	12		T146	12		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T20	2		T118	5		T134	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T20	8		T190	1		T262	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	12		T16	13		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T133	2		T163	5		T35	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	7		T11	7		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T147	12		T259	14		T237	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T161	10		T349	15		T347	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T263	11		T222	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T348	11		T260	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	1		T18	2		T205	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T67	2		T258	4		T196	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T123	4		T143	5		T124	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	8		T14	10		T119	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T123	8		T17	6		T236	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T118	18		T125	1		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T12	21		T129	19		T123	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T35	18		T59	8		T331	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T20	5		T125	2		T137	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T16	14		T125	12		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T16	10		T143	14		T19	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	14		T226	12		T179	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	13		T182	8		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T118	6		T228	3		T167	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T20	10		T190	6		T70	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	14		T16	3		T136	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T163	2		T35	15		T124	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	8		T11	8		T136	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T34	2		T135	1		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T134	1		T144	1		T67	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T123	5		T156	1		T143	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T8	9		T14	11		T119	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T123	9		T17	8		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T35	15		T118	19		T125	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T2	1		T9	1		T12	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T35	5		T125	13		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T143	15		T19	8		T146	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T16	15		T21	1		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T16	11		T34	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T22	15		T134	1		T226	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T3	14		T182	9		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	15		T16	4		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T20	11		T133	1		T190	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T144	1		T136	15		T195	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T133	1		T163	3		T35	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	9		T11	9		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T158	1		T256	15		T259	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T21	1		T166	1		T175	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18058	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T206	1		T266	1		T60	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T34	1		T127	2		T128	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T134	5		T245	8		T316	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T124	10		T267	4		T233	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	11		T14	15		T119	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	1		T140	24		T234	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	10		T125	1		T166	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T9	10		T15	14		T20	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T35	10		T125	8		T265	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T143	14		T19	8		T146	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	14		T21	9		T232	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	9		T146	11		T231	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T22	13		T134	13		T152	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	11		T139	5		T140	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	11		T16	12		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T20	7		T70	5		T268	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T195	1		T255	11		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T163	4		T35	15		T124	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T8	6		T11	6		T166	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T256	11		T259	11		T237	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T21	4		T166	13		T347	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T18	1		T257	9		T286	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T266	5		T244	2		T254	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T147	13		T246	1		T259	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T21	1		T135	1		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T286	1		T263	12		T222	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T206	1		T266	1		T348	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T34	2		T135	1		T18	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T144	1		T67	3		T245	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T123	5		T156	1		T143	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	9		T14	11		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T123	9		T17	8		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T118	19		T125	2		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T2	1		T9	1		T12	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T35	20		T138	1		T59	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T20	6		T22	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	15		T21	1		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T16	11		T34	1		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T22	15		T226	13		T179	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	14		T146	1		T182	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	1		T118	7		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T20	11		T190	7		T262	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	15		T16	4		T136	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T133	2		T163	3		T35	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	9		T11	9		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T246	14		T259	11		T237	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T21	4		T166	11		T347	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T286	6		T263	5		T222	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T266	5		T260	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	1		T18	1		T127	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T245	8		T258	16		T196	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T124	10		T267	4		T233	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	11		T14	15		T134	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T17	1		T236	1		T140	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T125	1		T166	7		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T9	10		T15	14		T132	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T35	20		T59	4		T331	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T20	5		T22	2		T125	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T16	14		T21	9		T125	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T16	9		T143	14		T19	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T22	13		T266	9		T80	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	11		T146	11		T140	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T20	1		T118	4		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T20	7		T139	5		T70	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T14	11		T16	12		T195	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T163	4		T35	15		T124	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T8	6		T11	6		T166	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10