Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T34	2		T135	1		T18	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T134	1		T144	1		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T123	5		T156	1		T143	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	9		T14	11		T119	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T123	17		T133	1		T17	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T35	15		T118	19		T125	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T2	1		T9	1		T12	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	1		T35	5		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T16	11		T143	15		T19	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T16	15		T17	1		T125	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	14		T34	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T22	15		T134	1		T226	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T182	9		T139	2		T140	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	15		T16	4		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T20	11		T133	1		T190	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T136	15		T148	1		T255	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T133	1		T163	3		T35	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T8	9		T21	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T158	1		T184	5		T256	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T11	9		T166	1		T257	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18011	1			T1	20		T3	20		T4	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	1		T18	1		T127	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T134	5		T245	8		T266	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T124	10		T267	4		T233	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	11		T14	15		T119	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T17	1		T140	24		T234	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T35	10		T125	1		T166	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T9	10		T15	14		T20	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T21	9		T35	10		T228	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	9		T143	14		T19	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	14		T125	8		T232	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	11		T146	11		T231	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T22	13		T134	13		T152	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T139	12		T140	5		T55	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	11		T16	12		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T20	7		T70	5		T268	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T255	11		T238	2		T269	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T163	4		T35	15		T124	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T8	6		T21	4		T166	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T256	11		T259	11		T253	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T11	6		T166	13		T257	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T239	12		T270	6		T250	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T252	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T239	1		T253	1		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T254	8		T260	3		T261	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	2		T135	1		T18	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T144	1		T206	1		T205	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T123	5		T156	1		T143	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	9		T14	11		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	8		T191	1		T236	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T118	19		T119	11		T125	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T2	1		T9	1		T12	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T35	20		T232	11		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T20	6		T22	1		T125	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	15		T21	1		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T16	11		T34	1		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T22	15		T226	13		T179	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	14		T146	1		T182	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T20	1		T118	7		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T20	11		T190	7		T262	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	15		T16	4		T136	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T133	2		T163	3		T35	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	9		T11	9		T21	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T252	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T239	12		T253	12		T250	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T254	5		T260	2		T261	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T34	1		T18	1		T127	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T245	8		T266	5		T258	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T124	10		T267	4		T233	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	11		T14	15		T134	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T17	1		T236	1		T140	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T119	14		T125	1		T166	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T9	10		T15	14		T132	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T35	20		T232	4		T59	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T20	5		T22	2		T125	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	14		T21	9		T125	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	9		T143	14		T19	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T22	13		T266	9		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	11		T146	11		T139	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T20	1		T118	4		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T20	7		T139	5		T70	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T14	11		T16	12		T195	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T163	4		T35	15		T124	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	6		T11	6		T21	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10