Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23194

1

T1

20

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3127

1

T3

25

T14

52

T16

49

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20263

1

T1

20

T3

20

T4

17

auto[1]

6058

1

T2

1

T3

25

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	664	1			T5	2		T10	6		T23	3
values[0]	31	1			T123	9		T190	7		T271	14
values[1]	774	1			T8	20		T16	16		T35	31
values[2]	2879	1			T2	1		T9	11		T12	23
values[3]	806	1			T8	15		T20	20		T156	1
values[4]	555	1			T16	29		T21	10		T133	1
values[5]	615	1			T14	26		T134	6		T135	1
values[6]	569	1			T3	25		T14	26		T143	29
values[7]	636	1			T133	1		T34	1		T119	25
values[8]	580	1			T11	15		T22	3		T134	14
values[9]	718	1			T123	8		T22	28		T133	1
minimum	17494	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	703	1			T8	20		T16	36		T21	5
values[1]	2839	1			T2	1		T9	11		T12	23
values[2]	927	1			T8	15		T16	29		T20	20
values[3]	432	1			T21	10		T133	1		T135	1
values[4]	596	1			T14	26		T134	6		T124	19
values[5]	719	1			T3	25		T14	26		T34	1
values[6]	637	1			T133	1		T166	8		T272	1
values[7]	476	1			T11	15		T22	3		T134	14
values[8]	716	1			T123	13		T22	28		T34	3
values[9]	48	1			T133	1		T273	1		T274	13
minimum	18228	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T8	12		T16	13		T118	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	10		T21	5		T163	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T2	1		T9	11		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T20	6		T144	1		T145	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T8	7		T20	8		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T16	15		T20	2		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T21	10		T133	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	1		T146	13		T137	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T124	11		T265	10		T236	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	16		T134	6		T19	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T119	15		T128	14		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	12		T14	12		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T133	1		T166	8		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T276	1		T234	3		T159	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	7		T22	3		T134	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T125	9		T138	1		T127	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T123	2		T34	2		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T22	14		T135	1		T202	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T274	13		T277	1		T278	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T133	1		T273	1		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17912	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T144	1		T18	4		T255	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	8		T16	3		T118	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	10		T163	2		T35	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1137	1			T12	21		T129	19		T130	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T20	5		T145	6		T136	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	8		T20	10		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T16	14		T35	14		T118	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T125	2		T182	8		T59	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T146	5		T137	15		T179	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T124	8		T265	14		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	10		T19	7		T195	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T119	10		T128	2		T67	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	13		T14	14		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T235	4		T238	15		T279	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T234	6		T159	17		T255	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	8		T136	13		T140	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T125	12		T127	2		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T123	11		T34	1		T241	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T22	14		T202	9		T242	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T280	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T281	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T123	8		T118	2		T119	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T18	2		T255	14		T282	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	500	1			T5	2		T10	6		T23	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T231	1		T183	1		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T123	1		T190	1		T271	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T8	12		T16	13		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T35	16		T144	1		T18	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T2	1		T9	11		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T16	10		T20	6		T21	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	7		T20	8		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	2		T35	11		T19	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T21	10		T133	1		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	15		T118	1		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T135	1		T124	11		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	16		T134	6		T19	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T128	14		T275	1		T67	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	12		T14	12		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T133	1		T119	15		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	1		T233	15		T276	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	7		T22	3		T134	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T127	3		T128	5		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T123	1		T34	2		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T22	14		T133	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17354	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T123	4		T161	10		T284	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T238	13		T174	11		T279	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T123	8		T190	6		T271	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	8		T16	3		T124	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	15		T18	2		T183	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1106	1			T12	21		T129	19		T130	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T16	10		T20	5		T163	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	8		T20	10		T236	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T35	14		T19	6		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T18	2		T125	2		T182	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T16	14		T118	18		T146	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T124	8		T265	14		T236	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	10		T19	7		T137	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T128	2		T67	2		T257	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	13		T14	14		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T119	10		T235	4		T238	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T233	16		T234	6		T255	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	8		T136	13		T140	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T127	2		T128	5		T159	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T123	7		T34	1		T241	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T22	14		T202	9		T125	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	9		T16	4		T118	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	11		T21	1		T163	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T2	1		T9	1		T12	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T20	6		T144	1		T145	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	9		T20	11		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T16	15		T20	1		T35	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T21	1		T133	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	1		T146	6		T137	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T124	9		T265	15		T236	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	11		T134	1		T19	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T119	11		T128	3		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	14		T14	15		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T133	1		T166	1		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T276	1		T234	7		T159	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	9		T22	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T125	13		T138	1		T127	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T123	13		T34	2		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T22	15		T135	1		T202	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T274	1		T277	1		T278	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T133	1		T273	1		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18068	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T144	1		T18	5		T255	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	11		T16	12		T118	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T16	9		T21	4		T163	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T9	10		T15	14		T132	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T20	5		T145	2		T232	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	6		T20	7		T236	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	14		T20	1		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T21	9		T125	5		T59	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T146	12		T137	4		T140	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T124	10		T265	9		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	15		T134	5		T19	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T119	14		T128	13		T257	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	11		T14	11		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T166	7		T279	10		T285	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T234	2		T255	15		T269	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T11	6		T22	2		T134	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T125	8		T127	2		T128	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T34	1		T55	4		T286	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T22	13		T202	8		T242	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T274	12		T278	11		T280	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T259	11		T197	11		T287	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T18	1		T255	11		T282	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	541	1			T5	2		T10	6		T23	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T231	1		T183	1		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T123	9		T190	7		T271	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	9		T16	4		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T35	16		T144	1		T18	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T2	1		T9	1		T12	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	11		T20	6		T21	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T8	9		T20	11		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T20	1		T35	15		T19	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T21	1		T133	1		T18	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T16	15		T118	19		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T135	1		T124	9		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	11		T134	1		T19	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T128	3		T275	1		T67	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	14		T14	15		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T133	1		T119	11		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T34	1		T233	17		T276	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	9		T22	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T127	3		T128	6		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T123	8		T34	2		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T22	15		T133	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T288	2		T40	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T245	9		T279	13		T177	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T271	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	11		T16	12		T124	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T35	15		T18	1		T166	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T9	10		T15	14		T132	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T16	9		T20	5		T21	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	6		T20	7		T236	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T20	1		T35	10		T19	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T21	9		T125	5		T238	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	14		T146	12		T139	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T124	10		T265	9		T236	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	15		T134	5		T19	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T128	13		T257	8		T289	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	11		T14	11		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T119	14		T279	10		T285	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T233	14		T234	2		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	6		T22	2		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T127	2		T128	4		T274	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T34	1		T55	4		T286	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T22	13		T202	8		T125	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10