Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23315

1

T1

20

T2

1

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3006

1

T11

15

T16

20

T20

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20690

1

T1

20

T3

45

T4

17

auto[1]

5631

1

T2

1

T8

15

T9

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T290	5		T291	15		T292	4
values[0]	51	1			T136	5		T196	6		T293	6
values[1]	708	1			T14	26		T21	5		T143	29
values[2]	689	1			T16	16		T163	7		T134	6
values[3]	771	1			T3	25		T8	15		T14	26
values[4]	580	1			T20	11		T123	9		T35	31
values[5]	691	1			T8	20		T20	18		T123	13
values[6]	683	1			T16	20		T20	2		T21	10
values[7]	491	1			T119	1		T136	14		T195	7
values[8]	2676	1			T2	1		T9	11		T12	23
values[9]	965	1			T11	15		T22	3		T156	1
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	950	1			T14	26		T21	5		T143	29
values[1]	667	1			T14	26		T163	7		T34	3
values[2]	660	1			T3	25		T8	15		T16	45
values[3]	721	1			T123	17		T22	28		T134	14
values[4]	752	1			T8	20		T20	18		T123	5
values[5]	528	1			T16	20		T20	2		T135	1
values[6]	2699	1			T2	1		T9	11		T12	23
values[7]	553	1			T34	1		T35	40		T143	6
values[8]	671	1			T11	15		T118	11		T124	19
values[9]	138	1			T22	3		T156	1		T124	24
minimum	17982	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T14	16		T21	5		T143	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T19	9		T138	1		T166	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	12		T163	5		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T135	1		T262	1		T140	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	12		T8	7		T16	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T20	6		T179	1		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T123	1		T22	14		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T123	1		T134	14		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T8	12		T20	8		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T123	1		T21	10		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T135	1		T119	1		T19	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T16	10		T20	2		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T2	1		T9	11		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T190	1		T136	1		T195	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T34	1		T143	1		T144	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T35	22		T294	1		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T118	5		T146	13		T226	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	7		T124	11		T145	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T22	3		T124	10		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T156	1		T296	15		T197	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T14	10		T143	14		T136	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T19	7		T257	12		T235	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	14		T163	2		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T140	12		T228	1		T233	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	13		T8	8		T16	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T20	5		T179	3		T227	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T123	8		T22	14		T202	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T123	7		T226	12		T125	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	8		T20	10		T18	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T123	4		T17	6		T265	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T19	5		T127	2		T241	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T16	10		T18	2		T182	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T12	21		T129	19		T130	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T190	6		T136	13		T195	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T143	5		T234	2		T173	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T35	18		T67	2		T255	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T118	6		T146	5		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	8		T124	8		T145	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T124	14		T295	2		T60	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T197	1		T291	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T290	1		T298	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T291	1		T292	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T136	1		T293	4		T186	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T196	4		T299	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T14	16		T21	5		T143	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T135	1		T138	1		T166	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T16	13		T163	5		T134	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T19	9		T140	6		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	12		T8	7		T14	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T262	1		T179	1		T140	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T123	1		T35	16		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T20	6		T134	14		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	12		T20	8		T22	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T123	2		T133	1		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T135	1		T18	4		T19	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	10		T20	2		T21	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T119	1		T54	10		T300	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T136	1		T195	5		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T2	1		T9	11		T12	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T35	22		T190	1		T166	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T22	3		T118	5		T124	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T11	7		T156	1		T124	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T290	4		T298	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T291	14		T292	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T136	4		T293	2		T301	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T196	2		T299	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	10		T143	14		T125	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T257	12		T159	10		T235	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	3		T163	2		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T19	7		T140	12		T228	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	13		T8	8		T14	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T179	3		T233	16		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T123	8		T35	15		T125	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T20	5		T226	12		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	8		T20	10		T22	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T123	11		T17	6		T67	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T18	2		T19	5		T127	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	10		T18	2		T265	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T54	11		T289	1		T302	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T136	13		T195	2		T183	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T12	21		T129	19		T130	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	18		T190	6		T255	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T118	6		T124	14		T146	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	8		T124	8		T145	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T14	11		T21	1		T143	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T19	8		T138	1		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	15		T163	3		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	1		T262	1		T140	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	14		T8	9		T16	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	6		T179	4		T227	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T123	9		T22	15		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T123	8		T134	1		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	9		T20	11		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T123	5		T21	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T135	1		T119	1		T19	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	11		T20	1		T18	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T2	1		T9	1		T12	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T190	7		T136	14		T195	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	1		T143	6		T144	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T35	20		T294	1		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T118	7		T146	6		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	9		T124	9		T145	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T22	1		T124	15		T295	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T156	1		T296	1		T197	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	15		T21	4		T143	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	8		T166	7		T55	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	11		T163	4		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T140	15		T228	1		T233	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	11		T8	6		T16	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	5		T59	15		T283	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T22	13		T202	8		T139	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T134	13		T125	8		T59	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	11		T20	7		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T21	9		T17	1		T265	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T19	2		T146	11		T127	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T16	9		T20	1		T303	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T9	10		T15	14		T132	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T195	1		T166	11		T304	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T234	10		T246	14		T173	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T35	20		T255	11		T152	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T118	4		T146	12		T226	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	6		T124	10		T145	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T22	2		T124	9		T60	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T296	14		T197	1		T274	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T290	5		T298	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T291	15		T292	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T136	5		T293	3		T186	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T196	4		T299	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T14	11		T21	1		T143	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T135	1		T138	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T16	4		T163	3		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T19	8		T140	13		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	14		T8	9		T14	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T262	1		T179	4		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T123	9		T35	16		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T20	6		T134	1		T226	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	9		T20	11		T22	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T123	13		T133	1		T17	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T135	1		T18	5		T19	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T16	11		T20	1		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T119	1		T54	12		T300	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T136	14		T195	6		T183	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T2	1		T9	1		T12	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T35	20		T190	7		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T22	1		T118	7		T124	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T11	9		T156	1		T124	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T293	3		T301	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T196	2		T299	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	15		T21	4		T143	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T166	7		T55	4		T257	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T16	12		T163	4		T134	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T19	8		T140	5		T228	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	11		T8	6		T14	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T140	10		T233	14		T59	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T35	15		T125	5		T139	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T20	5		T134	13		T125	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	11		T20	7		T22	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T17	1		T59	4		T234	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	1		T19	2		T127	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	9		T20	1		T21	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T54	9		T289	2		T302	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T195	1		T70	3		T305	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T9	10		T15	14		T132	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T35	20		T166	11		T255	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T22	2		T118	4		T124	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	6		T124	10		T145	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10