Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23165

1

T1

20

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3156

1

T3

25

T14

26

T16

49

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20532

1

T1

20

T3

45

T4

17

auto[1]

5789

1

T2

1

T8

20

T9

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T138	1		T306	33		T307	1
values[0]	66	1			T54	14		T268	26		T308	10
values[1]	748	1			T3	25		T16	16		T123	5
values[2]	2686	1			T2	1		T8	20		T9	11
values[3]	724	1			T8	15		T16	20		T20	18
values[4]	573	1			T20	2		T163	7		T19	8
values[5]	581	1			T118	11		T135	1		T119	1
values[6]	684	1			T14	26		T21	5		T22	3
values[7]	671	1			T133	1		T35	56		T143	6
values[8]	663	1			T14	26		T123	9		T22	28
values[9]	909	1			T11	15		T16	29		T123	8
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	868	1			T3	25		T16	16		T20	11
values[1]	2781	1			T2	1		T8	35		T9	11
values[2]	749	1			T16	20		T20	18		T144	1
values[3]	520	1			T20	2		T163	7		T135	1
values[4]	516	1			T14	26		T21	5		T34	3
values[5]	853	1			T22	3		T35	25		T135	1
values[6]	488	1			T133	1		T35	31		T143	6
values[7]	671	1			T14	26		T123	9		T22	28
values[8]	684	1			T16	29		T123	8		T133	1
values[9]	177	1			T11	15		T202	18		T19	16
minimum	18014	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T16	13		T123	1		T21	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	12		T20	6		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T2	1		T8	19		T9	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	3		T19	6		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T20	8		T19	3		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T16	10		T144	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T20	2		T231	15		T127	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T163	5		T135	1		T124	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T21	5		T34	2		T118	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	12		T119	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T35	11		T135	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T22	3		T124	10		T242	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T35	16		T126	4		T26	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T133	1		T143	1		T195	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	16		T22	14		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T123	1		T17	1		T146	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T145	3		T18	3		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T16	15		T123	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T11	7		T19	9		T238	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T202	9		T262	1		T140	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T257	10		T309	5		T310	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	3		T123	4		T143	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	13		T20	5		T118	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T8	16		T12	21		T129	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	6		T19	6		T128	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T20	10		T19	5		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	10		T303	15		T167	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T231	12		T127	2		T289	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T163	2		T124	8		T190	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T34	1		T118	6		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	14		T205	17		T67	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T35	14		T136	4		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T124	14		T295	9		T151	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T35	15		T242	10		T311	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T143	5		T195	2		T265	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	10		T22	14		T226	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T123	8		T228	1		T59	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T145	6		T18	2		T182	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	14		T123	7		T146	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T11	8		T19	7		T238	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T202	9		T248	3		T312	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T257	10		T310	3		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T307	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T138	1		T306	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T313	1		T277	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T54	6		T268	11		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T16	13		T123	1		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	12		T133	1		T118	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T2	1		T8	12		T9	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T20	6		T119	15		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	7		T20	8		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	10		T17	3		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T20	2		T19	3		T231	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T163	5		T190	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T118	5		T125	9		T127	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T135	1		T119	1		T124	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T21	5		T34	2		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	12		T22	3		T124	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T35	27		T144	1		T126	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	1		T143	1		T195	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	16		T22	14		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T123	1		T17	1		T146	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	7		T145	3		T18	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T16	15		T123	1		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T306	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T54	8		T268	15		T308	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	3		T123	4		T143	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	13		T118	18		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T8	8		T12	21		T129	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T20	5		T119	10		T128	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	8		T20	10		T35	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T16	10		T17	6		T19	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T19	5		T231	12		T289	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T163	2		T190	6		T228	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T118	6		T125	12		T127	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T124	8		T67	2		T257	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	1		T136	4		T234	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	14		T124	14		T205	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T35	29		T242	10		T183	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T143	5		T195	2		T265	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	10		T22	14		T226	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T123	8		T59	8		T314	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	8		T145	6		T18	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	14		T123	7		T202	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T16	4		T123	5		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T3	14		T20	6		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T2	1		T8	18		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	8		T19	7		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T20	11		T19	6		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	11		T144	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T20	1		T231	13		T127	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T163	3		T135	1		T124	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T21	1		T34	2		T118	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	15		T119	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T35	15		T135	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T22	1		T124	15		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T35	16		T126	4		T26	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T133	1		T143	6		T195	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	11		T22	15		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T123	9		T17	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T145	7		T18	5		T182	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T16	15		T123	8		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T11	9		T19	8		T238	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T202	10		T262	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T257	11		T309	3		T310	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T16	12		T21	9		T143	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	11		T20	5		T134	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T8	17		T9	10		T15	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T17	1		T19	5		T128	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	7		T19	2		T232	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T16	9		T166	20		T303	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T20	1		T231	14		T127	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T163	4		T124	10		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T21	4		T34	1		T118	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	11		T166	11		T245	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T35	10		T125	8		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	2		T124	9		T242	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T35	15		T242	3		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T195	1		T265	9		T283	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	15		T22	13		T137	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T146	11		T226	11		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T145	2		T236	1		T70	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T16	14		T146	12		T236	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T11	6		T19	8		T238	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T202	8		T140	10		T296	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T257	9		T309	2		T310	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T307	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T138	1		T306	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T313	1		T277	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T54	9		T268	16		T308	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T16	4		T123	5		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	14		T133	1		T118	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T2	1		T8	9		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T20	6		T119	11		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	9		T20	11		T35	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T16	11		T17	8		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T20	1		T19	6		T231	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T163	3		T190	7		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T118	7		T125	13		T127	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T135	1		T119	1		T124	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	1		T34	2		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	15		T22	1		T124	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T35	31		T144	1		T126	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T133	1		T143	6		T195	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	11		T22	15		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T123	9		T17	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T11	9		T145	7		T18	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T16	15		T123	8		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T306	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T54	5		T268	10		T315	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T16	12		T143	14		T125	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	11		T134	13		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T8	11		T9	10		T15	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T20	5		T119	14		T128	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	6		T20	7		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T16	9		T17	1		T19	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T20	1		T19	2		T231	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T163	4		T228	2		T316	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T118	4		T125	8		T127	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T124	10		T166	11		T257	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T21	4		T34	1		T234	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	11		T22	2		T124	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T35	25		T242	3		T311	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T195	1		T265	9		T283	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	15		T22	13		T137	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T146	11		T226	11		T139	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	6		T145	2		T19	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T16	14		T202	8		T146	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10