Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23233

1

T1

20

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3088

1

T3

25

T8

35

T20

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20899

1

T1

20

T3

20

T4

17

auto[1]

5422

1

T2

1

T3

25

T8

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T159	11		T239	12		T323	1
values[0]	16	1			T234	13		T324	3		-	-
values[1]	764	1			T8	15		T16	45		T133	1
values[2]	792	1			T3	25		T20	11		T21	5
values[3]	680	1			T8	20		T34	3		T156	1
values[4]	545	1			T14	26		T34	1		T35	25
values[5]	2624	1			T2	1		T9	11		T12	23
values[6]	470	1			T11	15		T123	5		T118	11
values[7]	616	1			T20	18		T123	8		T21	10
values[8]	801	1			T20	2		T22	3		T163	7
values[9]	1008	1			T14	26		T16	20		T118	19
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	956	1			T8	15		T16	45		T133	1
values[1]	813	1			T3	25		T21	5		T22	28
values[2]	589	1			T8	20		T20	11		T34	1
values[3]	2702	1			T2	1		T9	11		T12	23
values[4]	459	1			T123	14		T133	1		T144	1
values[5]	495	1			T11	15		T21	10		T118	11
values[6]	643	1			T20	20		T123	8		T134	6
values[7]	729	1			T22	3		T163	7		T35	15
values[8]	796	1			T14	26		T16	20		T118	19
values[9]	132	1			T127	5		T183	1		T225	27
minimum	18007	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T16	28		T17	3		T190	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	7		T133	1		T146	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T156	1		T226	1		T137	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	12		T21	5		T22	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T20	6		T34	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	12		T135	1		T202	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T2	1		T9	11		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T145	3		T191	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T123	2		T144	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T133	1		T18	3		T59	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	7		T21	10		T124	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T118	5		T17	1		T125	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T20	8		T134	6		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T20	2		T123	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T163	5		T35	11		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T22	3		T119	15		T139	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	12		T16	10		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	14		T18	4		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T127	3		T183	1		T229	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T225	15		T161	1		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T325	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T16	17		T17	6		T190	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	8		T146	5		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T226	12		T137	15		T128	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	13		T22	14		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	5		T143	5		T232	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T8	8		T202	9		T19	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T12	21		T14	10		T129	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T145	6		T136	13		T54	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T123	12		T234	15		T235	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T18	2		T59	17		T308	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	8		T124	8		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T118	6		T125	1		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T20	10		T136	4		T140	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T123	7		T195	2		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T163	2		T35	4		T124	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T119	10		T228	3		T54	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	14		T16	10		T118	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T18	2		T205	17		T67	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T127	2		T229	6		T326	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T225	12		T161	10		T240	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T325	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T159	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T239	12		T323	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T324	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T234	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T16	28		T190	1		T226	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	7		T133	1		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T20	6		T17	3		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	12		T21	5		T22	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T156	1		T143	1		T128	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	12		T34	2		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	16		T34	1		T35	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	6		T136	1		T125	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T2	1		T9	11		T12	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T133	1		T145	3		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	7		T123	1		T124	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T118	5		T17	1		T125	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T20	8		T21	10		T134	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T123	1		T138	1		T195	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T163	5		T35	11		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T20	2		T22	3		T119	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T14	12		T16	10		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T134	14		T18	4		T205	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T159	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T234	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T16	17		T190	6		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	8		T146	5		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T20	5		T17	6		T226	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	13		T22	14		T35	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T143	5		T128	7		T147	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T8	8		T34	1		T202	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	10		T35	14		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T19	6		T136	13		T125	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T12	21		T129	19		T123	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T145	6		T18	2		T59	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	8		T123	4		T124	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T118	6		T125	1		T295	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T20	10		T136	4		T238	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T123	7		T195	2		T241	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T163	2		T35	4		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T119	10		T236	12		T228	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	14		T16	10		T118	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T18	2		T205	17		T67	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T16	19		T17	8		T190	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	9		T133	1		T146	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T156	1		T226	13		T137	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	14		T21	1		T22	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	6		T34	1		T143	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	9		T135	1		T202	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T2	1		T9	1		T12	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T145	7		T191	1		T136	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T123	14		T144	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T133	1		T18	5		T59	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	9		T21	1		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T118	7		T17	1		T125	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T20	11		T134	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T20	1		T123	8		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T163	3		T35	5		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T22	1		T119	11		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T14	15		T16	11		T118	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T134	1		T18	5		T205	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T127	3		T183	1		T229	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T225	13		T161	11		T240	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T325	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T16	26		T17	1		T226	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	6		T146	23		T125	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	4		T128	17		T327	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	11		T21	4		T22	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T20	5		T232	4		T242	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T8	11		T202	8		T19	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T9	10		T14	15		T15	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T145	2		T166	7		T54	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T234	3		T244	2		T328	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T59	15		T245	8		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T11	6		T21	9		T124	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T118	4		T125	1		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T20	7		T134	5		T140	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T20	1		T195	1		T166	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T163	4		T35	10		T124	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T22	2		T119	14		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	11		T16	9		T242	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T134	13		T18	1		T70	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T127	2		T229	4		T230	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T225	14		T248	11		T249	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T325	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T159	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T239	1		T323	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T324	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T234	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T16	19		T190	7		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	9		T133	1		T146	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T20	6		T17	8		T226	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	14		T21	1		T22	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T156	1		T143	6		T128	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	9		T34	2		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	11		T34	1		T35	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T19	7		T136	14		T125	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T2	1		T9	1		T12	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T133	1		T145	7		T18	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	9		T123	5		T124	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T118	7		T17	1		T125	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T20	11		T21	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T123	8		T138	1		T195	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T163	3		T35	5		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T20	1		T22	1		T119	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T14	15		T16	11		T118	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T134	1		T18	5		T205	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T239	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T324	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T234	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	26		T226	11		T231	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	6		T146	12		T279	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T20	5		T17	1		T232	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	11		T21	4		T22	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T128	17		T257	8		T321	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T8	11		T34	1		T202	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T14	15		T35	10		T242	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T19	5		T125	5		T166	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	943	1			T9	10		T15	14		T132	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T145	2		T59	15		T245	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T11	6		T124	10		T140	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T118	4		T125	1		T289	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T20	7		T21	9		T134	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T195	1		T166	13		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T163	4		T35	10		T124	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T20	1		T22	2		T119	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	11		T16	9		T127	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T134	13		T18	1		T70	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10