Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21056

1

T1

20

T3

20

T4

17

auto[ADC_CTRL_FILTER_COND_OUT]

5265

1

T2

1

T3

25

T9

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

20

T3

20

T4

17

auto[1]

5552

1

T2

1

T3

25

T8

35

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	63	1			T136	14		T295	3		T329	29
values[0]	77	1			T14	26		T124	24		T144	1
values[1]	652	1			T21	10		T34	1		T118	19
values[2]	682	1			T3	25		T22	3		T133	1
values[3]	529	1			T14	26		T123	8		T22	28
values[4]	541	1			T124	19		T19	8		T232	15
values[5]	660	1			T11	15		T16	20		T20	2
values[6]	854	1			T8	15		T16	29		T17	9
values[7]	633	1			T20	18		T123	5		T146	12
values[8]	665	1			T20	11		T35	25		T135	1
values[9]	2984	1			T2	1		T8	20		T9	11
minimum	17981	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	879	1			T3	25		T14	26		T21	10
values[1]	2738	1			T2	1		T9	11		T12	23
values[2]	574	1			T14	26		T123	8		T22	28
values[3]	630	1			T11	15		T133	1		T163	7
values[4]	630	1			T8	15		T16	20		T20	2
values[5]	826	1			T16	29		T20	18		T123	5
values[6]	721	1			T35	25		T119	25		T126	4
values[7]	549	1			T20	11		T35	31		T135	1
values[8]	703	1			T16	16		T123	9		T118	11
values[9]	45	1			T8	20		T29	1		T272	1
minimum	18026	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T21	10		T118	1		T134	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	12		T14	16		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T22	3		T133	1		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1369	1			T2	1		T9	11		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T156	1		T124	11		T19	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	12		T123	1		T22	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T133	1		T191	1		T127	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	7		T163	5		T143	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	7		T16	10		T20	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T143	1		T158	1		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T20	8		T123	1		T125	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T16	15		T21	5		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T35	11		T119	15		T126	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T236	7		T228	2		T245	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T20	6		T135	1		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T35	16		T226	12		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T123	1		T118	5		T19	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T16	13		T134	6		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T8	12		T272	1		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T29	1		T150	1		T92	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17851	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T177	16		T243	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T118	18		T303	15		T147	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	13		T14	10		T124	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T34	1		T35	4		T18	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1091	1			T12	21		T129	19		T130	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T124	8		T19	5		T232	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	14		T123	7		T22	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T127	2		T128	5		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	8		T163	2		T143	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	8		T16	10		T228	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T143	5		T183	10		T59	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T20	10		T123	4		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	14		T17	6		T145	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T35	14		T119	10		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T236	12		T228	1		T305	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T20	5		T128	2		T235	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T35	15		T205	17		T182	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T123	8		T118	6		T19	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	3		T190	6		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T8	8		T168	4		T177	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T118	2		T119	2		T17	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T177	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T295	1		T329	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T136	1		T298	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T60	2		T330	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T14	16		T124	10		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T21	10		T118	1		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T34	1		T19	9		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T22	3		T133	1		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	12		T202	9		T166	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T156	1		T35	11		T18	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	12		T123	1		T22	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T124	11		T19	3		T232	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T167	1		T255	16		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T16	10		T20	2		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	7		T21	5		T163	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T8	7		T125	2		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T16	15		T17	3		T145	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T20	8		T123	1		T195	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T146	12		T125	9		T245	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	6		T35	11		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T226	12		T205	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	12		T123	1		T118	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1511	1			T2	1		T9	11		T12	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17841	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T295	2		T329	17		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T136	13		T298	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T14	10		T124	14		T177	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T118	18		T136	4		T303	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T19	7		T238	15		T308	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T34	1		T18	2		T70	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	13		T202	9		T265	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T35	4		T18	2		T231	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	14		T123	7		T22	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T124	8		T19	5		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T167	1		T255	10		T184	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	10		T127	2		T128	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	8		T163	2		T143	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	8		T125	1		T234	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T16	14		T17	6		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T20	10		T123	4		T195	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T125	12		T331	14		T225	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	5		T35	14		T119	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T205	17		T182	8		T236	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	8		T123	8		T118	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1151	1			T12	21		T16	3		T129	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T21	1		T118	19		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	14		T14	11		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T22	1		T133	1		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1442	1			T2	1		T9	1		T12	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T156	1		T124	9		T19	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	15		T123	8		T22	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T133	1		T191	1		T127	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	9		T163	3		T143	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	9		T16	11		T20	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T143	6		T158	1		T183	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T20	11		T123	5		T125	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T16	15		T21	1		T17	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T35	15		T119	11		T126	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T236	17		T228	2		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	6		T135	1		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T35	16		T226	1		T205	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T123	9		T118	7		T19	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T16	4		T134	1		T190	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T8	9		T272	1		T168	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T29	1		T150	1		T92	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17990	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T177	6		T243	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T21	9		T134	13		T303	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	11		T14	15		T124	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T22	2		T34	1		T35	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1018	1			T9	10		T15	14		T132	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T124	10		T19	2		T232	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	11		T22	13		T125	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T127	2		T128	4		T140	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	6		T163	4		T143	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	6		T16	9		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T59	15		T257	9		T305	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T20	7		T125	1		T195	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	14		T21	4		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	10		T119	14		T234	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T236	2		T228	1		T245	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T20	5		T267	4		T128	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T35	15		T226	11		T242	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T118	4		T19	5		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T16	12		T134	5		T236	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T8	11		T177	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T92	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T299	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T177	15		T243	5		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T295	3		T329	18		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T136	14		T298	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T60	2		T330	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T14	11		T124	15		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T21	1		T118	19		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T34	1		T19	8		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T22	1		T133	1		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	14		T202	10		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T156	1		T35	5		T18	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	15		T123	8		T22	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T124	9		T19	6		T232	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T167	2		T255	11		T184	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T16	11		T20	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	9		T21	1		T163	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T8	9		T125	2		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T16	15		T17	8		T145	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T20	11		T123	5		T195	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T146	1		T125	13		T245	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	6		T35	15		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T226	1		T205	18		T182	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	9		T123	9		T118	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1520	1			T2	1		T9	1		T12	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17981	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T329	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T14	15		T124	9		T177	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T21	9		T134	13		T303	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T19	8		T70	3		T279	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T22	2		T34	1		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	11		T202	8		T166	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T35	10		T231	14		T167	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T14	11		T22	13		T125	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T124	10		T19	2		T232	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T255	15		T173	9		T306	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	9		T20	1		T127	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	6		T21	4		T163	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	6		T125	1		T166	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	14		T17	1		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T20	7		T195	1		T267	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T146	11		T125	8		T245	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	5		T35	10		T119	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T226	11		T236	2		T228	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	11		T118	4		T19	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1142	1			T9	10		T15	14		T16	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10