Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

20

T2

1

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23341

1

T1

20

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

2980

1

T3

25

T14

26

T16

49

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20257

1

T1

20

T3

20

T4

17

auto[1]

6064

1

T2

1

T3

25

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22408

1

T1

20

T2

1

T3

32

auto[1]

3913

1

T3

13

T8

16

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	512	1			T5	2		T10	6		T23	3
values[0]	102	1			T123	9		T190	7		T136	15
values[1]	721	1			T8	20		T16	16		T35	31
values[2]	2874	1			T2	1		T9	11		T12	23
values[3]	816	1			T8	15		T20	18		T156	1
values[4]	581	1			T16	29		T20	2		T21	10
values[5]	520	1			T14	26		T135	1		T124	19
values[6]	599	1			T3	25		T14	26		T134	6
values[7]	609	1			T133	1		T34	1		T143	29
values[8]	613	1			T11	15		T22	3		T134	14
values[9]	880	1			T123	13		T22	28		T133	1
minimum	17494	1			T1	20		T3	20		T4	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	924	1			T8	20		T16	36		T123	9
values[1]	2829	1			T2	1		T9	11		T12	23
values[2]	952	1			T8	15		T16	29		T20	20
values[3]	361	1			T21	10		T133	1		T135	1
values[4]	627	1			T14	26		T134	6		T124	19
values[5]	684	1			T3	25		T14	26		T34	1
values[6]	654	1			T133	1		T146	12		T138	1
values[7]	447	1			T11	15		T22	3		T134	14
values[8]	671	1			T123	13		T22	28		T133	1
values[9]	136	1			T29	1		T242	14		T245	10
minimum	18036	1			T1	20		T3	20		T4	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

3517

1

T3

11

T8

17

T9

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T8	12		T16	13		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T16	10		T21	5		T35	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T2	1		T9	11		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	6		T144	1		T145	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	7		T20	10		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T16	15		T35	11		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T21	10		T133	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T146	13		T137	5		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T124	11		T236	7		T228	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	16		T134	6		T19	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	12		T119	15		T125	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	12		T34	1		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T133	1		T138	1		T166	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T146	12		T276	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	7		T22	3		T134	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T125	9		T127	3		T128	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T123	2		T133	1		T34	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	14		T202	9		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T29	1		T277	2		T278	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T242	4		T245	10		T238	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17866	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T144	1		T168	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	8		T16	3		T123	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	10		T35	15		T183	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T12	21		T129	19		T130	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T20	5		T145	6		T136	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	8		T20	10		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T16	14		T35	14		T118	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T125	2		T182	8		T70	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T146	5		T137	15		T179	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T124	8		T236	12		T228	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	10		T19	7		T195	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	14		T119	10		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	13		T143	14		T19	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T147	9		T255	10		T308	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T234	6		T257	9		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	8		T136	13		T241	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T125	12		T127	2		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T123	11		T34	1		T311	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T22	14		T202	9		T184	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T200	1		T288	6		T280	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T242	10		T238	13		T310	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T118	2		T119	2		T17	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T168	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	497	1			T5	2		T10	6		T23	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T332	1		T333	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T123	1		T190	1		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T166	14		T321	15		T219	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	12		T16	13		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T35	16		T144	1		T166	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T2	1		T9	11		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T16	10		T20	6		T21	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	7		T20	8		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T35	11		T145	3		T19	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T20	2		T21	10		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	15		T118	1		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T135	1		T124	11		T236	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	16		T137	5		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	12		T125	2		T128	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	12		T134	6		T19	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T133	1		T119	15		T166	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	1		T143	15		T276	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	7		T22	3		T134	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T127	3		T128	5		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T123	2		T133	1		T34	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T22	14		T202	9		T125	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17354	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T288	6		T334	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T123	8		T190	6		T136	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T219	10		T271	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	8		T16	3		T124	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T35	15		T255	14		T335	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T12	21		T129	19		T130	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T16	10		T20	5		T136	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	8		T20	10		T35	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T35	14		T145	6		T19	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T18	2		T125	2		T182	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T16	14		T118	18		T146	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T124	8		T236	12		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	10		T137	15		T195	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T14	14		T125	1		T128	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	13		T19	12		T257	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T119	10		T233	16		T279	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T143	14		T227	7		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	8		T140	19		T54	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T127	2		T128	5		T159	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T123	11		T34	1		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	14		T202	9		T125	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T119	2		T17	6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	9		T16	4		T123	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T16	11		T21	1		T35	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T2	1		T9	1		T12	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T20	6		T144	1		T145	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	9		T20	12		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T16	15		T35	15		T118	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T21	1		T133	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T146	6		T137	16		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T124	9		T236	17		T228	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	11		T134	1		T19	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	15		T119	11		T125	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	14		T34	1		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T133	1		T138	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T146	1		T276	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	9		T22	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T125	13		T127	3		T128	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T123	13		T133	1		T34	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	15		T202	10		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T29	1		T277	2		T278	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T242	11		T245	1		T238	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18008	1			T1	20		T3	20		T4	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T144	1		T168	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	11		T16	12		T163	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T16	9		T21	4		T35	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T9	10		T15	14		T132	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T20	5		T145	2		T226	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	6		T20	8		T228	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T16	14		T35	10		T19	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T21	9		T125	5		T70	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T146	12		T137	4		T140	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T124	10		T236	2		T228	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	15		T134	5		T19	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	11		T119	14		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	11		T143	14		T19	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T166	7		T255	15		T279	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T146	11		T234	2		T257	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	6		T22	2		T134	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T125	8		T127	2		T128	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T34	1		T55	4		T286	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T22	13		T202	8		T184	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T278	11		T200	2		T288	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T242	3		T245	9		T274	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T259	11		T197	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	503	1			T5	2		T10	6		T23	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T332	1		T333	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T123	9		T190	7		T136	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T166	1		T321	1		T219	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	9		T16	4		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T35	16		T144	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T2	1		T9	1		T12	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	11		T20	6		T21	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T8	9		T20	11		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T35	15		T145	7		T19	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T20	1		T21	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T16	15		T118	19		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T135	1		T124	9		T236	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	11		T137	16		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	15		T125	2		T128	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	14		T134	1		T19	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T133	1		T119	11		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	1		T143	15		T276	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	9		T22	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T127	3		T128	6		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T123	13		T133	1		T34	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T22	15		T202	10		T125	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T1	20		T3	20		T4	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T288	2		T334	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T309	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T166	13		T321	14		T219	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	11		T16	12		T124	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	15		T166	11		T139	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T9	10		T15	14		T132	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	9		T20	5		T21	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	6		T20	7		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T35	10		T145	2		T19	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T20	1		T21	9		T125	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	14		T146	12		T139	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T124	10		T236	2		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T14	15		T137	4		T195	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T14	11		T125	1		T128	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	11		T134	5		T19	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T119	14		T166	7		T233	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T143	14		T234	2		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	6		T22	2		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T127	2		T128	4		T77	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T34	1		T55	4		T286	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T22	13		T202	8		T125	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

20

T2

1

T3

34

auto[1]

auto[0]

3517

1

T3

11

T8

17

T9

10