Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.58 98.98 95.69 100.00 100.00 98.18 98.64 91.59


Total test records in report: 913
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T36 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1641616578 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:49 PM PST 24 676002990 ps
T37 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1933674027 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:51 PM PST 24 637272847 ps
T38 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2622317211 Feb 18 12:38:33 PM PST 24 Feb 18 12:38:38 PM PST 24 1007424018 ps
T792 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4025497799 Feb 18 12:34:35 PM PST 24 Feb 18 12:34:44 PM PST 24 502215561 ps
T73 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1526461532 Feb 18 12:34:34 PM PST 24 Feb 18 12:34:52 PM PST 24 3943715436 ps
T793 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2974715537 Feb 18 12:34:45 PM PST 24 Feb 18 12:34:54 PM PST 24 513992822 ps
T63 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4006043466 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:52 PM PST 24 483408400 ps
T87 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.279500787 Feb 18 12:34:41 PM PST 24 Feb 18 12:35:09 PM PST 24 8079018886 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2599287873 Feb 18 12:34:36 PM PST 24 Feb 18 12:34:46 PM PST 24 964508920 ps
T794 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.375674445 Feb 18 12:34:55 PM PST 24 Feb 18 12:35:00 PM PST 24 444983630 ps
T30 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3572369446 Feb 18 12:34:32 PM PST 24 Feb 18 12:35:38 PM PST 24 26249603077 ps
T64 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1878840802 Feb 18 12:34:40 PM PST 24 Feb 18 12:34:48 PM PST 24 490200149 ps
T795 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3733126826 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:04 PM PST 24 323807051 ps
T98 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.450908923 Feb 18 12:34:31 PM PST 24 Feb 18 12:34:40 PM PST 24 430954649 ps
T31 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.236791790 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:55 PM PST 24 2084859354 ps
T111 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2416007568 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:49 PM PST 24 1967882634 ps
T32 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2733140807 Feb 18 12:34:49 PM PST 24 Feb 18 12:35:07 PM PST 24 3536793110 ps
T65 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2671251859 Feb 18 12:34:45 PM PST 24 Feb 18 12:34:53 PM PST 24 752701826 ps
T112 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1453388737 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:53 PM PST 24 4418682294 ps
T74 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.865771247 Feb 18 12:34:46 PM PST 24 Feb 18 12:34:57 PM PST 24 778005074 ps
T75 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3451520886 Feb 18 12:38:31 PM PST 24 Feb 18 12:38:35 PM PST 24 423108950 ps
T85 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1539876491 Feb 18 12:34:40 PM PST 24 Feb 18 12:35:05 PM PST 24 7750374987 ps
T796 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3222304835 Feb 18 12:34:54 PM PST 24 Feb 18 12:34:59 PM PST 24 334915927 ps
T797 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3053201504 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:49 PM PST 24 498403772 ps
T350 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1452646366 Feb 18 12:34:44 PM PST 24 Feb 18 12:34:58 PM PST 24 8802604937 ps
T86 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1565455330 Feb 18 12:34:52 PM PST 24 Feb 18 12:35:00 PM PST 24 748255456 ps
T113 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3879695428 Feb 18 12:34:44 PM PST 24 Feb 18 12:34:58 PM PST 24 4893522164 ps
T798 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2358978245 Feb 18 12:34:44 PM PST 24 Feb 18 12:34:52 PM PST 24 301573950 ps
T117 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2414416624 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:52 PM PST 24 1072355238 ps
T799 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1040511425 Feb 18 12:34:56 PM PST 24 Feb 18 12:35:00 PM PST 24 458355279 ps
T114 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2165119665 Feb 18 12:34:30 PM PST 24 Feb 18 12:34:40 PM PST 24 506049137 ps
T800 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2400967652 Feb 18 12:34:48 PM PST 24 Feb 18 12:34:58 PM PST 24 411803799 ps
T801 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2969920174 Feb 18 12:35:06 PM PST 24 Feb 18 12:35:09 PM PST 24 304840616 ps
T99 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1683059511 Feb 18 12:34:31 PM PST 24 Feb 18 12:34:40 PM PST 24 1287245927 ps
T802 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2398210245 Feb 18 12:34:32 PM PST 24 Feb 18 12:34:42 PM PST 24 1019676436 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4045940766 Feb 18 12:34:31 PM PST 24 Feb 18 12:34:52 PM PST 24 4009357073 ps
T803 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1002020311 Feb 18 12:34:56 PM PST 24 Feb 18 12:35:01 PM PST 24 524018907 ps
T804 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2792686472 Feb 18 12:34:53 PM PST 24 Feb 18 12:35:09 PM PST 24 2658596558 ps
T805 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2001905270 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:54 PM PST 24 4092605224 ps
T806 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4289799931 Feb 18 12:34:45 PM PST 24 Feb 18 12:34:54 PM PST 24 451378319 ps
T807 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2281736470 Feb 18 12:34:30 PM PST 24 Feb 18 12:34:39 PM PST 24 447359672 ps
T808 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2833080379 Feb 18 12:34:55 PM PST 24 Feb 18 12:35:00 PM PST 24 340706877 ps
T809 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1443670738 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:04 PM PST 24 380449255 ps
T810 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1028967916 Feb 18 12:34:46 PM PST 24 Feb 18 12:34:54 PM PST 24 389960854 ps
T120 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.436820446 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:49 PM PST 24 811112311 ps
T811 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2279118372 Feb 18 12:34:54 PM PST 24 Feb 18 12:34:59 PM PST 24 495217188 ps
T812 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.336070207 Feb 18 12:34:39 PM PST 24 Feb 18 12:34:53 PM PST 24 2405854445 ps
T813 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2744020337 Feb 18 12:34:49 PM PST 24 Feb 18 12:34:57 PM PST 24 445937129 ps
T814 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2097740692 Feb 18 12:34:31 PM PST 24 Feb 18 12:34:41 PM PST 24 1388397647 ps
T351 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1246284305 Feb 18 12:34:39 PM PST 24 Feb 18 12:35:04 PM PST 24 7707758598 ps
T815 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1661214688 Feb 18 12:34:45 PM PST 24 Feb 18 12:34:53 PM PST 24 395848788 ps
T816 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4071460310 Feb 18 12:34:47 PM PST 24 Feb 18 12:34:56 PM PST 24 313754593 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3544948136 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:50 PM PST 24 749660865 ps
T818 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1642190651 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:51 PM PST 24 509179667 ps
T352 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3349652907 Feb 18 12:34:53 PM PST 24 Feb 18 12:35:04 PM PST 24 8108656563 ps
T100 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.568167413 Feb 18 12:34:38 PM PST 24 Feb 18 12:34:46 PM PST 24 501700301 ps
T101 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3938428164 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:50 PM PST 24 369495198 ps
T819 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3436441581 Feb 18 12:34:40 PM PST 24 Feb 18 12:34:47 PM PST 24 463835083 ps
T102 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1532667982 Feb 18 12:34:40 PM PST 24 Feb 18 12:34:47 PM PST 24 408126227 ps
T353 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3648438900 Feb 18 12:34:31 PM PST 24 Feb 18 12:34:46 PM PST 24 8522054831 ps
T820 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2137362889 Feb 18 12:34:55 PM PST 24 Feb 18 12:35:00 PM PST 24 309033453 ps
T821 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2712747305 Feb 18 12:34:35 PM PST 24 Feb 18 12:34:46 PM PST 24 1283172337 ps
T822 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1893422439 Feb 18 12:34:49 PM PST 24 Feb 18 12:35:05 PM PST 24 3917845703 ps
T354 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.920480450 Feb 18 12:34:40 PM PST 24 Feb 18 12:34:50 PM PST 24 4072540406 ps
T823 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2691307064 Feb 18 12:34:36 PM PST 24 Feb 18 12:34:44 PM PST 24 429534415 ps
T103 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3941834557 Feb 18 12:34:46 PM PST 24 Feb 18 12:34:56 PM PST 24 314160683 ps
T824 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3701090805 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:50 PM PST 24 361673629 ps
T825 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3012487855 Feb 18 12:34:37 PM PST 24 Feb 18 12:34:44 PM PST 24 307737235 ps
T826 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1589339085 Feb 18 12:34:57 PM PST 24 Feb 18 12:35:02 PM PST 24 491431227 ps
T827 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3928345715 Feb 18 12:34:45 PM PST 24 Feb 18 12:34:54 PM PST 24 515729469 ps
T828 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1463417715 Feb 18 12:34:49 PM PST 24 Feb 18 12:35:07 PM PST 24 4539306887 ps
T829 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.619032642 Feb 18 12:34:47 PM PST 24 Feb 18 12:34:56 PM PST 24 287738547 ps
T104 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1986668171 Feb 18 12:34:38 PM PST 24 Feb 18 12:34:46 PM PST 24 555491335 ps
T105 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3330237938 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:52 PM PST 24 913879875 ps
T830 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3847511068 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:51 PM PST 24 727851658 ps
T831 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2145333648 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:51 PM PST 24 4337558932 ps
T106 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3296088329 Feb 18 12:34:36 PM PST 24 Feb 18 12:34:47 PM PST 24 1102424526 ps
T832 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.944565247 Feb 18 12:34:29 PM PST 24 Feb 18 12:34:38 PM PST 24 329805456 ps
T833 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.186896860 Feb 18 12:34:53 PM PST 24 Feb 18 12:34:59 PM PST 24 310499168 ps
T834 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4022975120 Feb 18 12:34:29 PM PST 24 Feb 18 12:34:45 PM PST 24 3498374085 ps
T835 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1456996272 Feb 18 12:34:46 PM PST 24 Feb 18 12:34:57 PM PST 24 474044870 ps
T836 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2394128533 Feb 18 12:34:50 PM PST 24 Feb 18 12:35:00 PM PST 24 697791054 ps
T837 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2971247828 Feb 18 12:34:45 PM PST 24 Feb 18 12:34:54 PM PST 24 366970336 ps
T838 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1735440553 Feb 18 12:34:31 PM PST 24 Feb 18 12:34:50 PM PST 24 4324783423 ps
T839 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2609987510 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:50 PM PST 24 380837751 ps
T840 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.915649079 Feb 18 12:34:50 PM PST 24 Feb 18 12:35:16 PM PST 24 7791306137 ps
T107 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1305711142 Feb 18 12:34:34 PM PST 24 Feb 18 12:35:04 PM PST 24 24028457077 ps
T841 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1540563177 Feb 18 12:34:49 PM PST 24 Feb 18 12:34:58 PM PST 24 604673698 ps
T842 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.515815303 Feb 18 12:34:49 PM PST 24 Feb 18 12:34:57 PM PST 24 525860004 ps
T108 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1476445189 Feb 18 12:34:29 PM PST 24 Feb 18 12:34:39 PM PST 24 526875327 ps
T843 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2461272432 Feb 18 12:34:32 PM PST 24 Feb 18 12:34:40 PM PST 24 334792547 ps
T844 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.362469138 Feb 18 12:34:47 PM PST 24 Feb 18 12:34:56 PM PST 24 334087204 ps
T845 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1547233875 Feb 18 12:34:54 PM PST 24 Feb 18 12:35:03 PM PST 24 623486554 ps
T846 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.736479653 Feb 18 12:34:46 PM PST 24 Feb 18 12:34:56 PM PST 24 527290100 ps
T847 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3875611260 Feb 18 12:34:40 PM PST 24 Feb 18 12:34:54 PM PST 24 1893657395 ps
T109 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3245529220 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:49 PM PST 24 331298067 ps
T848 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2671253525 Feb 18 12:34:54 PM PST 24 Feb 18 12:35:00 PM PST 24 1329902999 ps
T849 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1775940418 Feb 18 12:35:02 PM PST 24 Feb 18 12:35:07 PM PST 24 522558319 ps
T850 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.157733102 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:54 PM PST 24 2174110731 ps
T851 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.232408987 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:51 PM PST 24 616314217 ps
T852 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3306167322 Feb 18 12:34:40 PM PST 24 Feb 18 12:34:55 PM PST 24 8118981302 ps
T853 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2100302764 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:51 PM PST 24 392995405 ps
T854 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2272016276 Feb 18 12:34:49 PM PST 24 Feb 18 12:34:57 PM PST 24 353644837 ps
T855 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.278650499 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:57 PM PST 24 4207082427 ps
T856 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4158046760 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:04 PM PST 24 509469869 ps
T110 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4004976125 Feb 18 12:34:28 PM PST 24 Feb 18 12:34:38 PM PST 24 345649505 ps
T857 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4137527070 Feb 18 12:34:49 PM PST 24 Feb 18 12:34:58 PM PST 24 447509196 ps
T858 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1011614194 Feb 18 12:34:56 PM PST 24 Feb 18 12:35:01 PM PST 24 397916972 ps
T859 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4041272585 Feb 18 12:34:52 PM PST 24 Feb 18 12:34:58 PM PST 24 294062919 ps
T860 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1091432111 Feb 18 12:34:29 PM PST 24 Feb 18 12:34:40 PM PST 24 525155571 ps
T861 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2603707169 Feb 18 12:34:32 PM PST 24 Feb 18 12:34:41 PM PST 24 623614287 ps
T862 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2615740781 Feb 18 12:34:57 PM PST 24 Feb 18 12:35:02 PM PST 24 322883448 ps
T863 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2036874203 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:48 PM PST 24 304264634 ps
T864 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.211346517 Feb 18 12:34:34 PM PST 24 Feb 18 12:35:16 PM PST 24 26828797408 ps
T865 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1258977631 Feb 18 12:34:49 PM PST 24 Feb 18 12:34:56 PM PST 24 345923442 ps
T866 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2660691191 Feb 18 12:35:02 PM PST 24 Feb 18 12:35:07 PM PST 24 366354180 ps
T867 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4128228420 Feb 18 12:34:38 PM PST 24 Feb 18 12:34:47 PM PST 24 900449797 ps
T868 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2230197661 Feb 18 12:34:32 PM PST 24 Feb 18 12:34:50 PM PST 24 27347201112 ps
T869 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1288737359 Feb 18 12:34:43 PM PST 24 Feb 18 12:35:11 PM PST 24 5327515176 ps
T870 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2748107423 Feb 18 12:34:54 PM PST 24 Feb 18 12:35:02 PM PST 24 4445978651 ps
T871 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.439228986 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:06 PM PST 24 563698677 ps
T872 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.6398156 Feb 18 12:34:38 PM PST 24 Feb 18 12:34:47 PM PST 24 512552289 ps
T873 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.762010251 Feb 18 12:34:45 PM PST 24 Feb 18 12:34:55 PM PST 24 589855687 ps
T874 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2250578373 Feb 18 12:34:49 PM PST 24 Feb 18 12:35:01 PM PST 24 4482430199 ps
T875 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.653835946 Feb 18 12:34:28 PM PST 24 Feb 18 12:34:49 PM PST 24 4534271891 ps
T876 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2548836645 Feb 18 12:34:56 PM PST 24 Feb 18 12:35:01 PM PST 24 375292397 ps
T877 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1263113402 Feb 18 12:34:44 PM PST 24 Feb 18 12:34:53 PM PST 24 464957329 ps
T878 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2104405286 Feb 18 12:34:40 PM PST 24 Feb 18 12:34:49 PM PST 24 6034500782 ps
T879 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3045908097 Feb 18 12:34:55 PM PST 24 Feb 18 12:35:00 PM PST 24 411434469 ps
T880 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4068375884 Feb 18 12:34:45 PM PST 24 Feb 18 12:34:53 PM PST 24 316175411 ps
T881 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3420060919 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:50 PM PST 24 521339882 ps
T882 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2087305536 Feb 18 12:34:59 PM PST 24 Feb 18 12:35:05 PM PST 24 457768123 ps
T883 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.482142414 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:54 PM PST 24 8747731165 ps
T884 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.476996230 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:50 PM PST 24 525153377 ps
T885 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2230075474 Feb 18 12:34:47 PM PST 24 Feb 18 12:35:05 PM PST 24 8899384346 ps
T886 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2886122295 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:50 PM PST 24 1072123415 ps
T887 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.469873114 Feb 18 12:34:57 PM PST 24 Feb 18 12:35:03 PM PST 24 526938961 ps
T888 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3680392428 Feb 18 12:34:34 PM PST 24 Feb 18 12:34:44 PM PST 24 895839390 ps
T889 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1045122989 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:51 PM PST 24 892147829 ps
T890 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2379956717 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:50 PM PST 24 440192888 ps
T891 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2035048890 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:52 PM PST 24 4599101178 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2167851888 Feb 18 12:34:40 PM PST 24 Feb 18 12:34:48 PM PST 24 447333507 ps
T893 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.681784277 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:52 PM PST 24 2319177180 ps
T894 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2185478785 Feb 18 12:34:53 PM PST 24 Feb 18 12:34:59 PM PST 24 539033205 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.618952639 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:50 PM PST 24 723727735 ps
T896 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4245327055 Feb 18 12:34:30 PM PST 24 Feb 18 12:34:39 PM PST 24 911429179 ps
T897 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1460017837 Feb 18 12:34:40 PM PST 24 Feb 18 12:34:53 PM PST 24 7991334074 ps
T898 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3172938855 Feb 18 12:35:01 PM PST 24 Feb 18 12:35:07 PM PST 24 493955369 ps
T899 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2213678564 Feb 18 12:34:39 PM PST 24 Feb 18 12:34:53 PM PST 24 4328586417 ps
T900 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1716471641 Feb 18 12:34:45 PM PST 24 Feb 18 12:34:56 PM PST 24 606683932 ps
T901 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.332380240 Feb 18 12:34:31 PM PST 24 Feb 18 12:34:41 PM PST 24 644131268 ps
T902 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2098742232 Feb 18 12:34:44 PM PST 24 Feb 18 12:34:52 PM PST 24 290846850 ps
T903 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1126406290 Feb 18 12:34:31 PM PST 24 Feb 18 12:34:40 PM PST 24 473473214 ps
T904 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2414689701 Feb 18 12:34:50 PM PST 24 Feb 18 12:34:58 PM PST 24 440534203 ps
T905 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3814737687 Feb 18 12:34:30 PM PST 24 Feb 18 12:34:41 PM PST 24 2466572806 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1158985116 Feb 18 12:34:28 PM PST 24 Feb 18 12:34:42 PM PST 24 1113734422 ps
T907 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2031703149 Feb 18 12:34:41 PM PST 24 Feb 18 12:34:59 PM PST 24 8555930301 ps
T908 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2076765838 Feb 18 12:34:29 PM PST 24 Feb 18 12:34:38 PM PST 24 292651941 ps
T909 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.488403062 Feb 18 12:34:43 PM PST 24 Feb 18 12:34:51 PM PST 24 442185941 ps
T910 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1240617359 Feb 18 12:34:38 PM PST 24 Feb 18 12:34:46 PM PST 24 429120694 ps
T911 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.41582416 Feb 18 12:34:39 PM PST 24 Feb 18 12:34:49 PM PST 24 640224183 ps
T912 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3723130190 Feb 18 12:34:42 PM PST 24 Feb 18 12:34:50 PM PST 24 386626861 ps
T913 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3106053049 Feb 18 12:34:49 PM PST 24 Feb 18 12:34:58 PM PST 24 504243415 ps

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3221235301
Short name T3
Test name
Test status
Simulation time 173326684244 ps
CPU time 104.7 seconds
Started Feb 18 01:20:58 PM PST 24
Finished Feb 18 01:22:44 PM PST 24
Peak memory 201424 kb
Host smart-d1383df8-9c53-4cd2-a866-88f2d3da7987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221235301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3221235301
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.541691226
Short name T23
Test name
Test status
Simulation time 128176577382 ps
CPU time 456.11 seconds
Started Feb 18 01:15:47 PM PST 24
Finished Feb 18 01:23:24 PM PST 24
Peak memory 201820 kb
Host smart-e82731de-d8ac-4181-998b-2c0d1708d0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541691226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.541691226
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.623009694
Short name T16
Test name
Test status
Simulation time 493353568818 ps
CPU time 508.74 seconds
Started Feb 18 01:15:48 PM PST 24
Finished Feb 18 01:24:18 PM PST 24
Peak memory 201440 kb
Host smart-59f0198c-87da-4dd3-9dda-261910468639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623009694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.623009694
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3804786459
Short name T17
Test name
Test status
Simulation time 196871160879 ps
CPU time 165.22 seconds
Started Feb 18 01:16:37 PM PST 24
Finished Feb 18 01:19:25 PM PST 24
Peak memory 217436 kb
Host smart-8a132aee-5a14-4e62-96f7-6016c8530436
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804786459 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3804786459
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1637861350
Short name T35
Test name
Test status
Simulation time 488048055978 ps
CPU time 126.77 seconds
Started Feb 18 01:21:47 PM PST 24
Finished Feb 18 01:23:54 PM PST 24
Peak memory 201456 kb
Host smart-92400a06-3d3c-4102-b142-20a9d57a1972
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637861350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1637861350
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2640561910
Short name T18
Test name
Test status
Simulation time 419059539435 ps
CPU time 258.07 seconds
Started Feb 18 01:21:19 PM PST 24
Finished Feb 18 01:25:38 PM PST 24
Peak memory 210144 kb
Host smart-0b7e6ccf-8c07-44b0-83f0-f278904f9949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640561910 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2640561910
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2041793404
Short name T20
Test name
Test status
Simulation time 502015886034 ps
CPU time 207.74 seconds
Started Feb 18 01:21:05 PM PST 24
Finished Feb 18 01:24:34 PM PST 24
Peak memory 201496 kb
Host smart-5dd898f1-bc4a-4245-8947-28696b2a2a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041793404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2041793404
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3807533036
Short name T34
Test name
Test status
Simulation time 56170478496 ps
CPU time 37.16 seconds
Started Feb 18 01:19:41 PM PST 24
Finished Feb 18 01:20:19 PM PST 24
Peak memory 201460 kb
Host smart-d7268f3c-320c-49c4-b794-4952663364da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807533036 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3807533036
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.189769171
Short name T257
Test name
Test status
Simulation time 498944486322 ps
CPU time 143.22 seconds
Started Feb 18 01:19:05 PM PST 24
Finished Feb 18 01:21:29 PM PST 24
Peak memory 201460 kb
Host smart-f1fa8261-7780-472c-987c-2581c7eb9678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189769171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
189769171
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2717260214
Short name T125
Test name
Test status
Simulation time 506254793011 ps
CPU time 1192.8 seconds
Started Feb 18 01:19:21 PM PST 24
Finished Feb 18 01:39:15 PM PST 24
Peak memory 201460 kb
Host smart-1f77c181-341f-4037-8a3d-401111461ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717260214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2717260214
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2622317211
Short name T38
Test name
Test status
Simulation time 1007424018 ps
CPU time 2.59 seconds
Started Feb 18 12:38:33 PM PST 24
Finished Feb 18 12:38:38 PM PST 24
Peak memory 201168 kb
Host smart-2c6d61a6-2c59-42ef-99b2-dc70641493d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622317211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2622317211
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3852749573
Short name T140
Test name
Test status
Simulation time 493553505862 ps
CPU time 1170.59 seconds
Started Feb 18 01:15:11 PM PST 24
Finished Feb 18 01:34:43 PM PST 24
Peak memory 201396 kb
Host smart-4a98f436-309b-4618-919b-8059e88a7d19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852749573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3852749573
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3153631834
Short name T123
Test name
Test status
Simulation time 492189483562 ps
CPU time 284.65 seconds
Started Feb 18 01:14:51 PM PST 24
Finished Feb 18 01:19:37 PM PST 24
Peak memory 201456 kb
Host smart-f0459ada-4b3a-4f84-af34-ff1f81d0d184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153631834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3153631834
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1282380066
Short name T46
Test name
Test status
Simulation time 4292840069 ps
CPU time 5.62 seconds
Started Feb 18 01:14:58 PM PST 24
Finished Feb 18 01:15:05 PM PST 24
Peak memory 216344 kb
Host smart-10c64aa6-f83e-4e49-bf36-e0ecb060bffc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282380066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1282380066
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.356466008
Short name T124
Test name
Test status
Simulation time 318843656152 ps
CPU time 209.81 seconds
Started Feb 18 01:21:10 PM PST 24
Finished Feb 18 01:24:41 PM PST 24
Peak memory 201496 kb
Host smart-c8a68b39-c632-4d95-bff7-cf77cd09c57c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356466008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.356466008
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1190238133
Short name T8
Test name
Test status
Simulation time 319781461445 ps
CPU time 540.8 seconds
Started Feb 18 01:19:05 PM PST 24
Finished Feb 18 01:28:06 PM PST 24
Peak memory 201428 kb
Host smart-995f0374-e604-4165-9279-cb0ba912ca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190238133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1190238133
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2541741660
Short name T238
Test name
Test status
Simulation time 503149438177 ps
CPU time 511.02 seconds
Started Feb 18 01:15:03 PM PST 24
Finished Feb 18 01:23:37 PM PST 24
Peak memory 201420 kb
Host smart-e630df88-032b-49e2-9433-2fbbba833f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541741660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2541741660
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3181959841
Short name T128
Test name
Test status
Simulation time 323172115541 ps
CPU time 512.01 seconds
Started Feb 18 01:21:05 PM PST 24
Finished Feb 18 01:29:39 PM PST 24
Peak memory 201496 kb
Host smart-e1258eab-186d-4dc0-9809-d95e3a402243
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181959841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3181959841
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1850606497
Short name T54
Test name
Test status
Simulation time 333050641850 ps
CPU time 726.74 seconds
Started Feb 18 01:14:57 PM PST 24
Finished Feb 18 01:27:04 PM PST 24
Peak memory 201504 kb
Host smart-c9949d71-32ac-463d-ab07-7a1af31ec4c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850606497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1850606497
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2265081531
Short name T97
Test name
Test status
Simulation time 380147748 ps
CPU time 0.8 seconds
Started Feb 18 12:34:47 PM PST 24
Finished Feb 18 12:34:55 PM PST 24
Peak memory 200904 kb
Host smart-a4605e2b-dfc2-47bc-a588-65626217227d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265081531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2265081531
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1190853808
Short name T15
Test name
Test status
Simulation time 331244974037 ps
CPU time 740.85 seconds
Started Feb 18 01:17:11 PM PST 24
Finished Feb 18 01:29:32 PM PST 24
Peak memory 201424 kb
Host smart-b2e5b7ec-93bd-4cf5-8b16-8c6da97e67d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190853808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1190853808
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1226106893
Short name T152
Test name
Test status
Simulation time 491208362818 ps
CPU time 1086.69 seconds
Started Feb 18 01:20:01 PM PST 24
Finished Feb 18 01:38:09 PM PST 24
Peak memory 201524 kb
Host smart-89f27d97-7104-4349-a95b-ca5a9c4a12f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226106893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1226106893
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1089797887
Short name T196
Test name
Test status
Simulation time 147436138568 ps
CPU time 183.04 seconds
Started Feb 18 01:22:11 PM PST 24
Finished Feb 18 01:25:15 PM PST 24
Peak memory 211080 kb
Host smart-4cd1d0c9-f008-4cf2-a100-a1874c1551d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089797887 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1089797887
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2288202595
Short name T166
Test name
Test status
Simulation time 486523401112 ps
CPU time 225.47 seconds
Started Feb 18 01:22:13 PM PST 24
Finished Feb 18 01:26:00 PM PST 24
Peak memory 201404 kb
Host smart-5408a3e5-487b-4724-bcd3-532cce5521d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288202595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2288202595
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2585994832
Short name T236
Test name
Test status
Simulation time 285758678855 ps
CPU time 191.72 seconds
Started Feb 18 01:22:44 PM PST 24
Finished Feb 18 01:25:56 PM PST 24
Peak memory 210032 kb
Host smart-ac63cfb7-a5e3-4031-8a22-bddcbf603a9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585994832 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2585994832
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.790002103
Short name T255
Test name
Test status
Simulation time 494509229008 ps
CPU time 286.57 seconds
Started Feb 18 01:15:53 PM PST 24
Finished Feb 18 01:20:41 PM PST 24
Peak memory 201484 kb
Host smart-10972d42-08da-402c-b914-8a94476e67c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790002103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.790002103
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1765071578
Short name T248
Test name
Test status
Simulation time 334856388627 ps
CPU time 423.25 seconds
Started Feb 18 01:16:35 PM PST 24
Finished Feb 18 01:23:40 PM PST 24
Peak memory 201488 kb
Host smart-9b53cf28-6742-4253-825a-76608b14879d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765071578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1765071578
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3179497362
Short name T70
Test name
Test status
Simulation time 331635854690 ps
CPU time 689.55 seconds
Started Feb 18 01:18:14 PM PST 24
Finished Feb 18 01:29:45 PM PST 24
Peak memory 201496 kb
Host smart-4c42ebe4-ea4a-49c8-acaa-a508e67673cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179497362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3179497362
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3717659830
Short name T378
Test name
Test status
Simulation time 400959968 ps
CPU time 0.86 seconds
Started Feb 18 01:14:57 PM PST 24
Finished Feb 18 01:14:59 PM PST 24
Peak memory 201148 kb
Host smart-577aa935-a50c-434d-a87d-a888bb1300bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717659830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3717659830
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.236791790
Short name T31
Test name
Test status
Simulation time 2084859354 ps
CPU time 5.49 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:55 PM PST 24
Peak memory 199692 kb
Host smart-4185d1cd-0f6f-4fd7-b083-c1de138371f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236791790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.236791790
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4142738631
Short name T266
Test name
Test status
Simulation time 1603005002064 ps
CPU time 2241.86 seconds
Started Feb 18 01:22:44 PM PST 24
Finished Feb 18 02:00:07 PM PST 24
Peak memory 201816 kb
Host smart-fd669a9d-34d6-4bf0-90fb-1bd9ee6e07e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142738631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4142738631
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.4227810245
Short name T197
Test name
Test status
Simulation time 476460153872 ps
CPU time 364.12 seconds
Started Feb 18 01:15:55 PM PST 24
Finished Feb 18 01:22:00 PM PST 24
Peak memory 210076 kb
Host smart-6eb3f5b9-5918-4a99-9dc8-20864c0bf246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227810245 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.4227810245
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1246284305
Short name T351
Test name
Test status
Simulation time 7707758598 ps
CPU time 19.59 seconds
Started Feb 18 12:34:39 PM PST 24
Finished Feb 18 12:35:04 PM PST 24
Peak memory 201260 kb
Host smart-f725e3ce-b0c7-4028-900f-df24d2b6f67b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246284305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1246284305
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2094859026
Short name T146
Test name
Test status
Simulation time 321326362921 ps
CPU time 193.62 seconds
Started Feb 18 01:14:52 PM PST 24
Finished Feb 18 01:18:08 PM PST 24
Peak memory 201360 kb
Host smart-751837ae-691c-49f2-ab26-2fc1f5585be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094859026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2094859026
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4160997356
Short name T263
Test name
Test status
Simulation time 331413702428 ps
CPU time 746.46 seconds
Started Feb 18 01:16:35 PM PST 24
Finished Feb 18 01:29:03 PM PST 24
Peak memory 201372 kb
Host smart-100ce51c-9e48-4fa0-a759-c473ab3cba95
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160997356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4160997356
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2516340075
Short name T270
Test name
Test status
Simulation time 331009736826 ps
CPU time 724.7 seconds
Started Feb 18 01:17:03 PM PST 24
Finished Feb 18 01:29:08 PM PST 24
Peak memory 201488 kb
Host smart-74870ea8-2ea7-4a1d-83e5-5960537938dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516340075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2516340075
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3874806411
Short name T92
Test name
Test status
Simulation time 491880826907 ps
CPU time 1074.89 seconds
Started Feb 18 01:16:14 PM PST 24
Finished Feb 18 01:34:11 PM PST 24
Peak memory 201412 kb
Host smart-043f75ff-6317-4e4a-9ece-8316efacbeca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874806411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3874806411
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3964446669
Short name T277
Test name
Test status
Simulation time 488402723964 ps
CPU time 589.71 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:27:13 PM PST 24
Peak memory 201488 kb
Host smart-9ce44cf2-c24c-44ef-ba80-f71970f4d20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964446669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3964446669
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.4137611924
Short name T22
Test name
Test status
Simulation time 328021278471 ps
CPU time 807.87 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:28:36 PM PST 24
Peak memory 201516 kb
Host smart-a8824057-c76c-4e55-99c2-b316283a9b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137611924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.4137611924
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.532076914
Short name T234
Test name
Test status
Simulation time 487639884440 ps
CPU time 1097.4 seconds
Started Feb 18 01:20:12 PM PST 24
Finished Feb 18 01:38:32 PM PST 24
Peak memory 201388 kb
Host smart-cd6eebdd-98c2-480a-bcfa-ed974a487b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532076914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.532076914
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3625926808
Short name T136
Test name
Test status
Simulation time 491737130836 ps
CPU time 187.43 seconds
Started Feb 18 01:19:52 PM PST 24
Finished Feb 18 01:23:01 PM PST 24
Peak memory 201432 kb
Host smart-b9992f24-60c9-4def-8501-90211420d1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625926808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3625926808
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2898850732
Short name T325
Test name
Test status
Simulation time 184899871795 ps
CPU time 191.97 seconds
Started Feb 18 01:15:39 PM PST 24
Finished Feb 18 01:18:54 PM PST 24
Peak memory 201528 kb
Host smart-ee0d2018-768a-491e-a47d-da18c71c2257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898850732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2898850732
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.948789547
Short name T306
Test name
Test status
Simulation time 325068680271 ps
CPU time 171.67 seconds
Started Feb 18 01:17:15 PM PST 24
Finished Feb 18 01:20:07 PM PST 24
Peak memory 201512 kb
Host smart-cb60d2d4-1595-4226-8be1-a8c75cc4981a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948789547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.948789547
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.661563631
Short name T155
Test name
Test status
Simulation time 135077168981 ps
CPU time 536.95 seconds
Started Feb 18 01:22:43 PM PST 24
Finished Feb 18 01:31:41 PM PST 24
Peak memory 201756 kb
Host smart-040ae9de-3c68-49af-8a11-cc30a8a49d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661563631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.661563631
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3637164576
Short name T260
Test name
Test status
Simulation time 185739516356 ps
CPU time 273.49 seconds
Started Feb 18 01:15:41 PM PST 24
Finished Feb 18 01:20:17 PM PST 24
Peak memory 201364 kb
Host smart-b33ec364-f8fd-4fa7-807f-c9162faa9693
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637164576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3637164576
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3375813882
Short name T296
Test name
Test status
Simulation time 324601971553 ps
CPU time 152.71 seconds
Started Feb 18 01:15:41 PM PST 24
Finished Feb 18 01:18:16 PM PST 24
Peak memory 201420 kb
Host smart-e9871930-aa0b-4c8b-8626-8f9b3557b048
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375813882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3375813882
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.655657188
Short name T177
Test name
Test status
Simulation time 486626196628 ps
CPU time 179.34 seconds
Started Feb 18 01:19:53 PM PST 24
Finished Feb 18 01:22:53 PM PST 24
Peak memory 201428 kb
Host smart-4c1fdb06-5cda-4c9e-b2a4-ae3909a38e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655657188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.655657188
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1958389239
Short name T280
Test name
Test status
Simulation time 492705000382 ps
CPU time 134.78 seconds
Started Feb 18 01:20:07 PM PST 24
Finished Feb 18 01:22:23 PM PST 24
Peak memory 201388 kb
Host smart-cdcd5f3a-2522-4bb8-85fe-3cbf11527f1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958389239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1958389239
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2631582584
Short name T11
Test name
Test status
Simulation time 171599482408 ps
CPU time 411.8 seconds
Started Feb 18 01:15:57 PM PST 24
Finished Feb 18 01:22:50 PM PST 24
Peak memory 201440 kb
Host smart-62914d1a-26ad-4cfa-8da1-1042168da56b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631582584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2631582584
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1806620768
Short name T252
Test name
Test status
Simulation time 330376304365 ps
CPU time 184.55 seconds
Started Feb 18 01:16:10 PM PST 24
Finished Feb 18 01:19:16 PM PST 24
Peak memory 201452 kb
Host smart-9714cf6c-b626-47d8-aab9-98eb9e61ad37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806620768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1806620768
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.814060379
Short name T290
Test name
Test status
Simulation time 327261290775 ps
CPU time 363.84 seconds
Started Feb 18 01:20:40 PM PST 24
Finished Feb 18 01:26:46 PM PST 24
Peak memory 201464 kb
Host smart-0854d291-1961-4c95-981e-afbab35888b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814060379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.814060379
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3179716524
Short name T310
Test name
Test status
Simulation time 361883496185 ps
CPU time 240.64 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:19:15 PM PST 24
Peak memory 210132 kb
Host smart-05b81eaf-d486-4430-a2bf-a680fc0c43b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179716524 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3179716524
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3484836028
Short name T329
Test name
Test status
Simulation time 326884285751 ps
CPU time 366.99 seconds
Started Feb 18 01:16:16 PM PST 24
Finished Feb 18 01:22:26 PM PST 24
Peak memory 201492 kb
Host smart-85052e25-9a8f-4cb9-880e-7e18b9c278e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484836028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3484836028
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3900813062
Short name T165
Test name
Test status
Simulation time 484559756329 ps
CPU time 278.68 seconds
Started Feb 18 01:16:22 PM PST 24
Finished Feb 18 01:21:02 PM PST 24
Peak memory 201412 kb
Host smart-a0180fc2-1f71-49be-8b0c-8a9d5d1d49b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900813062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3900813062
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.293983791
Short name T239
Test name
Test status
Simulation time 485232537692 ps
CPU time 1154.31 seconds
Started Feb 18 01:20:32 PM PST 24
Finished Feb 18 01:39:48 PM PST 24
Peak memory 201436 kb
Host smart-b2993020-0019-41e5-bd29-d291545b5956
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293983791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.293983791
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.907987268
Short name T340
Test name
Test status
Simulation time 325472979197 ps
CPU time 176.38 seconds
Started Feb 18 01:21:30 PM PST 24
Finished Feb 18 01:24:27 PM PST 24
Peak memory 201420 kb
Host smart-8a670d11-40ff-494b-afab-2f2a081ee025
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907987268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.907987268
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3854806601
Short name T171
Test name
Test status
Simulation time 501751174889 ps
CPU time 269.68 seconds
Started Feb 18 01:15:25 PM PST 24
Finished Feb 18 01:19:56 PM PST 24
Peak memory 201416 kb
Host smart-a7445fc1-d157-499f-ae8f-99ba9870b265
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854806601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3854806601
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3861744480
Short name T292
Test name
Test status
Simulation time 499912227162 ps
CPU time 607.71 seconds
Started Feb 18 01:15:20 PM PST 24
Finished Feb 18 01:25:30 PM PST 24
Peak memory 201500 kb
Host smart-33cd12b3-a412-42c9-93a8-a4b6d5034bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861744480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3861744480
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.988313017
Short name T213
Test name
Test status
Simulation time 130415029398 ps
CPU time 725.15 seconds
Started Feb 18 01:14:57 PM PST 24
Finished Feb 18 01:27:03 PM PST 24
Peak memory 201628 kb
Host smart-54222282-252d-4f44-8879-b93c9fa119df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988313017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.988313017
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1769127011
Short name T288
Test name
Test status
Simulation time 166138885460 ps
CPU time 97.92 seconds
Started Feb 18 01:17:20 PM PST 24
Finished Feb 18 01:18:59 PM PST 24
Peak memory 201416 kb
Host smart-8b506408-ac26-4b18-9ccb-23eb5223a6cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769127011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1769127011
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3185805950
Short name T168
Test name
Test status
Simulation time 489722581546 ps
CPU time 1054.44 seconds
Started Feb 18 01:17:55 PM PST 24
Finished Feb 18 01:35:31 PM PST 24
Peak memory 201420 kb
Host smart-184bde03-a207-4ff5-a613-268cce46de20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185805950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3185805950
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2260789870
Short name T337
Test name
Test status
Simulation time 489798094879 ps
CPU time 1193.58 seconds
Started Feb 18 01:18:03 PM PST 24
Finished Feb 18 01:37:57 PM PST 24
Peak memory 201380 kb
Host smart-3c8119d4-6a39-4b6c-a212-790ef9256ea0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260789870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2260789870
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.385990073
Short name T159
Test name
Test status
Simulation time 475124251425 ps
CPU time 272.8 seconds
Started Feb 18 01:21:17 PM PST 24
Finished Feb 18 01:25:51 PM PST 24
Peak memory 201268 kb
Host smart-ef0d8f96-e1cd-421c-b039-a243d42b27eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385990073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.385990073
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2110897177
Short name T151
Test name
Test status
Simulation time 161003865428 ps
CPU time 55.41 seconds
Started Feb 18 01:22:31 PM PST 24
Finished Feb 18 01:23:27 PM PST 24
Peak memory 201524 kb
Host smart-6544adf1-a426-4044-a726-82e3de80c905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110897177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2110897177
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.214846628
Short name T324
Test name
Test status
Simulation time 495277338443 ps
CPU time 280.44 seconds
Started Feb 18 01:15:16 PM PST 24
Finished Feb 18 01:19:58 PM PST 24
Peak memory 201512 kb
Host smart-6c9d953e-b38f-4220-8504-be0c55943bb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214846628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.214846628
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.752417209
Short name T395
Test name
Test status
Simulation time 158239002815 ps
CPU time 85.09 seconds
Started Feb 18 01:14:55 PM PST 24
Finished Feb 18 01:16:21 PM PST 24
Peak memory 201480 kb
Host smart-efd3eced-5ebc-45c5-a9e5-9c594cc1925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752417209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.752417209
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1347020612
Short name T330
Test name
Test status
Simulation time 19082887005 ps
CPU time 45.11 seconds
Started Feb 18 01:14:47 PM PST 24
Finished Feb 18 01:15:34 PM PST 24
Peak memory 209808 kb
Host smart-98e21c00-6838-4d32-b7b0-e4532ad07eee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347020612 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1347020612
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2728863644
Short name T271
Test name
Test status
Simulation time 161400832230 ps
CPU time 214.13 seconds
Started Feb 18 01:15:42 PM PST 24
Finished Feb 18 01:19:18 PM PST 24
Peak memory 210056 kb
Host smart-1267c545-0771-42d5-b388-ed39e6ddefa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728863644 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2728863644
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2069867790
Short name T222
Test name
Test status
Simulation time 768457327214 ps
CPU time 1124.04 seconds
Started Feb 18 01:15:54 PM PST 24
Finished Feb 18 01:34:39 PM PST 24
Peak memory 211828 kb
Host smart-3ca02e42-083a-406d-bb8b-d9781476855a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069867790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2069867790
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1145907737
Short name T297
Test name
Test status
Simulation time 327104182348 ps
CPU time 757.42 seconds
Started Feb 18 01:15:53 PM PST 24
Finished Feb 18 01:28:31 PM PST 24
Peak memory 201412 kb
Host smart-07cf6e11-4d2a-427d-abe5-444f39f4657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145907737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1145907737
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3142185385
Short name T207
Test name
Test status
Simulation time 133584047339 ps
CPU time 465.65 seconds
Started Feb 18 01:16:27 PM PST 24
Finished Feb 18 01:24:13 PM PST 24
Peak memory 201708 kb
Host smart-5e8cd0a0-f187-4274-bf5c-0673014176c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142185385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3142185385
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2731336352
Short name T332
Test name
Test status
Simulation time 491804068516 ps
CPU time 306.92 seconds
Started Feb 18 01:19:53 PM PST 24
Finished Feb 18 01:25:01 PM PST 24
Peak memory 201512 kb
Host smart-213762a0-96f4-4d92-9f0b-030e730101ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731336352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2731336352
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3708669405
Short name T307
Test name
Test status
Simulation time 188943668742 ps
CPU time 183.35 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:23:23 PM PST 24
Peak memory 201468 kb
Host smart-db38877f-13f0-42e0-9609-6adc4f135443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708669405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3708669405
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.96817666
Short name T347
Test name
Test status
Simulation time 27696696674 ps
CPU time 54.21 seconds
Started Feb 18 01:20:16 PM PST 24
Finished Feb 18 01:21:12 PM PST 24
Peak memory 201624 kb
Host smart-20ab7dbd-7aa4-4ada-b9dc-f90b43f56826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96817666 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.96817666
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3673690637
Short name T339
Test name
Test status
Simulation time 330459905626 ps
CPU time 209.4 seconds
Started Feb 18 01:21:11 PM PST 24
Finished Feb 18 01:24:42 PM PST 24
Peak memory 201476 kb
Host smart-b88801bb-6ca6-4838-a539-67635b13f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673690637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3673690637
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.906414546
Short name T229
Test name
Test status
Simulation time 326568524691 ps
CPU time 709.36 seconds
Started Feb 18 01:21:23 PM PST 24
Finished Feb 18 01:33:14 PM PST 24
Peak memory 201248 kb
Host smart-a3ad38ca-bf8e-4ff8-b236-7394d87a7da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906414546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.906414546
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2748107423
Short name T870
Test name
Test status
Simulation time 4445978651 ps
CPU time 4.5 seconds
Started Feb 18 12:34:54 PM PST 24
Finished Feb 18 12:35:02 PM PST 24
Peak memory 201280 kb
Host smart-d177e690-5d9e-4d73-9bcb-d062d2d00c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748107423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2748107423
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.373663257
Short name T27
Test name
Test status
Simulation time 49673007507 ps
CPU time 93.79 seconds
Started Feb 18 01:14:52 PM PST 24
Finished Feb 18 01:16:28 PM PST 24
Peak memory 210052 kb
Host smart-e18a84fb-f064-49a7-b2d7-eaa0f109b686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373663257 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.373663257
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3397728184
Short name T220
Test name
Test status
Simulation time 274630677255 ps
CPU time 496.14 seconds
Started Feb 18 01:15:53 PM PST 24
Finished Feb 18 01:24:10 PM PST 24
Peak memory 212564 kb
Host smart-039b6f30-9d3a-4cff-8fcd-86617064c839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397728184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3397728184
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3555160860
Short name T217
Test name
Test status
Simulation time 221107522948 ps
CPU time 471.25 seconds
Started Feb 18 01:17:17 PM PST 24
Finished Feb 18 01:25:09 PM PST 24
Peak memory 218260 kb
Host smart-510e4272-334b-4f71-ae52-c994bf1b7a26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555160860 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3555160860
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4133939904
Short name T358
Test name
Test status
Simulation time 70592572626 ps
CPU time 363.59 seconds
Started Feb 18 01:17:32 PM PST 24
Finished Feb 18 01:23:38 PM PST 24
Peak memory 201656 kb
Host smart-0dadd5c8-7491-48e8-aa2a-2f0d15127ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133939904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4133939904
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2662340190
Short name T293
Test name
Test status
Simulation time 491798847570 ps
CPU time 606.54 seconds
Started Feb 18 01:18:59 PM PST 24
Finished Feb 18 01:29:06 PM PST 24
Peak memory 201532 kb
Host smart-2d3866ef-29e4-4376-9985-41c1c61736c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662340190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2662340190
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.544641231
Short name T309
Test name
Test status
Simulation time 105581509111 ps
CPU time 23.07 seconds
Started Feb 18 01:19:22 PM PST 24
Finished Feb 18 01:19:46 PM PST 24
Peak memory 201516 kb
Host smart-54981489-b97f-403e-b1ba-44987c3b68a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544641231 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.544641231
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2871469538
Short name T281
Test name
Test status
Simulation time 405116463745 ps
CPU time 487.72 seconds
Started Feb 18 01:19:38 PM PST 24
Finished Feb 18 01:27:46 PM PST 24
Peak memory 201788 kb
Host smart-9e40c143-5788-4bed-9764-1609e60f66cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871469538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2871469538
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.726366331
Short name T299
Test name
Test status
Simulation time 332443230183 ps
CPU time 795.05 seconds
Started Feb 18 01:20:57 PM PST 24
Finished Feb 18 01:34:13 PM PST 24
Peak memory 201464 kb
Host smart-5e67c3be-1b8d-45e3-a644-91e805f96f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726366331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.726366331
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.210786396
Short name T312
Test name
Test status
Simulation time 164375054994 ps
CPU time 96.94 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:16:51 PM PST 24
Peak memory 201468 kb
Host smart-8e641419-4d2a-42a1-bb7f-33c75328ac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210786396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.210786396
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3664835746
Short name T355
Test name
Test status
Simulation time 82086696486 ps
CPU time 282.1 seconds
Started Feb 18 01:15:33 PM PST 24
Finished Feb 18 01:20:17 PM PST 24
Peak memory 201724 kb
Host smart-5e283920-17bb-4faf-96f2-7566c7ac2e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664835746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3664835746
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1158985116
Short name T906
Test name
Test status
Simulation time 1113734422 ps
CPU time 5.38 seconds
Started Feb 18 12:34:28 PM PST 24
Finished Feb 18 12:34:42 PM PST 24
Peak memory 201036 kb
Host smart-ec932483-4f2c-404e-b055-6f0de0732285
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158985116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1158985116
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2230197661
Short name T868
Test name
Test status
Simulation time 27347201112 ps
CPU time 10.89 seconds
Started Feb 18 12:34:32 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 201156 kb
Host smart-ec2f2660-0ffe-42a3-8ee2-8ba9f4fd5086
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230197661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2230197661
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1683059511
Short name T99
Test name
Test status
Simulation time 1287245927 ps
CPU time 1.26 seconds
Started Feb 18 12:34:31 PM PST 24
Finished Feb 18 12:34:40 PM PST 24
Peak memory 200848 kb
Host smart-821ac61f-e1a8-4c1d-9104-f5ea0551f7dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683059511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1683059511
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3451520886
Short name T75
Test name
Test status
Simulation time 423108950 ps
CPU time 2.33 seconds
Started Feb 18 12:38:31 PM PST 24
Finished Feb 18 12:38:35 PM PST 24
Peak memory 209404 kb
Host smart-89fa1d90-8829-42b5-8f69-b883755a3662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451520886 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3451520886
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2461272432
Short name T843
Test name
Test status
Simulation time 334792547 ps
CPU time 0.85 seconds
Started Feb 18 12:34:32 PM PST 24
Finished Feb 18 12:34:40 PM PST 24
Peak memory 200852 kb
Host smart-41a75c47-a8ad-44ea-8157-c78fc2c8c9d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461272432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2461272432
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2076765838
Short name T908
Test name
Test status
Simulation time 292651941 ps
CPU time 0.98 seconds
Started Feb 18 12:34:29 PM PST 24
Finished Feb 18 12:34:38 PM PST 24
Peak memory 200888 kb
Host smart-2aec3d68-ef41-4e92-a22e-84f87cae6e2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076765838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2076765838
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4022975120
Short name T834
Test name
Test status
Simulation time 3498374085 ps
CPU time 8.58 seconds
Started Feb 18 12:34:29 PM PST 24
Finished Feb 18 12:34:45 PM PST 24
Peak memory 201196 kb
Host smart-9e0c4ed7-faa2-4a6b-8f72-d80b3ef2ac2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022975120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.4022975120
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2097740692
Short name T814
Test name
Test status
Simulation time 1388397647 ps
CPU time 2.14 seconds
Started Feb 18 12:34:31 PM PST 24
Finished Feb 18 12:34:41 PM PST 24
Peak memory 201164 kb
Host smart-8130ed2d-a38e-44b5-b89b-23646bd75ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097740692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2097740692
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1735440553
Short name T838
Test name
Test status
Simulation time 4324783423 ps
CPU time 11.53 seconds
Started Feb 18 12:34:31 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 201148 kb
Host smart-60dd7879-1687-4419-b601-a598c6706f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735440553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1735440553
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2603707169
Short name T861
Test name
Test status
Simulation time 623614287 ps
CPU time 1.86 seconds
Started Feb 18 12:34:32 PM PST 24
Finished Feb 18 12:34:41 PM PST 24
Peak memory 201012 kb
Host smart-f97789f6-dbc3-4764-9d51-eba84a185310
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603707169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2603707169
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.211346517
Short name T864
Test name
Test status
Simulation time 26828797408 ps
CPU time 33.96 seconds
Started Feb 18 12:34:34 PM PST 24
Finished Feb 18 12:35:16 PM PST 24
Peak memory 201272 kb
Host smart-94ee9955-2040-47eb-bbac-e54f1c8215bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211346517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.211346517
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2398210245
Short name T802
Test name
Test status
Simulation time 1019676436 ps
CPU time 3 seconds
Started Feb 18 12:34:32 PM PST 24
Finished Feb 18 12:34:42 PM PST 24
Peak memory 200844 kb
Host smart-92e1bccf-596b-41fd-b20b-ff763db0d779
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398210245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2398210245
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1126406290
Short name T903
Test name
Test status
Simulation time 473473214 ps
CPU time 1.73 seconds
Started Feb 18 12:34:31 PM PST 24
Finished Feb 18 12:34:40 PM PST 24
Peak memory 209476 kb
Host smart-a5de90e8-281b-44ab-91f2-ae00e4fa63dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126406290 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1126406290
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4004976125
Short name T110
Test name
Test status
Simulation time 345649505 ps
CPU time 1.61 seconds
Started Feb 18 12:34:28 PM PST 24
Finished Feb 18 12:34:38 PM PST 24
Peak memory 200872 kb
Host smart-5a982f02-f539-45f7-b511-99efedde6325
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004976125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4004976125
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.944565247
Short name T832
Test name
Test status
Simulation time 329805456 ps
CPU time 0.91 seconds
Started Feb 18 12:34:29 PM PST 24
Finished Feb 18 12:34:38 PM PST 24
Peak memory 200876 kb
Host smart-2a7b7718-8cc6-4510-b297-b67b4bc52170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944565247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.944565247
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.157733102
Short name T850
Test name
Test status
Simulation time 2174110731 ps
CPU time 5.61 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:54 PM PST 24
Peak memory 201040 kb
Host smart-47e11011-1e16-4a33-a64b-5a825491ef8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157733102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.157733102
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.653835946
Short name T875
Test name
Test status
Simulation time 4534271891 ps
CPU time 12.78 seconds
Started Feb 18 12:34:28 PM PST 24
Finished Feb 18 12:34:49 PM PST 24
Peak memory 201208 kb
Host smart-534ea950-4de7-4628-9d76-314713656dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653835946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.653835946
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2671251859
Short name T65
Test name
Test status
Simulation time 752701826 ps
CPU time 1.33 seconds
Started Feb 18 12:34:45 PM PST 24
Finished Feb 18 12:34:53 PM PST 24
Peak memory 201148 kb
Host smart-0b782565-39dc-40b9-accc-e7c17031e80b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671251859 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2671251859
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.488403062
Short name T909
Test name
Test status
Simulation time 442185941 ps
CPU time 0.97 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:51 PM PST 24
Peak memory 199752 kb
Host smart-00b51f3f-8e5f-4c48-8ea8-5159bd12d7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488403062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.488403062
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2036874203
Short name T863
Test name
Test status
Simulation time 304264634 ps
CPU time 0.76 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:48 PM PST 24
Peak memory 200708 kb
Host smart-d0efa719-6a7e-47d8-8749-0803d690873d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036874203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2036874203
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3875611260
Short name T847
Test name
Test status
Simulation time 1893657395 ps
CPU time 7.67 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:34:54 PM PST 24
Peak memory 200932 kb
Host smart-84d699b4-9d03-42a8-a781-75445ae82368
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875611260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3875611260
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4006043466
Short name T63
Test name
Test status
Simulation time 483408400 ps
CPU time 2.94 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:52 PM PST 24
Peak memory 217600 kb
Host smart-90e3f629-b259-446e-bfa4-bc0ec4b06dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006043466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4006043466
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.278650499
Short name T855
Test name
Test status
Simulation time 4207082427 ps
CPU time 6.71 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:57 PM PST 24
Peak memory 201316 kb
Host smart-e659e2dc-c51e-4c08-9dc2-05ba186dbca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278650499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.278650499
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1933674027
Short name T37
Test name
Test status
Simulation time 637272847 ps
CPU time 3.85 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:51 PM PST 24
Peak memory 212228 kb
Host smart-628c2951-3b6f-4425-9858-03b3ae427250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933674027 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1933674027
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1028967916
Short name T810
Test name
Test status
Simulation time 389960854 ps
CPU time 1.19 seconds
Started Feb 18 12:34:46 PM PST 24
Finished Feb 18 12:34:54 PM PST 24
Peak memory 200956 kb
Host smart-096c3f26-ba08-45bf-b0ff-367effd42c6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028967916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1028967916
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3436441581
Short name T819
Test name
Test status
Simulation time 463835083 ps
CPU time 1.11 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:34:47 PM PST 24
Peak memory 200768 kb
Host smart-505c9817-d28f-455a-96b6-27a33b8643b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436441581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3436441581
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2971247828
Short name T837
Test name
Test status
Simulation time 366970336 ps
CPU time 2.13 seconds
Started Feb 18 12:34:45 PM PST 24
Finished Feb 18 12:34:54 PM PST 24
Peak memory 201192 kb
Host smart-cd4e9c8a-f4d7-43bc-b59f-9006d5ca9e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971247828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2971247828
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.618952639
Short name T895
Test name
Test status
Simulation time 723727735 ps
CPU time 2.69 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 217236 kb
Host smart-5781acb4-6a4d-4e29-b9d7-3a853bb67d2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618952639 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.618952639
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1240617359
Short name T910
Test name
Test status
Simulation time 429120694 ps
CPU time 1.63 seconds
Started Feb 18 12:34:38 PM PST 24
Finished Feb 18 12:34:46 PM PST 24
Peak memory 200972 kb
Host smart-d031f58e-ad0b-4c2a-9448-2177782276fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240617359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1240617359
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2098742232
Short name T902
Test name
Test status
Simulation time 290846850 ps
CPU time 1.02 seconds
Started Feb 18 12:34:44 PM PST 24
Finished Feb 18 12:34:52 PM PST 24
Peak memory 200888 kb
Host smart-bb395269-010f-4db9-bcd9-cdb2e3593d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098742232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2098742232
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1288737359
Short name T869
Test name
Test status
Simulation time 5327515176 ps
CPU time 21.35 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:35:11 PM PST 24
Peak memory 201368 kb
Host smart-033af036-8982-4bbc-8b27-9dfcb6bb4b31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288737359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1288737359
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.6398156
Short name T872
Test name
Test status
Simulation time 512552289 ps
CPU time 3.21 seconds
Started Feb 18 12:34:38 PM PST 24
Finished Feb 18 12:34:47 PM PST 24
Peak memory 201152 kb
Host smart-41f83770-3465-49fe-886e-7b055734909f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6398156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.6398156
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1460017837
Short name T897
Test name
Test status
Simulation time 7991334074 ps
CPU time 7.7 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:34:53 PM PST 24
Peak memory 201232 kb
Host smart-9545e0e5-e65c-4133-9c85-3b6c34de66f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460017837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1460017837
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.476996230
Short name T884
Test name
Test status
Simulation time 525153377 ps
CPU time 3.15 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 209276 kb
Host smart-89bf80be-f4f7-463b-82f8-8fd4fb90a980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476996230 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.476996230
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1986668171
Short name T104
Test name
Test status
Simulation time 555491335 ps
CPU time 2.23 seconds
Started Feb 18 12:34:38 PM PST 24
Finished Feb 18 12:34:46 PM PST 24
Peak memory 200868 kb
Host smart-cf628275-fc72-47a5-aca1-ad68d560a5bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986668171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1986668171
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3928345715
Short name T827
Test name
Test status
Simulation time 515729469 ps
CPU time 1.95 seconds
Started Feb 18 12:34:45 PM PST 24
Finished Feb 18 12:34:54 PM PST 24
Peak memory 200900 kb
Host smart-07d975bb-897e-4e26-ae56-d369fbf5cbce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928345715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3928345715
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.681784277
Short name T893
Test name
Test status
Simulation time 2319177180 ps
CPU time 5.19 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:52 PM PST 24
Peak memory 200908 kb
Host smart-528020ec-204f-4d30-985d-e93c5253d33f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681784277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.681784277
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3420060919
Short name T881
Test name
Test status
Simulation time 521339882 ps
CPU time 2.46 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 201212 kb
Host smart-537a0ee4-2e6f-4232-ace6-285e94aaaf2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420060919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3420060919
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1539876491
Short name T85
Test name
Test status
Simulation time 7750374987 ps
CPU time 19.66 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:35:05 PM PST 24
Peak memory 201072 kb
Host smart-104964b8-1919-4941-a41e-f1a8b9140fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539876491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1539876491
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3544948136
Short name T817
Test name
Test status
Simulation time 749660865 ps
CPU time 2.09 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 209340 kb
Host smart-c016a091-d4da-43e1-904c-901aff3ad020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544948136 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3544948136
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3938428164
Short name T101
Test name
Test status
Simulation time 369495198 ps
CPU time 1.73 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 200904 kb
Host smart-8d1b14ae-0262-49e3-8e33-c5d102f3be9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938428164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3938428164
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.515815303
Short name T842
Test name
Test status
Simulation time 525860004 ps
CPU time 1.73 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:34:57 PM PST 24
Peak memory 200660 kb
Host smart-465806c9-1db2-4eb5-9c5b-c96e8d707e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515815303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.515815303
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1463417715
Short name T828
Test name
Test status
Simulation time 4539306887 ps
CPU time 11.57 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:35:07 PM PST 24
Peak memory 200688 kb
Host smart-33a2ef9e-fc50-4b64-b9f9-4bccb994034a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463417715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1463417715
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1716471641
Short name T900
Test name
Test status
Simulation time 606683932 ps
CPU time 3.64 seconds
Started Feb 18 12:34:45 PM PST 24
Finished Feb 18 12:34:56 PM PST 24
Peak memory 200496 kb
Host smart-83585044-2108-4409-ba92-a9e6050fbfc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716471641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1716471641
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2035048890
Short name T891
Test name
Test status
Simulation time 4599101178 ps
CPU time 3.34 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:52 PM PST 24
Peak memory 201260 kb
Host smart-ffeca2f3-ceb5-40e4-870d-5377c68a57d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035048890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2035048890
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.865771247
Short name T74
Test name
Test status
Simulation time 778005074 ps
CPU time 2.84 seconds
Started Feb 18 12:34:46 PM PST 24
Finished Feb 18 12:34:57 PM PST 24
Peak memory 211960 kb
Host smart-491394b7-668a-4d3f-90c1-a8536c94c06d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865771247 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.865771247
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2414689701
Short name T904
Test name
Test status
Simulation time 440534203 ps
CPU time 1.66 seconds
Started Feb 18 12:34:50 PM PST 24
Finished Feb 18 12:34:58 PM PST 24
Peak memory 200892 kb
Host smart-15ee8a64-a112-4c3f-874d-a65168486887
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414689701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2414689701
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3106053049
Short name T913
Test name
Test status
Simulation time 504243415 ps
CPU time 1.98 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:34:58 PM PST 24
Peak memory 200208 kb
Host smart-46732286-fae3-426f-94a0-d4a94e3ee8e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106053049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3106053049
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1893422439
Short name T822
Test name
Test status
Simulation time 3917845703 ps
CPU time 9.43 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:35:05 PM PST 24
Peak memory 200868 kb
Host smart-aa5e3976-a077-411f-b504-d868bc44b60f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893422439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1893422439
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1045122989
Short name T889
Test name
Test status
Simulation time 892147829 ps
CPU time 3.23 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:51 PM PST 24
Peak memory 210320 kb
Host smart-d6b810f3-9a8b-4ec2-ac65-fad882628c83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045122989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1045122989
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2145333648
Short name T831
Test name
Test status
Simulation time 4337558932 ps
CPU time 4.08 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:51 PM PST 24
Peak memory 201172 kb
Host smart-887d5613-ac2f-4ce4-bdb6-e283484b5dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145333648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2145333648
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1540563177
Short name T841
Test name
Test status
Simulation time 604673698 ps
CPU time 2.65 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:34:58 PM PST 24
Peak memory 209392 kb
Host smart-37577203-bbc5-469f-bd3e-ae3542c8148d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540563177 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1540563177
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4137527070
Short name T857
Test name
Test status
Simulation time 447509196 ps
CPU time 1.85 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:34:58 PM PST 24
Peak memory 200908 kb
Host smart-53bbdaf6-e998-4531-afab-3a9f043a1af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137527070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4137527070
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4289799931
Short name T806
Test name
Test status
Simulation time 451378319 ps
CPU time 0.9 seconds
Started Feb 18 12:34:45 PM PST 24
Finished Feb 18 12:34:54 PM PST 24
Peak memory 201016 kb
Host smart-a704794c-8439-4664-beca-700477784a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289799931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.4289799931
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2792686472
Short name T804
Test name
Test status
Simulation time 2658596558 ps
CPU time 11.55 seconds
Started Feb 18 12:34:53 PM PST 24
Finished Feb 18 12:35:09 PM PST 24
Peak memory 200900 kb
Host smart-63bc374f-a053-4222-a8a7-fdb2081f3248
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792686472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2792686472
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1565455330
Short name T86
Test name
Test status
Simulation time 748255456 ps
CPU time 2.64 seconds
Started Feb 18 12:34:52 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 217256 kb
Host smart-f7cb3c29-ff65-447a-93c0-91b92695a8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565455330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1565455330
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3349652907
Short name T352
Test name
Test status
Simulation time 8108656563 ps
CPU time 6.55 seconds
Started Feb 18 12:34:53 PM PST 24
Finished Feb 18 12:35:04 PM PST 24
Peak memory 201280 kb
Host smart-f80ecdb0-56a7-453a-a627-48e693b710d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349652907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3349652907
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.439228986
Short name T871
Test name
Test status
Simulation time 563698677 ps
CPU time 2.48 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:06 PM PST 24
Peak memory 209348 kb
Host smart-166b6971-8d83-4144-82bc-6208bbbb0a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439228986 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.439228986
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3941834557
Short name T103
Test name
Test status
Simulation time 314160683 ps
CPU time 1.5 seconds
Started Feb 18 12:34:46 PM PST 24
Finished Feb 18 12:34:56 PM PST 24
Peak memory 200924 kb
Host smart-2af4f789-8f07-4517-8fab-3e956ece291e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941834557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3941834557
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2358978245
Short name T798
Test name
Test status
Simulation time 301573950 ps
CPU time 1.28 seconds
Started Feb 18 12:34:44 PM PST 24
Finished Feb 18 12:34:52 PM PST 24
Peak memory 200880 kb
Host smart-6f23234c-9c8a-47bf-8570-26e5d7449cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358978245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2358978245
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4204929791
Short name T33
Test name
Test status
Simulation time 4815306370 ps
CPU time 11.21 seconds
Started Feb 18 12:34:54 PM PST 24
Finished Feb 18 12:35:09 PM PST 24
Peak memory 201200 kb
Host smart-10cb6b8d-2d04-493c-8b42-e31a0fb70cb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204929791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.4204929791
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2671253525
Short name T848
Test name
Test status
Simulation time 1329902999 ps
CPU time 2.07 seconds
Started Feb 18 12:34:54 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 201212 kb
Host smart-11663a45-b722-443b-8a03-0c2cf1692f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671253525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2671253525
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2230075474
Short name T885
Test name
Test status
Simulation time 8899384346 ps
CPU time 10.3 seconds
Started Feb 18 12:34:47 PM PST 24
Finished Feb 18 12:35:05 PM PST 24
Peak memory 201272 kb
Host smart-9c441718-c21c-4059-b0fc-03613e74040a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230075474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2230075474
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2394128533
Short name T836
Test name
Test status
Simulation time 697791054 ps
CPU time 3.8 seconds
Started Feb 18 12:34:50 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 209412 kb
Host smart-804d0119-39e5-4d5c-b373-106cd5055d8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394128533 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2394128533
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4071460310
Short name T816
Test name
Test status
Simulation time 313754593 ps
CPU time 1.36 seconds
Started Feb 18 12:34:47 PM PST 24
Finished Feb 18 12:34:56 PM PST 24
Peak memory 200912 kb
Host smart-628b2144-cdeb-4a75-a8cb-4bce9d4ec0bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071460310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4071460310
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4068375884
Short name T880
Test name
Test status
Simulation time 316175411 ps
CPU time 1.02 seconds
Started Feb 18 12:34:45 PM PST 24
Finished Feb 18 12:34:53 PM PST 24
Peak memory 200768 kb
Host smart-65b2fdf7-bae6-4c3b-98ec-001bd3823e5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068375884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4068375884
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2733140807
Short name T32
Test name
Test status
Simulation time 3536793110 ps
CPU time 11.87 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:35:07 PM PST 24
Peak memory 200960 kb
Host smart-c5e6f39c-adda-4eff-9f11-7c49b9cfe673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733140807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2733140807
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2400967652
Short name T800
Test name
Test status
Simulation time 411803799 ps
CPU time 2.81 seconds
Started Feb 18 12:34:48 PM PST 24
Finished Feb 18 12:34:58 PM PST 24
Peak memory 217476 kb
Host smart-d0b91215-96df-4583-b3c5-ccdd0f30594c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400967652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2400967652
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1547233875
Short name T845
Test name
Test status
Simulation time 623486554 ps
CPU time 4.62 seconds
Started Feb 18 12:34:54 PM PST 24
Finished Feb 18 12:35:03 PM PST 24
Peak memory 209392 kb
Host smart-0cc5a64f-5a8f-46cc-bcc4-befa30577993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547233875 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1547233875
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.736479653
Short name T846
Test name
Test status
Simulation time 527290100 ps
CPU time 1.83 seconds
Started Feb 18 12:34:46 PM PST 24
Finished Feb 18 12:34:56 PM PST 24
Peak memory 200804 kb
Host smart-29aa729e-2c3b-4cca-8976-645453111531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736479653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.736479653
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2250578373
Short name T874
Test name
Test status
Simulation time 4482430199 ps
CPU time 4.71 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:35:01 PM PST 24
Peak memory 201264 kb
Host smart-63171dc8-0ee7-4ab1-a8d2-ece5676b1f8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250578373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2250578373
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1456996272
Short name T835
Test name
Test status
Simulation time 474044870 ps
CPU time 3.34 seconds
Started Feb 18 12:34:46 PM PST 24
Finished Feb 18 12:34:57 PM PST 24
Peak memory 217544 kb
Host smart-64281252-f9e3-45fa-9699-822c0bdac862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456996272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1456996272
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.915649079
Short name T840
Test name
Test status
Simulation time 7791306137 ps
CPU time 19.58 seconds
Started Feb 18 12:34:50 PM PST 24
Finished Feb 18 12:35:16 PM PST 24
Peak memory 201332 kb
Host smart-dd1d5c04-e541-4ea3-acbb-532c5006ff17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915649079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.915649079
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3296088329
Short name T106
Test name
Test status
Simulation time 1102424526 ps
CPU time 3.65 seconds
Started Feb 18 12:34:36 PM PST 24
Finished Feb 18 12:34:47 PM PST 24
Peak memory 201068 kb
Host smart-2135546e-83a1-4db2-a9e2-45d22399e5f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296088329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3296088329
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2104405286
Short name T878
Test name
Test status
Simulation time 6034500782 ps
CPU time 3.96 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:34:49 PM PST 24
Peak memory 201312 kb
Host smart-72eacd6f-9399-4e0c-be9a-362945418b00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104405286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2104405286
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2599287873
Short name T116
Test name
Test status
Simulation time 964508920 ps
CPU time 2.79 seconds
Started Feb 18 12:34:36 PM PST 24
Finished Feb 18 12:34:46 PM PST 24
Peak memory 200900 kb
Host smart-ede0e184-3604-459e-8041-db73a2ecd325
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599287873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2599287873
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1091432111
Short name T860
Test name
Test status
Simulation time 525155571 ps
CPU time 2.8 seconds
Started Feb 18 12:34:29 PM PST 24
Finished Feb 18 12:34:40 PM PST 24
Peak memory 209388 kb
Host smart-9e1b3ab2-9fe0-44a6-99f8-828358b5bdfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091432111 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1091432111
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.450908923
Short name T98
Test name
Test status
Simulation time 430954649 ps
CPU time 0.95 seconds
Started Feb 18 12:34:31 PM PST 24
Finished Feb 18 12:34:40 PM PST 24
Peak memory 200904 kb
Host smart-81781580-e727-4ddb-8dfa-19d13d481631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450908923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.450908923
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3012487855
Short name T825
Test name
Test status
Simulation time 307737235 ps
CPU time 1 seconds
Started Feb 18 12:34:37 PM PST 24
Finished Feb 18 12:34:44 PM PST 24
Peak memory 200808 kb
Host smart-a212cd67-7734-42af-af75-1f7d8b47f39a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012487855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3012487855
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4045940766
Short name T115
Test name
Test status
Simulation time 4009357073 ps
CPU time 13.41 seconds
Started Feb 18 12:34:31 PM PST 24
Finished Feb 18 12:34:52 PM PST 24
Peak memory 201260 kb
Host smart-78e11579-0942-4d2b-a7be-be701405fff1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045940766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.4045940766
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3723130190
Short name T912
Test name
Test status
Simulation time 386626861 ps
CPU time 2.11 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 201200 kb
Host smart-a055e067-c601-4a52-b7d7-b3d931f3959b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723130190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3723130190
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.482142414
Short name T883
Test name
Test status
Simulation time 8747731165 ps
CPU time 5.49 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:54 PM PST 24
Peak memory 201204 kb
Host smart-3eda3840-d58f-4dc0-a40e-8797f04d07b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482142414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.482142414
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2744020337
Short name T813
Test name
Test status
Simulation time 445937129 ps
CPU time 1.68 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:34:57 PM PST 24
Peak memory 200636 kb
Host smart-69513464-5e3e-4b01-9439-9087b8b1774c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744020337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2744020337
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1661214688
Short name T815
Test name
Test status
Simulation time 395848788 ps
CPU time 0.88 seconds
Started Feb 18 12:34:45 PM PST 24
Finished Feb 18 12:34:53 PM PST 24
Peak memory 200720 kb
Host smart-fa6f79f8-2620-404e-ac01-844a13d13b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661214688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1661214688
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1258977631
Short name T865
Test name
Test status
Simulation time 345923442 ps
CPU time 0.82 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:34:56 PM PST 24
Peak memory 200728 kb
Host smart-ca84c6db-2f94-4a5c-84c4-3307332aca39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258977631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1258977631
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2272016276
Short name T854
Test name
Test status
Simulation time 353644837 ps
CPU time 1.58 seconds
Started Feb 18 12:34:49 PM PST 24
Finished Feb 18 12:34:57 PM PST 24
Peak memory 200876 kb
Host smart-83ea91a6-ddba-4ddc-bd9f-295cedf530df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272016276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2272016276
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.362469138
Short name T844
Test name
Test status
Simulation time 334087204 ps
CPU time 1.36 seconds
Started Feb 18 12:34:47 PM PST 24
Finished Feb 18 12:34:56 PM PST 24
Peak memory 200764 kb
Host smart-95a7517b-e936-4a02-9c95-ca41649b050d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362469138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.362469138
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1443670738
Short name T809
Test name
Test status
Simulation time 380449255 ps
CPU time 0.85 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:04 PM PST 24
Peak memory 200892 kb
Host smart-eb72c146-f6e5-432c-83a9-7ddf777bebf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443670738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1443670738
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4041272585
Short name T859
Test name
Test status
Simulation time 294062919 ps
CPU time 1 seconds
Started Feb 18 12:34:52 PM PST 24
Finished Feb 18 12:34:58 PM PST 24
Peak memory 200720 kb
Host smart-d8696fc5-0e88-43f1-b397-646f4dee52ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041272585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4041272585
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.619032642
Short name T829
Test name
Test status
Simulation time 287738547 ps
CPU time 1.33 seconds
Started Feb 18 12:34:47 PM PST 24
Finished Feb 18 12:34:56 PM PST 24
Peak memory 200712 kb
Host smart-dcc4b3a4-4f99-4224-853f-a7ab1aadfb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619032642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.619032642
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.186896860
Short name T833
Test name
Test status
Simulation time 310499168 ps
CPU time 1.36 seconds
Started Feb 18 12:34:53 PM PST 24
Finished Feb 18 12:34:59 PM PST 24
Peak memory 200724 kb
Host smart-617fdcff-de97-4779-a748-9960c83af949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186896860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.186896860
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2969920174
Short name T801
Test name
Test status
Simulation time 304840616 ps
CPU time 1.05 seconds
Started Feb 18 12:35:06 PM PST 24
Finished Feb 18 12:35:09 PM PST 24
Peak memory 200844 kb
Host smart-6c58eae2-3eaf-401d-a14d-305ad4813918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969920174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2969920174
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2414416624
Short name T117
Test name
Test status
Simulation time 1072355238 ps
CPU time 4.38 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:52 PM PST 24
Peak memory 201148 kb
Host smart-af93af4a-bc9f-46ac-8454-1ad37edebb74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414416624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2414416624
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3572369446
Short name T30
Test name
Test status
Simulation time 26249603077 ps
CPU time 58.21 seconds
Started Feb 18 12:34:32 PM PST 24
Finished Feb 18 12:35:38 PM PST 24
Peak memory 201260 kb
Host smart-df740bf4-4e9e-45bd-9420-05b19c35b595
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572369446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3572369446
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2712747305
Short name T821
Test name
Test status
Simulation time 1283172337 ps
CPU time 3.05 seconds
Started Feb 18 12:34:35 PM PST 24
Finished Feb 18 12:34:46 PM PST 24
Peak memory 200740 kb
Host smart-995ffeab-5694-4a5b-b9dc-e11456f82535
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712747305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2712747305
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.41582416
Short name T911
Test name
Test status
Simulation time 640224183 ps
CPU time 3.75 seconds
Started Feb 18 12:34:39 PM PST 24
Finished Feb 18 12:34:49 PM PST 24
Peak memory 209416 kb
Host smart-1f2f179b-c963-49c0-a177-571981bccae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41582416 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.41582416
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1476445189
Short name T108
Test name
Test status
Simulation time 526875327 ps
CPU time 1.94 seconds
Started Feb 18 12:34:29 PM PST 24
Finished Feb 18 12:34:39 PM PST 24
Peak memory 200924 kb
Host smart-a1b9c4d9-9526-462a-9f38-79a9789c65f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476445189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1476445189
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3053201504
Short name T797
Test name
Test status
Simulation time 498403772 ps
CPU time 1.67 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:49 PM PST 24
Peak memory 200748 kb
Host smart-b50c381e-197d-4f9c-ac5c-a2eaaad3484e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053201504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3053201504
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3814737687
Short name T905
Test name
Test status
Simulation time 2466572806 ps
CPU time 3.46 seconds
Started Feb 18 12:34:30 PM PST 24
Finished Feb 18 12:34:41 PM PST 24
Peak memory 201032 kb
Host smart-d6e1684a-2513-4f31-bb1a-fc7e9495ff26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814737687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3814737687
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1878840802
Short name T64
Test name
Test status
Simulation time 490200149 ps
CPU time 2.15 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:34:48 PM PST 24
Peak memory 201168 kb
Host smart-ccecd5eb-5a6b-4635-90ad-b33deb95fc1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878840802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1878840802
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1526461532
Short name T73
Test name
Test status
Simulation time 3943715436 ps
CPU time 10.94 seconds
Started Feb 18 12:34:34 PM PST 24
Finished Feb 18 12:34:52 PM PST 24
Peak memory 201328 kb
Host smart-71af0b76-ab54-451f-8d54-94fb41e359f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526461532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1526461532
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2833080379
Short name T808
Test name
Test status
Simulation time 340706877 ps
CPU time 1.45 seconds
Started Feb 18 12:34:55 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 200720 kb
Host smart-95d74604-35e0-4897-9c7b-998a692c2fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833080379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2833080379
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3222304835
Short name T796
Test name
Test status
Simulation time 334915927 ps
CPU time 1.17 seconds
Started Feb 18 12:34:54 PM PST 24
Finished Feb 18 12:34:59 PM PST 24
Peak memory 200880 kb
Host smart-2270d4d7-ac88-41b5-80a5-75d29319d03a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222304835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3222304835
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1011614194
Short name T858
Test name
Test status
Simulation time 397916972 ps
CPU time 0.9 seconds
Started Feb 18 12:34:56 PM PST 24
Finished Feb 18 12:35:01 PM PST 24
Peak memory 200768 kb
Host smart-f123c49f-fdb8-4246-ae7d-744c9091c48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011614194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1011614194
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1775940418
Short name T849
Test name
Test status
Simulation time 522558319 ps
CPU time 1.77 seconds
Started Feb 18 12:35:02 PM PST 24
Finished Feb 18 12:35:07 PM PST 24
Peak memory 200748 kb
Host smart-bca2daf1-82f0-4fb5-b516-15a16e02a9aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775940418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1775940418
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2137362889
Short name T820
Test name
Test status
Simulation time 309033453 ps
CPU time 0.96 seconds
Started Feb 18 12:34:55 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 200748 kb
Host smart-13705c07-eddd-4db0-abad-6b16ed19d4ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137362889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2137362889
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1002020311
Short name T803
Test name
Test status
Simulation time 524018907 ps
CPU time 0.94 seconds
Started Feb 18 12:34:56 PM PST 24
Finished Feb 18 12:35:01 PM PST 24
Peak memory 200772 kb
Host smart-6bfdc8e7-72db-4734-a49b-0cf7fd4c1e6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002020311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1002020311
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3733126826
Short name T795
Test name
Test status
Simulation time 323807051 ps
CPU time 1.39 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:04 PM PST 24
Peak memory 200720 kb
Host smart-b865c7fc-bfbc-4880-93d7-13917fa2d8a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733126826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3733126826
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2548836645
Short name T876
Test name
Test status
Simulation time 375292397 ps
CPU time 1.1 seconds
Started Feb 18 12:34:56 PM PST 24
Finished Feb 18 12:35:01 PM PST 24
Peak memory 200704 kb
Host smart-c2b60924-3f2c-4acf-89f0-b77e2405670a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548836645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2548836645
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1040511425
Short name T799
Test name
Test status
Simulation time 458355279 ps
CPU time 0.87 seconds
Started Feb 18 12:34:56 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 200884 kb
Host smart-e1ffde28-5646-4b1e-9b0f-c4e0bac9f675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040511425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1040511425
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2660691191
Short name T866
Test name
Test status
Simulation time 366354180 ps
CPU time 1.04 seconds
Started Feb 18 12:35:02 PM PST 24
Finished Feb 18 12:35:07 PM PST 24
Peak memory 200896 kb
Host smart-fbef496d-53ed-4ea6-ac0b-80ea6b880488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660691191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2660691191
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3330237938
Short name T105
Test name
Test status
Simulation time 913879875 ps
CPU time 2.76 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:52 PM PST 24
Peak memory 201088 kb
Host smart-abc3a524-830a-4503-bb21-f35d9cf04b4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330237938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3330237938
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1305711142
Short name T107
Test name
Test status
Simulation time 24028457077 ps
CPU time 22.92 seconds
Started Feb 18 12:34:34 PM PST 24
Finished Feb 18 12:35:04 PM PST 24
Peak memory 201288 kb
Host smart-6dfd0d83-75a9-43df-bbaa-f25b0e879e8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305711142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1305711142
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3680392428
Short name T888
Test name
Test status
Simulation time 895839390 ps
CPU time 2.63 seconds
Started Feb 18 12:34:34 PM PST 24
Finished Feb 18 12:34:44 PM PST 24
Peak memory 200904 kb
Host smart-962e34d1-d3cf-4138-b641-834a2e3a01a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680392428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3680392428
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4245327055
Short name T896
Test name
Test status
Simulation time 911429179 ps
CPU time 1.55 seconds
Started Feb 18 12:34:30 PM PST 24
Finished Feb 18 12:34:39 PM PST 24
Peak memory 209408 kb
Host smart-64675d52-bd5a-4797-8916-ddd5424ccb33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245327055 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.4245327055
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2165119665
Short name T114
Test name
Test status
Simulation time 506049137 ps
CPU time 1.82 seconds
Started Feb 18 12:34:30 PM PST 24
Finished Feb 18 12:34:40 PM PST 24
Peak memory 201004 kb
Host smart-7ca8e243-2fbe-4e18-ab16-0266629d1dfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165119665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2165119665
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2691307064
Short name T823
Test name
Test status
Simulation time 429534415 ps
CPU time 1.52 seconds
Started Feb 18 12:34:36 PM PST 24
Finished Feb 18 12:34:44 PM PST 24
Peak memory 200892 kb
Host smart-1958d7d3-9f7a-48f5-adfb-21547fae4442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691307064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2691307064
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1453388737
Short name T112
Test name
Test status
Simulation time 4418682294 ps
CPU time 4.74 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:53 PM PST 24
Peak memory 201228 kb
Host smart-61144b20-3f4b-485d-9de4-2c627902e03e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453388737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1453388737
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1263113402
Short name T877
Test name
Test status
Simulation time 464957329 ps
CPU time 3.09 seconds
Started Feb 18 12:34:44 PM PST 24
Finished Feb 18 12:34:53 PM PST 24
Peak memory 201204 kb
Host smart-6e4814f8-166b-4df3-b3f5-b82b72a04420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263113402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1263113402
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3648438900
Short name T353
Test name
Test status
Simulation time 8522054831 ps
CPU time 7.54 seconds
Started Feb 18 12:34:31 PM PST 24
Finished Feb 18 12:34:46 PM PST 24
Peak memory 201276 kb
Host smart-feeae6a0-6244-408e-9181-844e5226bf47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648438900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3648438900
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2279118372
Short name T811
Test name
Test status
Simulation time 495217188 ps
CPU time 0.95 seconds
Started Feb 18 12:34:54 PM PST 24
Finished Feb 18 12:34:59 PM PST 24
Peak memory 200812 kb
Host smart-2af64ca6-43d6-4f7b-84ad-c7cb521c8403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279118372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2279118372
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.469873114
Short name T887
Test name
Test status
Simulation time 526938961 ps
CPU time 1.27 seconds
Started Feb 18 12:34:57 PM PST 24
Finished Feb 18 12:35:03 PM PST 24
Peak memory 200764 kb
Host smart-3d8cedd3-b325-4851-8436-fb9f6e73340f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469873114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.469873114
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2615740781
Short name T862
Test name
Test status
Simulation time 322883448 ps
CPU time 0.85 seconds
Started Feb 18 12:34:57 PM PST 24
Finished Feb 18 12:35:02 PM PST 24
Peak memory 200764 kb
Host smart-bfb0d46b-336a-46cc-a2ab-35495e9ee4e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615740781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2615740781
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2185478785
Short name T894
Test name
Test status
Simulation time 539033205 ps
CPU time 1.36 seconds
Started Feb 18 12:34:53 PM PST 24
Finished Feb 18 12:34:59 PM PST 24
Peak memory 200824 kb
Host smart-8e8d70d8-e6be-403a-8528-91855fa3a843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185478785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2185478785
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2087305536
Short name T882
Test name
Test status
Simulation time 457768123 ps
CPU time 0.85 seconds
Started Feb 18 12:34:59 PM PST 24
Finished Feb 18 12:35:05 PM PST 24
Peak memory 200744 kb
Host smart-2a3d55cd-bf57-4a78-9c8f-b56b42d7d536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087305536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2087305536
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1589339085
Short name T826
Test name
Test status
Simulation time 491431227 ps
CPU time 0.93 seconds
Started Feb 18 12:34:57 PM PST 24
Finished Feb 18 12:35:02 PM PST 24
Peak memory 200692 kb
Host smart-cd4fc55e-1ebd-4895-9b3e-97aac27e8fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589339085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1589339085
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4158046760
Short name T856
Test name
Test status
Simulation time 509469869 ps
CPU time 1.23 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:04 PM PST 24
Peak memory 200764 kb
Host smart-4019c3b3-9738-4414-89ce-f99bd415907f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158046760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4158046760
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3045908097
Short name T879
Test name
Test status
Simulation time 411434469 ps
CPU time 1.62 seconds
Started Feb 18 12:34:55 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 200872 kb
Host smart-5212f94c-ad20-440d-9254-d5f9f746d07d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045908097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3045908097
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3172938855
Short name T898
Test name
Test status
Simulation time 493955369 ps
CPU time 1.72 seconds
Started Feb 18 12:35:01 PM PST 24
Finished Feb 18 12:35:07 PM PST 24
Peak memory 200752 kb
Host smart-152c2408-5161-47cc-a942-3077379b2566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172938855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3172938855
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.375674445
Short name T794
Test name
Test status
Simulation time 444983630 ps
CPU time 0.93 seconds
Started Feb 18 12:34:55 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 200792 kb
Host smart-55a740c3-2064-4a1a-b8fc-3794f40785c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375674445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.375674445
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4128228420
Short name T867
Test name
Test status
Simulation time 900449797 ps
CPU time 3.1 seconds
Started Feb 18 12:34:38 PM PST 24
Finished Feb 18 12:34:47 PM PST 24
Peak memory 212308 kb
Host smart-0219708c-8c65-4600-bc27-70f5ca7584ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128228420 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.4128228420
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2281736470
Short name T807
Test name
Test status
Simulation time 447359672 ps
CPU time 0.94 seconds
Started Feb 18 12:34:30 PM PST 24
Finished Feb 18 12:34:39 PM PST 24
Peak memory 200848 kb
Host smart-1662edda-e9e3-4062-abc9-5c1b5da46aec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281736470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2281736470
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4025497799
Short name T792
Test name
Test status
Simulation time 502215561 ps
CPU time 1.8 seconds
Started Feb 18 12:34:35 PM PST 24
Finished Feb 18 12:34:44 PM PST 24
Peak memory 200728 kb
Host smart-ec88eb47-e916-4d2b-b48e-56bab492ec99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025497799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4025497799
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2001905270
Short name T805
Test name
Test status
Simulation time 4092605224 ps
CPU time 5.02 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:54 PM PST 24
Peak memory 201212 kb
Host smart-e861aba1-b4f4-408e-9870-511fc9f02311
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001905270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2001905270
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.332380240
Short name T901
Test name
Test status
Simulation time 644131268 ps
CPU time 2.58 seconds
Started Feb 18 12:34:31 PM PST 24
Finished Feb 18 12:34:41 PM PST 24
Peak memory 209320 kb
Host smart-69aa4886-2358-4db3-9b31-b00b2fb33d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332380240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.332380240
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3306167322
Short name T852
Test name
Test status
Simulation time 8118981302 ps
CPU time 9.5 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:34:55 PM PST 24
Peak memory 201280 kb
Host smart-06dc5e95-07a7-4f4e-af60-c39e080d1f57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306167322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3306167322
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1641616578
Short name T36
Test name
Test status
Simulation time 676002990 ps
CPU time 2.1 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:49 PM PST 24
Peak memory 209356 kb
Host smart-32e3edcd-4fef-4dec-beca-423f3a13a96d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641616578 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1641616578
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1532667982
Short name T102
Test name
Test status
Simulation time 408126227 ps
CPU time 0.95 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:34:47 PM PST 24
Peak memory 200900 kb
Host smart-268580a1-0b88-448a-aee9-a91d65f44d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532667982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1532667982
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2379956717
Short name T890
Test name
Test status
Simulation time 440192888 ps
CPU time 0.86 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 200944 kb
Host smart-e94bc3d8-c59c-4660-964b-b429a0a9a07e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379956717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2379956717
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2416007568
Short name T111
Test name
Test status
Simulation time 1967882634 ps
CPU time 1.94 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:49 PM PST 24
Peak memory 200932 kb
Host smart-1d78655c-f0e7-4e69-a2f3-716aecbb6c1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416007568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2416007568
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.436820446
Short name T120
Test name
Test status
Simulation time 811112311 ps
CPU time 2.17 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:49 PM PST 24
Peak memory 209416 kb
Host smart-18596722-f4bb-4388-bbf7-8d5ff4233e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436820446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.436820446
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1452646366
Short name T350
Test name
Test status
Simulation time 8802604937 ps
CPU time 7.89 seconds
Started Feb 18 12:34:44 PM PST 24
Finished Feb 18 12:34:58 PM PST 24
Peak memory 201184 kb
Host smart-5c498598-f6af-4279-8614-30ae66f35676
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452646366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1452646366
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2886122295
Short name T886
Test name
Test status
Simulation time 1072123415 ps
CPU time 2.74 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 209276 kb
Host smart-1cf7e98e-94a4-4878-9c76-a0020c99c033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886122295 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2886122295
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.568167413
Short name T100
Test name
Test status
Simulation time 501700301 ps
CPU time 1.65 seconds
Started Feb 18 12:34:38 PM PST 24
Finished Feb 18 12:34:46 PM PST 24
Peak memory 200888 kb
Host smart-36671778-9a7d-4380-9fcc-b3076299d37b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568167413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.568167413
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1642190651
Short name T818
Test name
Test status
Simulation time 509179667 ps
CPU time 1.86 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:51 PM PST 24
Peak memory 200956 kb
Host smart-7a371a9d-2a01-49ef-9e16-dbeca3cf3da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642190651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1642190651
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2213678564
Short name T899
Test name
Test status
Simulation time 4328586417 ps
CPU time 7.83 seconds
Started Feb 18 12:34:39 PM PST 24
Finished Feb 18 12:34:53 PM PST 24
Peak memory 201256 kb
Host smart-e16c4b2a-34d7-4868-a6fd-0219038322af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213678564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2213678564
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2609987510
Short name T839
Test name
Test status
Simulation time 380837751 ps
CPU time 2.53 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 201148 kb
Host smart-e7d85077-0909-431b-b22e-439d04fa07e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609987510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2609987510
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.920480450
Short name T354
Test name
Test status
Simulation time 4072540406 ps
CPU time 4.11 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 201240 kb
Host smart-ee4aa1dc-88b9-4e08-acd4-0a44b4c48a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920480450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.920480450
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3847511068
Short name T830
Test name
Test status
Simulation time 727851658 ps
CPU time 3.33 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:51 PM PST 24
Peak memory 212784 kb
Host smart-1b3d02f8-116b-488b-910c-8a82a1d09604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847511068 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3847511068
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2100302764
Short name T853
Test name
Test status
Simulation time 392995405 ps
CPU time 1.67 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:51 PM PST 24
Peak memory 200920 kb
Host smart-4ff2997f-1f29-45c6-84d6-077aab156f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100302764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2100302764
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2974715537
Short name T793
Test name
Test status
Simulation time 513992822 ps
CPU time 1.96 seconds
Started Feb 18 12:34:45 PM PST 24
Finished Feb 18 12:34:54 PM PST 24
Peak memory 200752 kb
Host smart-a51608e3-11b0-4bab-9043-7a5a013e4408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974715537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2974715537
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.336070207
Short name T812
Test name
Test status
Simulation time 2405854445 ps
CPU time 8.29 seconds
Started Feb 18 12:34:39 PM PST 24
Finished Feb 18 12:34:53 PM PST 24
Peak memory 201036 kb
Host smart-eaaba5fe-8710-4e4a-8cd2-852215a4b1a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336070207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.336070207
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.762010251
Short name T873
Test name
Test status
Simulation time 589855687 ps
CPU time 2.35 seconds
Started Feb 18 12:34:45 PM PST 24
Finished Feb 18 12:34:55 PM PST 24
Peak memory 200384 kb
Host smart-7ac00ad8-f0ad-4b4c-a307-df1a9ec527d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762010251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.762010251
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.279500787
Short name T87
Test name
Test status
Simulation time 8079018886 ps
CPU time 21.84 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:35:09 PM PST 24
Peak memory 201296 kb
Host smart-74b19bd0-5e57-4b01-b501-cbc0be051557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279500787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.279500787
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.232408987
Short name T851
Test name
Test status
Simulation time 616314217 ps
CPU time 1.99 seconds
Started Feb 18 12:34:43 PM PST 24
Finished Feb 18 12:34:51 PM PST 24
Peak memory 209432 kb
Host smart-225ab59f-87de-4d9c-a2e3-415b9479555d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232408987 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.232408987
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3245529220
Short name T109
Test name
Test status
Simulation time 331298067 ps
CPU time 1.55 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:49 PM PST 24
Peak memory 200864 kb
Host smart-e070a0b3-9135-4cac-831e-888edddc6030
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245529220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3245529220
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3701090805
Short name T824
Test name
Test status
Simulation time 361673629 ps
CPU time 0.99 seconds
Started Feb 18 12:34:42 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 200900 kb
Host smart-11924f97-1366-4192-9bbf-8aeca577d4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701090805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3701090805
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3879695428
Short name T113
Test name
Test status
Simulation time 4893522164 ps
CPU time 6.32 seconds
Started Feb 18 12:34:44 PM PST 24
Finished Feb 18 12:34:58 PM PST 24
Peak memory 201232 kb
Host smart-6f0b5d9f-b5e8-43c6-b430-5241e9cd425f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879695428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3879695428
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2167851888
Short name T892
Test name
Test status
Simulation time 447333507 ps
CPU time 3 seconds
Started Feb 18 12:34:40 PM PST 24
Finished Feb 18 12:34:48 PM PST 24
Peak memory 217488 kb
Host smart-192b4306-6c9c-4af8-a7a0-586a5c32ef45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167851888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2167851888
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2031703149
Short name T907
Test name
Test status
Simulation time 8555930301 ps
CPU time 11.88 seconds
Started Feb 18 12:34:41 PM PST 24
Finished Feb 18 12:34:59 PM PST 24
Peak memory 201164 kb
Host smart-5b3b2747-de6b-4919-8912-c3dba31f381e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031703149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2031703149
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3842174062
Short name T233
Test name
Test status
Simulation time 167107083051 ps
CPU time 204.41 seconds
Started Feb 18 01:14:50 PM PST 24
Finished Feb 18 01:18:16 PM PST 24
Peak memory 201412 kb
Host smart-3aac00a2-5f93-4add-a152-a07e665eb51a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842174062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3842174062
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4036907967
Short name T670
Test name
Test status
Simulation time 165364381161 ps
CPU time 68.36 seconds
Started Feb 18 01:14:47 PM PST 24
Finished Feb 18 01:15:57 PM PST 24
Peak memory 201396 kb
Host smart-bd7d046c-d68a-4fab-aee6-d1fda9094034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036907967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4036907967
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1604323331
Short name T349
Test name
Test status
Simulation time 322046492420 ps
CPU time 799.71 seconds
Started Feb 18 01:14:46 PM PST 24
Finished Feb 18 01:28:07 PM PST 24
Peak memory 201488 kb
Host smart-a7086feb-5c81-42b2-a40d-d2d260f9902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604323331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1604323331
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2569425572
Short name T412
Test name
Test status
Simulation time 166963281584 ps
CPU time 147.05 seconds
Started Feb 18 01:14:45 PM PST 24
Finished Feb 18 01:17:13 PM PST 24
Peak memory 201436 kb
Host smart-7369143c-0a88-4e02-ad6e-998b9047a0cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569425572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2569425572
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1468711195
Short name T144
Test name
Test status
Simulation time 333632582608 ps
CPU time 802.59 seconds
Started Feb 18 01:14:47 PM PST 24
Finished Feb 18 01:28:12 PM PST 24
Peak memory 201488 kb
Host smart-db042089-1014-4edc-9c2a-b5bbd5c4b7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468711195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1468711195
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3694905596
Short name T690
Test name
Test status
Simulation time 495820202920 ps
CPU time 282.92 seconds
Started Feb 18 01:14:53 PM PST 24
Finished Feb 18 01:19:38 PM PST 24
Peak memory 201424 kb
Host smart-b147bf4c-dec0-4194-9e7c-defcb8f11177
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694905596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3694905596
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.937962210
Short name T286
Test name
Test status
Simulation time 170555126317 ps
CPU time 375.72 seconds
Started Feb 18 01:14:48 PM PST 24
Finished Feb 18 01:21:05 PM PST 24
Peak memory 201516 kb
Host smart-3027cb60-84cc-4901-ace0-debae1dd8d20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937962210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.937962210
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1439218719
Short name T384
Test name
Test status
Simulation time 324810649900 ps
CPU time 199.4 seconds
Started Feb 18 01:14:46 PM PST 24
Finished Feb 18 01:18:07 PM PST 24
Peak memory 201364 kb
Host smart-1571b8c4-738e-4698-9a68-723c7ed8131e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439218719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1439218719
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3997960243
Short name T720
Test name
Test status
Simulation time 80094452606 ps
CPU time 422.61 seconds
Started Feb 18 01:14:46 PM PST 24
Finished Feb 18 01:21:50 PM PST 24
Peak memory 201784 kb
Host smart-e935a46e-4880-4d5f-8c91-870cc9d75cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997960243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3997960243
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2757302065
Short name T201
Test name
Test status
Simulation time 31757331880 ps
CPU time 77.8 seconds
Started Feb 18 01:14:47 PM PST 24
Finished Feb 18 01:16:06 PM PST 24
Peak memory 201064 kb
Host smart-b15ec8c5-2e3b-4d74-834a-88b2e56f4ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757302065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2757302065
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4138850159
Short name T466
Test name
Test status
Simulation time 4862894394 ps
CPU time 5.82 seconds
Started Feb 18 01:14:45 PM PST 24
Finished Feb 18 01:14:51 PM PST 24
Peak memory 201228 kb
Host smart-62962f21-399d-463b-ab80-1074eebe2de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138850159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4138850159
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1300255028
Short name T47
Test name
Test status
Simulation time 4565347316 ps
CPU time 3.53 seconds
Started Feb 18 01:14:48 PM PST 24
Finished Feb 18 01:14:53 PM PST 24
Peak memory 216348 kb
Host smart-e1114868-257b-4aca-8b1d-9d81fbabfc4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300255028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1300255028
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1482973620
Short name T66
Test name
Test status
Simulation time 5771663131 ps
CPU time 10.12 seconds
Started Feb 18 01:14:47 PM PST 24
Finished Feb 18 01:14:58 PM PST 24
Peak memory 201152 kb
Host smart-7db19af9-82c2-48d9-995d-d552bbd3a8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482973620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1482973620
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.186347292
Short name T119
Test name
Test status
Simulation time 340078331712 ps
CPU time 162.34 seconds
Started Feb 18 01:14:46 PM PST 24
Finished Feb 18 01:17:30 PM PST 24
Peak memory 201472 kb
Host smart-d7478faf-111d-4bd7-87b4-c9ea87c5ab3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186347292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.186347292
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1446393506
Short name T582
Test name
Test status
Simulation time 438384071 ps
CPU time 0.79 seconds
Started Feb 18 01:14:53 PM PST 24
Finished Feb 18 01:14:55 PM PST 24
Peak memory 201040 kb
Host smart-25f56370-ceca-4839-8730-c7e633bec6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446393506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1446393506
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3841186926
Short name T592
Test name
Test status
Simulation time 488339501520 ps
CPU time 964.73 seconds
Started Feb 18 01:14:49 PM PST 24
Finished Feb 18 01:30:55 PM PST 24
Peak memory 201412 kb
Host smart-fc3271cb-42c3-40db-80b3-738663408eff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841186926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3841186926
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2954992728
Short name T387
Test name
Test status
Simulation time 161980947704 ps
CPU time 143.14 seconds
Started Feb 18 01:14:54 PM PST 24
Finished Feb 18 01:17:18 PM PST 24
Peak memory 201340 kb
Host smart-cf9bcc06-8fe6-4947-82d1-7e4aa55f58a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954992728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2954992728
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1638932527
Short name T543
Test name
Test status
Simulation time 488999093171 ps
CPU time 1091.61 seconds
Started Feb 18 01:14:56 PM PST 24
Finished Feb 18 01:33:09 PM PST 24
Peak memory 201424 kb
Host smart-54fa794f-bcae-4345-90e2-eb3a36b38136
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638932527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1638932527
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3513867901
Short name T55
Test name
Test status
Simulation time 163478268935 ps
CPU time 372.05 seconds
Started Feb 18 01:14:53 PM PST 24
Finished Feb 18 01:21:06 PM PST 24
Peak memory 201324 kb
Host smart-e3649fe9-f27a-4f9f-ac93-c4446419e5e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513867901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3513867901
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1457138593
Short name T708
Test name
Test status
Simulation time 328794977648 ps
CPU time 106.79 seconds
Started Feb 18 01:14:49 PM PST 24
Finished Feb 18 01:16:37 PM PST 24
Peak memory 201396 kb
Host smart-6738068f-f552-462a-b75f-b75205b0e6d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457138593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1457138593
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.97967537
Short name T415
Test name
Test status
Simulation time 24345020963 ps
CPU time 55.93 seconds
Started Feb 18 01:14:50 PM PST 24
Finished Feb 18 01:15:47 PM PST 24
Peak memory 201220 kb
Host smart-8bb0725f-2ca1-4dc0-a2dc-671811f27d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97967537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.97967537
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2749599034
Short name T388
Test name
Test status
Simulation time 3376879154 ps
CPU time 1.83 seconds
Started Feb 18 01:14:56 PM PST 24
Finished Feb 18 01:14:58 PM PST 24
Peak memory 201232 kb
Host smart-1100a602-936d-4b01-a4e0-d84dd5ccd61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749599034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2749599034
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1811332292
Short name T49
Test name
Test status
Simulation time 7454346508 ps
CPU time 17.19 seconds
Started Feb 18 01:15:00 PM PST 24
Finished Feb 18 01:15:19 PM PST 24
Peak memory 217388 kb
Host smart-c9bcb894-7ca4-4800-80dd-4b05eae41d43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811332292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1811332292
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2538164172
Short name T503
Test name
Test status
Simulation time 5834340906 ps
CPU time 14.12 seconds
Started Feb 18 01:14:54 PM PST 24
Finished Feb 18 01:15:09 PM PST 24
Peak memory 201224 kb
Host smart-804eaa28-11c5-41c3-b3c2-0af8aeaadd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538164172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2538164172
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.765164701
Short name T294
Test name
Test status
Simulation time 224552188172 ps
CPU time 122.64 seconds
Started Feb 18 01:14:57 PM PST 24
Finished Feb 18 01:17:01 PM PST 24
Peak memory 201476 kb
Host smart-cdfd85f9-7ea2-4d02-a554-f2b874c9552b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765164701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.765164701
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.501121017
Short name T716
Test name
Test status
Simulation time 369499119 ps
CPU time 1.41 seconds
Started Feb 18 01:15:41 PM PST 24
Finished Feb 18 01:15:45 PM PST 24
Peak memory 201164 kb
Host smart-3b0aaade-fb0a-4f55-b8ad-4f7a7207b253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501121017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.501121017
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2713550348
Short name T328
Test name
Test status
Simulation time 161549823402 ps
CPU time 96.36 seconds
Started Feb 18 01:15:47 PM PST 24
Finished Feb 18 01:17:24 PM PST 24
Peak memory 201516 kb
Host smart-cf3d151e-db79-4102-aa4f-45f399cbf1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713550348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2713550348
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2783182786
Short name T174
Test name
Test status
Simulation time 493481312452 ps
CPU time 281.33 seconds
Started Feb 18 01:15:40 PM PST 24
Finished Feb 18 01:20:24 PM PST 24
Peak memory 201428 kb
Host smart-6df2ed84-a359-43db-b523-1bad25060427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783182786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2783182786
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.446911289
Short name T506
Test name
Test status
Simulation time 164788094066 ps
CPU time 287.13 seconds
Started Feb 18 01:15:51 PM PST 24
Finished Feb 18 01:20:39 PM PST 24
Peak memory 201416 kb
Host smart-577e348e-efe8-4d91-a2c0-88ad045ddabc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=446911289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.446911289
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2729583219
Short name T771
Test name
Test status
Simulation time 164851588776 ps
CPU time 402.76 seconds
Started Feb 18 01:15:26 PM PST 24
Finished Feb 18 01:22:10 PM PST 24
Peak memory 201504 kb
Host smart-1822e77f-be06-4ac7-8cc9-7112047aa7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729583219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2729583219
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2415941794
Short name T787
Test name
Test status
Simulation time 162273111233 ps
CPU time 346.51 seconds
Started Feb 18 01:15:25 PM PST 24
Finished Feb 18 01:21:13 PM PST 24
Peak memory 201460 kb
Host smart-53f83d37-0f6a-41f0-83b7-9865c08cf095
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415941794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2415941794
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3621435414
Short name T707
Test name
Test status
Simulation time 169103778585 ps
CPU time 367.41 seconds
Started Feb 18 01:15:37 PM PST 24
Finished Feb 18 01:21:47 PM PST 24
Peak memory 201404 kb
Host smart-85ebc475-b8d1-4644-bd96-4e12179e6715
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621435414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3621435414
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1680896036
Short name T449
Test name
Test status
Simulation time 91957147353 ps
CPU time 380.49 seconds
Started Feb 18 01:15:40 PM PST 24
Finished Feb 18 01:22:03 PM PST 24
Peak memory 201728 kb
Host smart-6a8c0d67-973e-43b5-87e5-48871d4494dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680896036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1680896036
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.4155485777
Short name T461
Test name
Test status
Simulation time 31731943935 ps
CPU time 12.03 seconds
Started Feb 18 01:15:48 PM PST 24
Finished Feb 18 01:16:01 PM PST 24
Peak memory 201232 kb
Host smart-12720d6d-b6d4-4173-983f-9a8f7885e053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155485777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.4155485777
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3637809241
Short name T475
Test name
Test status
Simulation time 5277180131 ps
CPU time 12.56 seconds
Started Feb 18 01:15:35 PM PST 24
Finished Feb 18 01:15:49 PM PST 24
Peak memory 201232 kb
Host smart-a8080bc7-56c2-499a-92b5-65deba27cb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637809241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3637809241
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2003435284
Short name T425
Test name
Test status
Simulation time 6097719324 ps
CPU time 4.19 seconds
Started Feb 18 01:15:29 PM PST 24
Finished Feb 18 01:15:34 PM PST 24
Peak memory 201172 kb
Host smart-58feb25f-823b-4f5c-91b1-7c0a5d2934a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003435284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2003435284
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.966404644
Short name T754
Test name
Test status
Simulation time 473180689618 ps
CPU time 648.32 seconds
Started Feb 18 01:15:56 PM PST 24
Finished Feb 18 01:26:45 PM PST 24
Peak memory 201756 kb
Host smart-e7727027-8e79-4ef7-80a8-e7911305113b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966404644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
966404644
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.47283454
Short name T375
Test name
Test status
Simulation time 491583191 ps
CPU time 1.1 seconds
Started Feb 18 01:15:41 PM PST 24
Finished Feb 18 01:15:45 PM PST 24
Peak memory 201152 kb
Host smart-6f949ffa-a873-4b9f-9470-30613992773b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47283454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.47283454
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.229524169
Short name T232
Test name
Test status
Simulation time 163291985031 ps
CPU time 321.17 seconds
Started Feb 18 01:15:40 PM PST 24
Finished Feb 18 01:21:04 PM PST 24
Peak memory 201544 kb
Host smart-aab9bc9a-1283-4268-a467-18a6e5a6f984
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229524169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.229524169
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2631486651
Short name T137
Test name
Test status
Simulation time 164880532609 ps
CPU time 372.14 seconds
Started Feb 18 01:15:40 PM PST 24
Finished Feb 18 01:21:55 PM PST 24
Peak memory 201468 kb
Host smart-a0cdcf4d-3d0e-4850-b3ff-570aa39a8cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631486651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2631486651
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3400828652
Short name T594
Test name
Test status
Simulation time 166945816591 ps
CPU time 51.32 seconds
Started Feb 18 01:15:35 PM PST 24
Finished Feb 18 01:16:27 PM PST 24
Peak memory 201440 kb
Host smart-300f571d-52de-40de-b977-06de99b86ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400828652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3400828652
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2895671272
Short name T430
Test name
Test status
Simulation time 330281415841 ps
CPU time 208.43 seconds
Started Feb 18 01:15:43 PM PST 24
Finished Feb 18 01:19:13 PM PST 24
Peak memory 201424 kb
Host smart-4ac9b191-48a0-48c8-88f2-7a58a3724600
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895671272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2895671272
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2194099053
Short name T785
Test name
Test status
Simulation time 164266188533 ps
CPU time 102.38 seconds
Started Feb 18 01:15:41 PM PST 24
Finished Feb 18 01:17:26 PM PST 24
Peak memory 201476 kb
Host smart-fd16fe5b-a67e-45aa-b722-10964ad49fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194099053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2194099053
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2742608364
Short name T697
Test name
Test status
Simulation time 495786705795 ps
CPU time 175.65 seconds
Started Feb 18 01:15:42 PM PST 24
Finished Feb 18 01:18:40 PM PST 24
Peak memory 201412 kb
Host smart-191861f5-bd56-47fc-a8c6-ee53ca4f461b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742608364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2742608364
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.980085105
Short name T513
Test name
Test status
Simulation time 169160749703 ps
CPU time 408.96 seconds
Started Feb 18 01:15:45 PM PST 24
Finished Feb 18 01:22:35 PM PST 24
Peak memory 201372 kb
Host smart-3969dada-46de-4f50-8c85-c5484105dfa5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980085105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.980085105
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.673722508
Short name T693
Test name
Test status
Simulation time 332900734839 ps
CPU time 596.6 seconds
Started Feb 18 01:15:37 PM PST 24
Finished Feb 18 01:25:35 PM PST 24
Peak memory 201380 kb
Host smart-1757c878-d45c-4fdb-932b-664b672d3882
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673722508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.673722508
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3645372804
Short name T630
Test name
Test status
Simulation time 27087740890 ps
CPU time 60.46 seconds
Started Feb 18 01:15:36 PM PST 24
Finished Feb 18 01:16:38 PM PST 24
Peak memory 201060 kb
Host smart-bc49e393-1ad9-4a18-ad4b-103196243c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645372804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3645372804
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.4209810735
Short name T433
Test name
Test status
Simulation time 3538036040 ps
CPU time 4.81 seconds
Started Feb 18 01:15:42 PM PST 24
Finished Feb 18 01:15:49 PM PST 24
Peak memory 201240 kb
Host smart-78c5367e-13a1-440a-9c82-2a54490ac1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209810735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.4209810735
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3936031699
Short name T479
Test name
Test status
Simulation time 6000183211 ps
CPU time 13.04 seconds
Started Feb 18 01:15:42 PM PST 24
Finished Feb 18 01:15:58 PM PST 24
Peak memory 201136 kb
Host smart-dc832556-0a61-43d3-94e7-abbebec0a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936031699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3936031699
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3526465432
Short name T618
Test name
Test status
Simulation time 329968391984 ps
CPU time 626.66 seconds
Started Feb 18 01:15:42 PM PST 24
Finished Feb 18 01:26:11 PM PST 24
Peak memory 201492 kb
Host smart-45e7b660-786b-4ceb-84ed-133e3077e379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526465432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3526465432
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1336649861
Short name T620
Test name
Test status
Simulation time 286958543 ps
CPU time 1.34 seconds
Started Feb 18 01:15:39 PM PST 24
Finished Feb 18 01:15:43 PM PST 24
Peak memory 201152 kb
Host smart-f409b9d3-0059-49b4-a7d8-e944520f40b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336649861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1336649861
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3379003985
Short name T554
Test name
Test status
Simulation time 488164159959 ps
CPU time 964 seconds
Started Feb 18 01:15:41 PM PST 24
Finished Feb 18 01:31:48 PM PST 24
Peak memory 201404 kb
Host smart-d6a186fc-2ad8-43db-88c2-49e7d014e44a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379003985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3379003985
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2083107564
Short name T490
Test name
Test status
Simulation time 491799690505 ps
CPU time 548.81 seconds
Started Feb 18 01:15:39 PM PST 24
Finished Feb 18 01:24:50 PM PST 24
Peak memory 201464 kb
Host smart-07d323a9-de86-4657-987c-12e0b0bba50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083107564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2083107564
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.614051356
Short name T740
Test name
Test status
Simulation time 166494786277 ps
CPU time 308.99 seconds
Started Feb 18 01:15:40 PM PST 24
Finished Feb 18 01:20:51 PM PST 24
Peak memory 201504 kb
Host smart-be50e7c1-d892-44f4-b442-1e879b34ff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614051356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.614051356
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1358279753
Short name T407
Test name
Test status
Simulation time 334876209528 ps
CPU time 199.23 seconds
Started Feb 18 01:15:41 PM PST 24
Finished Feb 18 01:19:03 PM PST 24
Peak memory 201328 kb
Host smart-3481bcaf-6c22-4840-a166-835acf43924d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358279753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1358279753
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3769379514
Short name T628
Test name
Test status
Simulation time 160181026570 ps
CPU time 105.65 seconds
Started Feb 18 01:15:45 PM PST 24
Finished Feb 18 01:17:32 PM PST 24
Peak memory 201420 kb
Host smart-e9dd3f7b-e19f-416f-aa15-9e5b93970ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769379514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3769379514
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1379073595
Short name T13
Test name
Test status
Simulation time 165840039294 ps
CPU time 174.75 seconds
Started Feb 18 01:15:43 PM PST 24
Finished Feb 18 01:18:40 PM PST 24
Peak memory 201468 kb
Host smart-e8369d68-be25-4784-a5f8-88dbc75905e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379073595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1379073595
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2076272170
Short name T496
Test name
Test status
Simulation time 166703734425 ps
CPU time 220.92 seconds
Started Feb 18 01:15:39 PM PST 24
Finished Feb 18 01:19:22 PM PST 24
Peak memory 201516 kb
Host smart-9cea664c-bf9e-41a4-871d-f02506bdd1ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076272170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2076272170
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1770880676
Short name T596
Test name
Test status
Simulation time 164941323085 ps
CPU time 213.95 seconds
Started Feb 18 01:15:42 PM PST 24
Finished Feb 18 01:19:19 PM PST 24
Peak memory 201416 kb
Host smart-d5f3573b-6d52-466b-9370-17cce2179671
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770880676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1770880676
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1267496920
Short name T216
Test name
Test status
Simulation time 95950191053 ps
CPU time 532.18 seconds
Started Feb 18 01:15:43 PM PST 24
Finished Feb 18 01:24:37 PM PST 24
Peak memory 201804 kb
Host smart-7bfffc8b-b1a1-4d44-87a9-98ab9dd8ad34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267496920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1267496920
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2894368611
Short name T362
Test name
Test status
Simulation time 37429935986 ps
CPU time 85.24 seconds
Started Feb 18 01:15:41 PM PST 24
Finished Feb 18 01:17:09 PM PST 24
Peak memory 201176 kb
Host smart-7d4a1487-521f-43dc-9541-86d96fec5ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894368611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2894368611
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3205773550
Short name T369
Test name
Test status
Simulation time 2652776988 ps
CPU time 3.75 seconds
Started Feb 18 01:15:40 PM PST 24
Finished Feb 18 01:15:47 PM PST 24
Peak memory 201228 kb
Host smart-e6fcd88a-9c73-44cb-b361-947f10e0e5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205773550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3205773550
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4266713318
Short name T614
Test name
Test status
Simulation time 5884731659 ps
CPU time 4.21 seconds
Started Feb 18 01:15:41 PM PST 24
Finished Feb 18 01:15:48 PM PST 24
Peak memory 201220 kb
Host smart-259aef1d-4013-41ff-8514-925d389b4644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266713318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4266713318
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2775322101
Short name T60
Test name
Test status
Simulation time 135162663041 ps
CPU time 158.25 seconds
Started Feb 18 01:15:40 PM PST 24
Finished Feb 18 01:18:21 PM PST 24
Peak memory 209948 kb
Host smart-32bd24e8-bda5-4e3b-8120-a8278930300b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775322101 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2775322101
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2234898477
Short name T673
Test name
Test status
Simulation time 436374773 ps
CPU time 0.74 seconds
Started Feb 18 01:15:53 PM PST 24
Finished Feb 18 01:15:55 PM PST 24
Peak memory 201096 kb
Host smart-9edf1481-35db-43e2-a293-46509b696c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234898477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2234898477
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1540092342
Short name T231
Test name
Test status
Simulation time 490452704968 ps
CPU time 103.19 seconds
Started Feb 18 01:15:50 PM PST 24
Finished Feb 18 01:17:33 PM PST 24
Peak memory 201428 kb
Host smart-aafac61e-8e58-40e3-ae39-27629b3b74a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540092342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1540092342
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3347226486
Short name T291
Test name
Test status
Simulation time 502031036244 ps
CPU time 359.67 seconds
Started Feb 18 01:15:50 PM PST 24
Finished Feb 18 01:21:50 PM PST 24
Peak memory 201528 kb
Host smart-9ee28846-5160-4337-8a27-7fbab418caef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347226486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3347226486
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3266957276
Short name T743
Test name
Test status
Simulation time 494097592844 ps
CPU time 290.4 seconds
Started Feb 18 01:15:55 PM PST 24
Finished Feb 18 01:20:46 PM PST 24
Peak memory 201492 kb
Host smart-5e5b6f33-ab21-41e8-8c70-f88aab7bc091
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266957276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3266957276
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2802442
Short name T133
Test name
Test status
Simulation time 488957958910 ps
CPU time 296.55 seconds
Started Feb 18 01:15:48 PM PST 24
Finished Feb 18 01:20:45 PM PST 24
Peak memory 201440 kb
Host smart-f53636cf-df1b-4220-aa40-056d1ca328e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2802442
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.917804016
Short name T565
Test name
Test status
Simulation time 162315822013 ps
CPU time 342.32 seconds
Started Feb 18 01:15:47 PM PST 24
Finished Feb 18 01:21:31 PM PST 24
Peak memory 201460 kb
Host smart-5b0d0d92-ac9e-4d12-960b-972ae89f36ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=917804016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.917804016
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2899101376
Short name T139
Test name
Test status
Simulation time 334763940526 ps
CPU time 371.15 seconds
Started Feb 18 01:15:55 PM PST 24
Finished Feb 18 01:22:07 PM PST 24
Peak memory 201488 kb
Host smart-bf60be52-e55c-4d7c-bccc-b69936af84fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899101376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2899101376
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3669502544
Short name T790
Test name
Test status
Simulation time 160951015184 ps
CPU time 91.27 seconds
Started Feb 18 01:15:48 PM PST 24
Finished Feb 18 01:17:20 PM PST 24
Peak memory 201476 kb
Host smart-9e8a6305-03d8-4942-a485-1d2ac5ae8e4d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669502544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3669502544
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2919697257
Short name T210
Test name
Test status
Simulation time 91740316060 ps
CPU time 489.1 seconds
Started Feb 18 01:15:52 PM PST 24
Finished Feb 18 01:24:03 PM PST 24
Peak memory 201740 kb
Host smart-83d1d416-e516-4471-ac93-76f34906927d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919697257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2919697257
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2145983109
Short name T499
Test name
Test status
Simulation time 47244634563 ps
CPU time 53.32 seconds
Started Feb 18 01:15:55 PM PST 24
Finished Feb 18 01:16:49 PM PST 24
Peak memory 201244 kb
Host smart-7171cec1-c4fb-4789-9bc0-35975b9bc076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145983109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2145983109
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3395622848
Short name T660
Test name
Test status
Simulation time 5016794854 ps
CPU time 11.94 seconds
Started Feb 18 01:15:48 PM PST 24
Finished Feb 18 01:16:00 PM PST 24
Peak memory 201156 kb
Host smart-9e8f10cb-394d-4d9e-901d-d47911052be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395622848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3395622848
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2208555927
Short name T564
Test name
Test status
Simulation time 5971711501 ps
CPU time 14.51 seconds
Started Feb 18 01:15:49 PM PST 24
Finished Feb 18 01:16:04 PM PST 24
Peak memory 201128 kb
Host smart-431d20ad-d7be-47a3-894b-7dd0027b0f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208555927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2208555927
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1456467193
Short name T40
Test name
Test status
Simulation time 436959536588 ps
CPU time 287.81 seconds
Started Feb 18 01:15:52 PM PST 24
Finished Feb 18 01:20:41 PM PST 24
Peak memory 210028 kb
Host smart-062e3421-4019-4818-8392-e60ab84d8be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456467193 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1456467193
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.262191555
Short name T377
Test name
Test status
Simulation time 323261144 ps
CPU time 1.32 seconds
Started Feb 18 01:16:01 PM PST 24
Finished Feb 18 01:16:03 PM PST 24
Peak memory 201140 kb
Host smart-36205bf4-2373-41ab-a864-6d8cf9eb605c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262191555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.262191555
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3573654158
Short name T718
Test name
Test status
Simulation time 325610580622 ps
CPU time 269.52 seconds
Started Feb 18 01:15:54 PM PST 24
Finished Feb 18 01:20:25 PM PST 24
Peak memory 201420 kb
Host smart-91dd9649-1713-4339-8e64-773c30b96b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573654158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3573654158
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3507834327
Short name T507
Test name
Test status
Simulation time 489142209086 ps
CPU time 117.31 seconds
Started Feb 18 01:15:54 PM PST 24
Finished Feb 18 01:17:52 PM PST 24
Peak memory 201336 kb
Host smart-83835a56-ead8-43a8-8231-b018102e1ff0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507834327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3507834327
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2175724188
Short name T553
Test name
Test status
Simulation time 499598188880 ps
CPU time 531.5 seconds
Started Feb 18 01:15:56 PM PST 24
Finished Feb 18 01:24:49 PM PST 24
Peak memory 201428 kb
Host smart-99992a6d-8119-48dc-b27f-f37a868666c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175724188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2175724188
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3472576059
Short name T497
Test name
Test status
Simulation time 335760132243 ps
CPU time 785.86 seconds
Started Feb 18 01:16:02 PM PST 24
Finished Feb 18 01:29:09 PM PST 24
Peak memory 201488 kb
Host smart-f07d42a4-d772-4419-93f4-bb952a391c53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472576059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3472576059
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.19478653
Short name T777
Test name
Test status
Simulation time 493105121168 ps
CPU time 289.07 seconds
Started Feb 18 01:15:58 PM PST 24
Finished Feb 18 01:20:48 PM PST 24
Peak memory 201520 kb
Host smart-a176e304-973d-4a90-8365-8dc4cdac8a04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19478653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.a
dc_ctrl_filters_wakeup_fixed.19478653
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2865139463
Short name T556
Test name
Test status
Simulation time 83861563816 ps
CPU time 260.1 seconds
Started Feb 18 01:16:04 PM PST 24
Finished Feb 18 01:20:25 PM PST 24
Peak memory 201800 kb
Host smart-93846bf7-3be8-4a58-bac5-2f61e306a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865139463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2865139463
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3157160140
Short name T571
Test name
Test status
Simulation time 35673793854 ps
CPU time 77.99 seconds
Started Feb 18 01:15:56 PM PST 24
Finished Feb 18 01:17:15 PM PST 24
Peak memory 201236 kb
Host smart-d1ff2563-fd7d-43a8-af2d-ae7b8ee7860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157160140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3157160140
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1227053641
Short name T627
Test name
Test status
Simulation time 3669651232 ps
CPU time 1.6 seconds
Started Feb 18 01:15:53 PM PST 24
Finished Feb 18 01:15:56 PM PST 24
Peak memory 201224 kb
Host smart-e2bd3218-1ffe-475b-aa39-056f9d08e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227053641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1227053641
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3024438867
Short name T504
Test name
Test status
Simulation time 6207265853 ps
CPU time 1.65 seconds
Started Feb 18 01:15:51 PM PST 24
Finished Feb 18 01:15:54 PM PST 24
Peak memory 201188 kb
Host smart-afa044c0-cf11-4de2-b0bd-3c6d65e6f2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024438867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3024438867
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3655571245
Short name T591
Test name
Test status
Simulation time 366122791 ps
CPU time 1.41 seconds
Started Feb 18 01:16:16 PM PST 24
Finished Feb 18 01:16:20 PM PST 24
Peak memory 201184 kb
Host smart-296a1644-87e4-4567-8107-0101e3ab549f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655571245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3655571245
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3849560080
Short name T734
Test name
Test status
Simulation time 167459119263 ps
CPU time 92.16 seconds
Started Feb 18 01:15:58 PM PST 24
Finished Feb 18 01:17:31 PM PST 24
Peak memory 201480 kb
Host smart-a7e1eb7b-917e-4e73-95c6-48962ebfeece
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849560080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3849560080
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3246921255
Short name T235
Test name
Test status
Simulation time 159153982513 ps
CPU time 159.44 seconds
Started Feb 18 01:15:58 PM PST 24
Finished Feb 18 01:18:39 PM PST 24
Peak memory 201520 kb
Host smart-94643e77-85e7-4bc9-8ae1-c41ae9fc76f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246921255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3246921255
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4187763134
Short name T439
Test name
Test status
Simulation time 502173973253 ps
CPU time 1150.91 seconds
Started Feb 18 01:16:04 PM PST 24
Finished Feb 18 01:35:16 PM PST 24
Peak memory 201424 kb
Host smart-70428033-00e2-42ed-8e1a-7a482f29c06c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187763134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.4187763134
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3878205507
Short name T649
Test name
Test status
Simulation time 487266486918 ps
CPU time 259.37 seconds
Started Feb 18 01:16:01 PM PST 24
Finished Feb 18 01:20:22 PM PST 24
Peak memory 201376 kb
Host smart-7c25116e-3d0a-4fa3-9d33-63256d6d9245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878205507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3878205507
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3467610711
Short name T164
Test name
Test status
Simulation time 331049603151 ps
CPU time 202.54 seconds
Started Feb 18 01:16:01 PM PST 24
Finished Feb 18 01:19:24 PM PST 24
Peak memory 201480 kb
Host smart-e7d8576c-2204-42f9-8c3f-ea824e277af7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467610711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3467610711
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1549051022
Short name T278
Test name
Test status
Simulation time 170846303151 ps
CPU time 394.12 seconds
Started Feb 18 01:16:02 PM PST 24
Finished Feb 18 01:22:37 PM PST 24
Peak memory 201452 kb
Host smart-a79480fe-e4e4-4493-befd-ea8ac697c8c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549051022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1549051022
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1902091020
Short name T687
Test name
Test status
Simulation time 493265893310 ps
CPU time 1168.97 seconds
Started Feb 18 01:15:59 PM PST 24
Finished Feb 18 01:35:29 PM PST 24
Peak memory 201484 kb
Host smart-d342f7af-a7f3-422e-b961-69c55d3a0e46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902091020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1902091020
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2406552098
Short name T757
Test name
Test status
Simulation time 81342924037 ps
CPU time 414.14 seconds
Started Feb 18 01:16:09 PM PST 24
Finished Feb 18 01:23:05 PM PST 24
Peak memory 201672 kb
Host smart-63eed782-189e-42a0-b407-65a1b3958ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406552098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2406552098
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3597129476
Short name T189
Test name
Test status
Simulation time 35167600439 ps
CPU time 15.64 seconds
Started Feb 18 01:16:16 PM PST 24
Finished Feb 18 01:16:34 PM PST 24
Peak memory 201220 kb
Host smart-73bce7de-b7f9-40a1-9bac-f0a5b8750852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597129476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3597129476
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.851096790
Short name T478
Test name
Test status
Simulation time 4034746094 ps
CPU time 1.81 seconds
Started Feb 18 01:16:10 PM PST 24
Finished Feb 18 01:16:13 PM PST 24
Peak memory 201192 kb
Host smart-08348278-503d-4a65-8531-c3a2b0b9360d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851096790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.851096790
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.4241967882
Short name T409
Test name
Test status
Simulation time 5600320567 ps
CPU time 12.07 seconds
Started Feb 18 01:16:00 PM PST 24
Finished Feb 18 01:16:12 PM PST 24
Peak memory 201168 kb
Host smart-dd186c4b-f2d7-402b-88de-70d272f484bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241967882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.4241967882
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2660139339
Short name T465
Test name
Test status
Simulation time 175410654514 ps
CPU time 92.98 seconds
Started Feb 18 01:16:16 PM PST 24
Finished Feb 18 01:17:51 PM PST 24
Peak memory 201460 kb
Host smart-3e0d12f4-e2d3-49c1-91cf-154543048747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660139339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2660139339
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4103142244
Short name T187
Test name
Test status
Simulation time 28515640865 ps
CPU time 12.97 seconds
Started Feb 18 01:16:10 PM PST 24
Finished Feb 18 01:16:25 PM PST 24
Peak memory 201572 kb
Host smart-89ecb6e9-7627-4fb3-a668-0009ee64e540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103142244 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4103142244
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1348544075
Short name T756
Test name
Test status
Simulation time 549770731 ps
CPU time 0.96 seconds
Started Feb 18 01:16:22 PM PST 24
Finished Feb 18 01:16:25 PM PST 24
Peak memory 201160 kb
Host smart-06b69fcd-f3f5-442d-9acc-897f145361de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348544075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1348544075
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1364414437
Short name T225
Test name
Test status
Simulation time 162980050502 ps
CPU time 184.7 seconds
Started Feb 18 01:16:21 PM PST 24
Finished Feb 18 01:19:27 PM PST 24
Peak memory 201536 kb
Host smart-b81a5144-5933-486a-aa4f-4a98aa398564
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364414437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1364414437
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.695681003
Short name T182
Test name
Test status
Simulation time 163146115122 ps
CPU time 355.6 seconds
Started Feb 18 01:16:15 PM PST 24
Finished Feb 18 01:22:12 PM PST 24
Peak memory 201448 kb
Host smart-f665e470-78dd-4653-a6df-a6209abb4b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695681003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.695681003
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.645354171
Short name T549
Test name
Test status
Simulation time 325491058902 ps
CPU time 197.98 seconds
Started Feb 18 01:16:17 PM PST 24
Finished Feb 18 01:19:37 PM PST 24
Peak memory 201464 kb
Host smart-c103e938-97a1-4ffe-a450-12b02a357659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645354171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.645354171
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3150107543
Short name T691
Test name
Test status
Simulation time 323945829889 ps
CPU time 302.58 seconds
Started Feb 18 01:16:17 PM PST 24
Finished Feb 18 01:21:22 PM PST 24
Peak memory 201424 kb
Host smart-d4604afc-1390-4921-80f5-71cd1e11b853
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150107543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3150107543
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3398082096
Short name T604
Test name
Test status
Simulation time 334001474538 ps
CPU time 145.73 seconds
Started Feb 18 01:16:15 PM PST 24
Finished Feb 18 01:18:44 PM PST 24
Peak memory 201512 kb
Host smart-5cefbab8-5822-49c5-a2c3-6857ad97e730
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398082096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3398082096
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1141919157
Short name T203
Test name
Test status
Simulation time 36373822732 ps
CPU time 16.77 seconds
Started Feb 18 01:16:27 PM PST 24
Finished Feb 18 01:16:44 PM PST 24
Peak memory 201236 kb
Host smart-8f621b00-2dbe-42f1-a08f-db6b53f39684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141919157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1141919157
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3434612906
Short name T640
Test name
Test status
Simulation time 3331508218 ps
CPU time 7.64 seconds
Started Feb 18 01:16:17 PM PST 24
Finished Feb 18 01:16:27 PM PST 24
Peak memory 201240 kb
Host smart-653770bd-7d6f-4458-843d-7299cf49c58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434612906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3434612906
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1310959570
Short name T403
Test name
Test status
Simulation time 5679179606 ps
CPU time 4.29 seconds
Started Feb 18 01:16:16 PM PST 24
Finished Feb 18 01:16:22 PM PST 24
Peak memory 201108 kb
Host smart-7faff8a6-9d88-4fe6-8023-1a0e9113be7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310959570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1310959570
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3576985291
Short name T665
Test name
Test status
Simulation time 306462514121 ps
CPU time 433.74 seconds
Started Feb 18 01:16:22 PM PST 24
Finished Feb 18 01:23:38 PM PST 24
Peak memory 209940 kb
Host smart-728c591f-2cdc-4a87-ac1e-59ff93c05eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576985291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3576985291
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2868955711
Short name T272
Test name
Test status
Simulation time 28211590127 ps
CPU time 67.33 seconds
Started Feb 18 01:16:23 PM PST 24
Finished Feb 18 01:17:32 PM PST 24
Peak memory 217732 kb
Host smart-d821c31a-1d66-4167-b4f1-74960f3e6185
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868955711 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2868955711
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3148122379
Short name T635
Test name
Test status
Simulation time 483583864 ps
CPU time 1.68 seconds
Started Feb 18 01:16:27 PM PST 24
Finished Feb 18 01:16:30 PM PST 24
Peak memory 201148 kb
Host smart-34fb662a-e646-453e-b333-82f986c171e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148122379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3148122379
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2435962006
Short name T268
Test name
Test status
Simulation time 167523201043 ps
CPU time 98.65 seconds
Started Feb 18 01:16:27 PM PST 24
Finished Feb 18 01:18:06 PM PST 24
Peak memory 201428 kb
Host smart-2f96b941-8a1c-4c2e-82dd-1c00ac1872b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435962006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2435962006
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3922162506
Short name T331
Test name
Test status
Simulation time 172998878815 ps
CPU time 207.41 seconds
Started Feb 18 01:16:20 PM PST 24
Finished Feb 18 01:19:49 PM PST 24
Peak memory 201492 kb
Host smart-db4f3836-e9a8-43b6-83aa-665619a3fe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922162506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3922162506
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.888024072
Short name T348
Test name
Test status
Simulation time 489447250475 ps
CPU time 1009.85 seconds
Started Feb 18 01:16:22 PM PST 24
Finished Feb 18 01:33:14 PM PST 24
Peak memory 201440 kb
Host smart-592ffee3-7afd-4a21-a71a-6eb8ecb943ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888024072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.888024072
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1080900804
Short name T427
Test name
Test status
Simulation time 325230381781 ps
CPU time 674.3 seconds
Started Feb 18 01:16:21 PM PST 24
Finished Feb 18 01:27:37 PM PST 24
Peak memory 201344 kb
Host smart-543b202a-c073-4a91-b73e-02cc5bcb3493
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080900804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1080900804
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2969037709
Short name T338
Test name
Test status
Simulation time 162668339170 ps
CPU time 307.09 seconds
Started Feb 18 01:16:23 PM PST 24
Finished Feb 18 01:21:32 PM PST 24
Peak memory 201360 kb
Host smart-e05cb4bc-2457-4dc8-a1b7-c2d4fdffc879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969037709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2969037709
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1387487884
Short name T788
Test name
Test status
Simulation time 326115488133 ps
CPU time 386.3 seconds
Started Feb 18 01:16:26 PM PST 24
Finished Feb 18 01:22:53 PM PST 24
Peak memory 201408 kb
Host smart-06e66e5f-db11-40e1-bf45-b0ab8f90a952
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387487884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1387487884
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.548903502
Short name T763
Test name
Test status
Simulation time 341603408530 ps
CPU time 409.17 seconds
Started Feb 18 01:16:22 PM PST 24
Finished Feb 18 01:23:14 PM PST 24
Peak memory 201360 kb
Host smart-4ead2121-c346-4bb3-be30-e6a441596e75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548903502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.548903502
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2555460407
Short name T588
Test name
Test status
Simulation time 496001009533 ps
CPU time 303.05 seconds
Started Feb 18 01:16:22 PM PST 24
Finished Feb 18 01:21:26 PM PST 24
Peak memory 201500 kb
Host smart-43d2d6ad-30cd-4571-9636-2d37066fb8cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555460407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2555460407
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2841656716
Short name T223
Test name
Test status
Simulation time 134800716957 ps
CPU time 554.71 seconds
Started Feb 18 01:16:29 PM PST 24
Finished Feb 18 01:25:44 PM PST 24
Peak memory 201804 kb
Host smart-f9c376e3-c601-45a9-a802-86ba8f5ac1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841656716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2841656716
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1448788544
Short name T547
Test name
Test status
Simulation time 37150766531 ps
CPU time 44.62 seconds
Started Feb 18 01:16:28 PM PST 24
Finished Feb 18 01:17:14 PM PST 24
Peak memory 201200 kb
Host smart-73333327-284a-4600-aa5d-d853fcb88a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448788544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1448788544
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3857326098
Short name T613
Test name
Test status
Simulation time 5577187400 ps
CPU time 12.89 seconds
Started Feb 18 01:16:28 PM PST 24
Finished Feb 18 01:16:41 PM PST 24
Peak memory 201236 kb
Host smart-69975814-881c-40b4-9455-2711c0dd320d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857326098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3857326098
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1494292747
Short name T508
Test name
Test status
Simulation time 5618128212 ps
CPU time 14.62 seconds
Started Feb 18 01:16:24 PM PST 24
Finished Feb 18 01:16:40 PM PST 24
Peak memory 201196 kb
Host smart-342a1c70-1eae-4402-a504-61be8d48e3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494292747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1494292747
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2119923774
Short name T561
Test name
Test status
Simulation time 296873351827 ps
CPU time 1005.27 seconds
Started Feb 18 01:16:28 PM PST 24
Finished Feb 18 01:33:14 PM PST 24
Peak memory 212024 kb
Host smart-9951205b-0854-4b49-be8d-82da42060ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119923774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2119923774
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.860950855
Short name T289
Test name
Test status
Simulation time 375582827935 ps
CPU time 236.92 seconds
Started Feb 18 01:16:30 PM PST 24
Finished Feb 18 01:20:27 PM PST 24
Peak memory 210104 kb
Host smart-e6a6e060-e0e7-48fe-ac1e-a91ff8ec70a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860950855 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.860950855
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2174585665
Short name T768
Test name
Test status
Simulation time 385023465 ps
CPU time 1.36 seconds
Started Feb 18 01:16:36 PM PST 24
Finished Feb 18 01:16:40 PM PST 24
Peak memory 201104 kb
Host smart-da3d6a99-a023-4ce8-999d-1d27cd1bf74d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174585665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2174585665
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1391899503
Short name T516
Test name
Test status
Simulation time 496943986282 ps
CPU time 369.8 seconds
Started Feb 18 01:16:29 PM PST 24
Finished Feb 18 01:22:40 PM PST 24
Peak memory 201488 kb
Host smart-be40e9e4-7bb8-49c1-9e56-96f5b84a4fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391899503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1391899503
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.362579530
Short name T671
Test name
Test status
Simulation time 486236202545 ps
CPU time 555.65 seconds
Started Feb 18 01:16:29 PM PST 24
Finished Feb 18 01:25:45 PM PST 24
Peak memory 201296 kb
Host smart-0c5ce582-c7fc-4c48-a6a6-c7df74c51d40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=362579530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.362579530
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2213352462
Short name T300
Test name
Test status
Simulation time 483500406376 ps
CPU time 1107.86 seconds
Started Feb 18 01:16:28 PM PST 24
Finished Feb 18 01:34:57 PM PST 24
Peak memory 201452 kb
Host smart-59693241-6474-4b73-9a8a-59ebd125650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213352462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2213352462
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.828071111
Short name T522
Test name
Test status
Simulation time 493868246688 ps
CPU time 905.88 seconds
Started Feb 18 01:16:29 PM PST 24
Finished Feb 18 01:31:36 PM PST 24
Peak memory 201484 kb
Host smart-9497d567-67d1-4480-9626-01d63d1fd9ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=828071111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.828071111
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.4286460327
Short name T243
Test name
Test status
Simulation time 588560389497 ps
CPU time 373.2 seconds
Started Feb 18 01:16:29 PM PST 24
Finished Feb 18 01:22:43 PM PST 24
Peak memory 201424 kb
Host smart-2392d66d-6711-400b-8b88-0c793e042d45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286460327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.4286460327
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2535256220
Short name T464
Test name
Test status
Simulation time 481655695015 ps
CPU time 239.87 seconds
Started Feb 18 01:16:27 PM PST 24
Finished Feb 18 01:20:28 PM PST 24
Peak memory 201464 kb
Host smart-490913cb-3729-44d9-96ad-cf782effa80d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535256220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2535256220
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1541332218
Short name T512
Test name
Test status
Simulation time 127679905990 ps
CPU time 586.96 seconds
Started Feb 18 01:16:35 PM PST 24
Finished Feb 18 01:26:25 PM PST 24
Peak memory 201804 kb
Host smart-275f0ef7-b2f9-4e2c-a878-f2ba62e6b130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541332218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1541332218
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2095507424
Short name T383
Test name
Test status
Simulation time 33757117768 ps
CPU time 74.43 seconds
Started Feb 18 01:16:35 PM PST 24
Finished Feb 18 01:17:52 PM PST 24
Peak memory 201228 kb
Host smart-ebe90e4e-c551-4698-b2c6-d9643f91527d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095507424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2095507424
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2789373765
Short name T577
Test name
Test status
Simulation time 3710984238 ps
CPU time 2.72 seconds
Started Feb 18 01:16:36 PM PST 24
Finished Feb 18 01:16:41 PM PST 24
Peak memory 201232 kb
Host smart-8b7f18c1-1c6c-409d-bf60-0d170329c757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789373765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2789373765
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1606275567
Short name T405
Test name
Test status
Simulation time 5777683650 ps
CPU time 7.53 seconds
Started Feb 18 01:16:29 PM PST 24
Finished Feb 18 01:16:37 PM PST 24
Peak memory 201232 kb
Host smart-de178c25-51b2-4dd4-95c0-2ad6df1f2f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606275567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1606275567
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.281363772
Short name T770
Test name
Test status
Simulation time 280856019809 ps
CPU time 480.25 seconds
Started Feb 18 01:16:36 PM PST 24
Finished Feb 18 01:24:38 PM PST 24
Peak memory 212468 kb
Host smart-67a160e9-e92c-4864-a59e-81a9e43dacde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281363772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
281363772
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3080206970
Short name T423
Test name
Test status
Simulation time 448748719 ps
CPU time 1.18 seconds
Started Feb 18 01:16:44 PM PST 24
Finished Feb 18 01:16:45 PM PST 24
Peak memory 201136 kb
Host smart-185c0bb2-de3e-483f-955c-a97f17509df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080206970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3080206970
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2267080986
Short name T343
Test name
Test status
Simulation time 496055292032 ps
CPU time 1016.73 seconds
Started Feb 18 01:16:43 PM PST 24
Finished Feb 18 01:33:40 PM PST 24
Peak memory 201492 kb
Host smart-a6c3ff57-3716-4dfc-95c5-9a5da5cefc81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267080986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2267080986
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.195695797
Short name T753
Test name
Test status
Simulation time 162686046659 ps
CPU time 105.45 seconds
Started Feb 18 01:16:43 PM PST 24
Finished Feb 18 01:18:29 PM PST 24
Peak memory 201456 kb
Host smart-e71f2c83-065d-4776-8789-97b3b09331a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195695797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.195695797
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1198695009
Short name T654
Test name
Test status
Simulation time 489389949108 ps
CPU time 195.11 seconds
Started Feb 18 01:16:41 PM PST 24
Finished Feb 18 01:19:57 PM PST 24
Peak memory 201448 kb
Host smart-257092c1-54f9-4294-b2de-111a23b47e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198695009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1198695009
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2306756154
Short name T541
Test name
Test status
Simulation time 324296751899 ps
CPU time 392.81 seconds
Started Feb 18 01:16:42 PM PST 24
Finished Feb 18 01:23:15 PM PST 24
Peak memory 201416 kb
Host smart-3b5641c5-3e98-4d67-a6bb-5ead61a0502a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306756154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2306756154
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1419259765
Short name T575
Test name
Test status
Simulation time 166716577409 ps
CPU time 371.71 seconds
Started Feb 18 01:16:35 PM PST 24
Finished Feb 18 01:22:49 PM PST 24
Peak memory 201504 kb
Host smart-0bf2bd6d-aebe-4209-b628-a9ad6774fdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419259765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1419259765
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3835871803
Short name T656
Test name
Test status
Simulation time 166124296639 ps
CPU time 355.31 seconds
Started Feb 18 01:16:42 PM PST 24
Finished Feb 18 01:22:38 PM PST 24
Peak memory 201408 kb
Host smart-aabc5639-7a17-4219-9aae-eb0c939fe51e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835871803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3835871803
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1866817461
Short name T250
Test name
Test status
Simulation time 491012745244 ps
CPU time 646.39 seconds
Started Feb 18 01:16:44 PM PST 24
Finished Feb 18 01:27:31 PM PST 24
Peak memory 201388 kb
Host smart-0e12b610-5e82-4bc2-88c8-a2d8686027f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866817461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1866817461
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3156736147
Short name T780
Test name
Test status
Simulation time 161558745525 ps
CPU time 95.35 seconds
Started Feb 18 01:16:44 PM PST 24
Finished Feb 18 01:18:20 PM PST 24
Peak memory 201472 kb
Host smart-b2f8c757-bdf8-43e3-a454-184a7eb73d82
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156736147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3156736147
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.374545280
Short name T448
Test name
Test status
Simulation time 97721951875 ps
CPU time 468.95 seconds
Started Feb 18 01:16:41 PM PST 24
Finished Feb 18 01:24:31 PM PST 24
Peak memory 201796 kb
Host smart-e3c07b6f-8dc5-4231-bb66-a7977b022df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374545280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.374545280
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.167803028
Short name T404
Test name
Test status
Simulation time 36481264429 ps
CPU time 44.78 seconds
Started Feb 18 01:16:42 PM PST 24
Finished Feb 18 01:17:28 PM PST 24
Peak memory 201172 kb
Host smart-4a9dc754-1979-42c9-bbe3-8a594781265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167803028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.167803028
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.4107493820
Short name T585
Test name
Test status
Simulation time 3921935177 ps
CPU time 2.7 seconds
Started Feb 18 01:16:42 PM PST 24
Finished Feb 18 01:16:46 PM PST 24
Peak memory 201064 kb
Host smart-b9a9ce1d-8e73-4567-a5c7-5182df568515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107493820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4107493820
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1753705278
Short name T583
Test name
Test status
Simulation time 5770122031 ps
CPU time 13.12 seconds
Started Feb 18 01:16:35 PM PST 24
Finished Feb 18 01:16:51 PM PST 24
Peak memory 201184 kb
Host smart-8aa338ac-cf9e-425b-b0d3-b347dd5e5503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753705278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1753705278
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3378624408
Short name T578
Test name
Test status
Simulation time 192270779789 ps
CPU time 115.03 seconds
Started Feb 18 01:16:42 PM PST 24
Finished Feb 18 01:18:38 PM PST 24
Peak memory 201440 kb
Host smart-ac730598-95c2-4d60-9b28-7d20a7ee6407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378624408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3378624408
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3480218134
Short name T683
Test name
Test status
Simulation time 177292748956 ps
CPU time 89.16 seconds
Started Feb 18 01:16:42 PM PST 24
Finished Feb 18 01:18:11 PM PST 24
Peak memory 211336 kb
Host smart-48894e24-b752-4cf3-af82-ac7213d7bbc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480218134 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3480218134
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2900477698
Short name T418
Test name
Test status
Simulation time 386338304 ps
CPU time 1.49 seconds
Started Feb 18 01:15:06 PM PST 24
Finished Feb 18 01:15:09 PM PST 24
Peak memory 201160 kb
Host smart-2973eb5d-7413-430f-af71-a95e89f53bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900477698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2900477698
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.4199756689
Short name T167
Test name
Test status
Simulation time 331847143128 ps
CPU time 95.36 seconds
Started Feb 18 01:14:52 PM PST 24
Finished Feb 18 01:16:29 PM PST 24
Peak memory 201400 kb
Host smart-75b52d89-dfad-4dd2-aef5-5154e087dd1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199756689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.4199756689
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1293418623
Short name T705
Test name
Test status
Simulation time 326187396045 ps
CPU time 139.55 seconds
Started Feb 18 01:14:58 PM PST 24
Finished Feb 18 01:17:18 PM PST 24
Peak memory 201524 kb
Host smart-e8957222-717d-4bbb-bbc6-12c36263c8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293418623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1293418623
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1552018300
Short name T319
Test name
Test status
Simulation time 164938356454 ps
CPU time 37.7 seconds
Started Feb 18 01:14:56 PM PST 24
Finished Feb 18 01:15:34 PM PST 24
Peak memory 201440 kb
Host smart-87b0084b-363e-442d-8968-c0b59508e59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552018300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1552018300
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3766224306
Short name T476
Test name
Test status
Simulation time 164311815480 ps
CPU time 128.26 seconds
Started Feb 18 01:14:58 PM PST 24
Finished Feb 18 01:17:09 PM PST 24
Peak memory 201404 kb
Host smart-576afba0-4df5-4bb4-965c-2c5963d060fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766224306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3766224306
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.365261288
Short name T158
Test name
Test status
Simulation time 483993051501 ps
CPU time 273.1 seconds
Started Feb 18 01:14:49 PM PST 24
Finished Feb 18 01:19:24 PM PST 24
Peak memory 201412 kb
Host smart-3ae051e6-20bc-4ea4-a3a8-d30b9ab7d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365261288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.365261288
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.514285681
Short name T142
Test name
Test status
Simulation time 499475650912 ps
CPU time 1154.39 seconds
Started Feb 18 01:14:54 PM PST 24
Finished Feb 18 01:34:10 PM PST 24
Peak memory 201472 kb
Host smart-ccbc42f6-b416-438b-af99-3d67301842ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=514285681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.514285681
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4072083080
Short name T623
Test name
Test status
Simulation time 164791516170 ps
CPU time 185.62 seconds
Started Feb 18 01:14:52 PM PST 24
Finished Feb 18 01:18:00 PM PST 24
Peak memory 201360 kb
Host smart-dd7b6cbe-12e6-44d3-b073-213c7d7bedec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072083080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4072083080
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3829246538
Short name T419
Test name
Test status
Simulation time 160454834887 ps
CPU time 192.33 seconds
Started Feb 18 01:14:57 PM PST 24
Finished Feb 18 01:18:11 PM PST 24
Peak memory 201432 kb
Host smart-4850eac4-189c-48ad-bbcc-c60eb7aef6b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829246538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3829246538
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3512431822
Short name T487
Test name
Test status
Simulation time 95806191778 ps
CPU time 424.87 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:22:14 PM PST 24
Peak memory 201796 kb
Host smart-f8ef24c9-fee6-47b2-b146-8de67dcc3455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512431822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3512431822
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2160058826
Short name T637
Test name
Test status
Simulation time 39670186343 ps
CPU time 17.01 seconds
Started Feb 18 01:14:49 PM PST 24
Finished Feb 18 01:15:07 PM PST 24
Peak memory 201216 kb
Host smart-59bf84c1-9f76-4089-bc4e-6c3da7ee746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160058826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2160058826
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2020736103
Short name T680
Test name
Test status
Simulation time 4221900810 ps
CPU time 5.9 seconds
Started Feb 18 01:14:53 PM PST 24
Finished Feb 18 01:15:00 PM PST 24
Peak memory 201100 kb
Host smart-15c91e73-0125-4746-bd43-d4cea8bcdcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020736103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2020736103
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2962970738
Short name T515
Test name
Test status
Simulation time 5884085874 ps
CPU time 2.06 seconds
Started Feb 18 01:14:53 PM PST 24
Finished Feb 18 01:14:56 PM PST 24
Peak memory 201224 kb
Host smart-68dfd3c2-7a29-49bf-a7a1-5b1aba64bbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962970738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2962970738
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1091321502
Short name T344
Test name
Test status
Simulation time 200929196778 ps
CPU time 36.3 seconds
Started Feb 18 01:14:58 PM PST 24
Finished Feb 18 01:15:35 PM PST 24
Peak memory 201504 kb
Host smart-5924c844-6366-439a-b4ed-4f6f94b47641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091321502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1091321502
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.821033526
Short name T62
Test name
Test status
Simulation time 138748154871 ps
CPU time 248.43 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:19:17 PM PST 24
Peak memory 217472 kb
Host smart-ace9833c-fdab-480c-987e-2d1e31d803f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821033526 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.821033526
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1980807668
Short name T645
Test name
Test status
Simulation time 352949541 ps
CPU time 1.47 seconds
Started Feb 18 01:17:22 PM PST 24
Finished Feb 18 01:17:24 PM PST 24
Peak memory 201136 kb
Host smart-3591756b-6429-4a27-84f6-c7fb78ccc9c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980807668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1980807668
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3568241946
Short name T533
Test name
Test status
Simulation time 163515250099 ps
CPU time 233.97 seconds
Started Feb 18 01:17:08 PM PST 24
Finished Feb 18 01:21:02 PM PST 24
Peak memory 201416 kb
Host smart-867cf6bd-af8e-4a27-bc9d-5839e74223f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568241946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3568241946
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1457129305
Short name T672
Test name
Test status
Simulation time 331552533733 ps
CPU time 746.49 seconds
Started Feb 18 01:16:54 PM PST 24
Finished Feb 18 01:29:21 PM PST 24
Peak memory 201364 kb
Host smart-c7a07449-aba2-4fde-8aa9-d5a66180eaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457129305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1457129305
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3203757271
Short name T525
Test name
Test status
Simulation time 166763983721 ps
CPU time 209.62 seconds
Started Feb 18 01:16:50 PM PST 24
Finished Feb 18 01:20:21 PM PST 24
Peak memory 201476 kb
Host smart-3e834e6c-fdcd-455e-b6b4-020eec022c4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203757271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3203757271
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1820449949
Short name T772
Test name
Test status
Simulation time 161154551780 ps
CPU time 299.98 seconds
Started Feb 18 01:16:50 PM PST 24
Finished Feb 18 01:21:51 PM PST 24
Peak memory 201464 kb
Host smart-ba49b48b-3deb-48c8-a46d-816552cad5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820449949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1820449949
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1332263618
Short name T505
Test name
Test status
Simulation time 326696880898 ps
CPU time 749.57 seconds
Started Feb 18 01:16:51 PM PST 24
Finished Feb 18 01:29:21 PM PST 24
Peak memory 201460 kb
Host smart-6cf917c8-13cc-421a-8362-cc3b14b7cd5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332263618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1332263618
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.4049177391
Short name T21
Test name
Test status
Simulation time 330798090317 ps
CPU time 745.86 seconds
Started Feb 18 01:16:54 PM PST 24
Finished Feb 18 01:29:20 PM PST 24
Peak memory 201432 kb
Host smart-e3e78269-a53e-411a-b76d-07fcc15b3f6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049177391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.4049177391
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2552255880
Short name T721
Test name
Test status
Simulation time 496593617583 ps
CPU time 1110.21 seconds
Started Feb 18 01:16:50 PM PST 24
Finished Feb 18 01:35:21 PM PST 24
Peak memory 201528 kb
Host smart-751d93fa-b0e6-4c29-a49b-d8be33cecae8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552255880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2552255880
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2752040807
Short name T729
Test name
Test status
Simulation time 75808594205 ps
CPU time 274.06 seconds
Started Feb 18 01:17:10 PM PST 24
Finished Feb 18 01:21:44 PM PST 24
Peak memory 201620 kb
Host smart-5d1b63a8-24b5-4b4a-a018-321035d63646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752040807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2752040807
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.4175753365
Short name T641
Test name
Test status
Simulation time 44853149645 ps
CPU time 27.29 seconds
Started Feb 18 01:17:04 PM PST 24
Finished Feb 18 01:17:32 PM PST 24
Peak memory 201232 kb
Host smart-b80b7262-67e3-4dfc-b012-a4e6465a8887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175753365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.4175753365
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1486771778
Short name T421
Test name
Test status
Simulation time 4053957565 ps
CPU time 11.56 seconds
Started Feb 18 01:17:05 PM PST 24
Finished Feb 18 01:17:17 PM PST 24
Peak memory 201228 kb
Host smart-db11c477-82e9-49f2-bec8-bccbc7e6ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486771778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1486771778
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1718784350
Short name T563
Test name
Test status
Simulation time 5902405587 ps
CPU time 8.11 seconds
Started Feb 18 01:16:51 PM PST 24
Finished Feb 18 01:17:00 PM PST 24
Peak memory 201240 kb
Host smart-207874f8-c12e-44fa-830e-ea7eabd04eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718784350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1718784350
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2651265675
Short name T341
Test name
Test status
Simulation time 365872100564 ps
CPU time 218.44 seconds
Started Feb 18 01:17:18 PM PST 24
Finished Feb 18 01:20:57 PM PST 24
Peak memory 201524 kb
Host smart-445ad006-f66e-462d-85ce-3a79dde65413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651265675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2651265675
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1220193469
Short name T186
Test name
Test status
Simulation time 55725348744 ps
CPU time 262.97 seconds
Started Feb 18 01:17:05 PM PST 24
Finished Feb 18 01:21:28 PM PST 24
Peak memory 210128 kb
Host smart-952b0de3-e704-4fce-9471-f37d44fa7d9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220193469 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1220193469
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.626843251
Short name T45
Test name
Test status
Simulation time 359386489 ps
CPU time 0.81 seconds
Started Feb 18 01:17:15 PM PST 24
Finished Feb 18 01:17:16 PM PST 24
Peak memory 201172 kb
Host smart-493f478f-b586-4fcc-a06a-bc749c6fbaec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626843251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.626843251
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2011102125
Short name T669
Test name
Test status
Simulation time 329673866215 ps
CPU time 187.2 seconds
Started Feb 18 01:17:24 PM PST 24
Finished Feb 18 01:20:31 PM PST 24
Peak memory 201492 kb
Host smart-242a0970-eec3-41a5-8b25-ed93cf3d4c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011102125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2011102125
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.634450626
Short name T183
Test name
Test status
Simulation time 333365617579 ps
CPU time 173.28 seconds
Started Feb 18 01:17:07 PM PST 24
Finished Feb 18 01:20:00 PM PST 24
Peak memory 201436 kb
Host smart-c7ea9d2e-5ff9-454d-87a1-da1261cc1fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634450626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.634450626
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2040862157
Short name T402
Test name
Test status
Simulation time 493498827996 ps
CPU time 579.71 seconds
Started Feb 18 01:17:22 PM PST 24
Finished Feb 18 01:27:02 PM PST 24
Peak memory 201480 kb
Host smart-a63dd536-90ce-4aa8-84c4-6cd9ea67b3cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040862157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2040862157
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1781932370
Short name T643
Test name
Test status
Simulation time 160249962519 ps
CPU time 369.36 seconds
Started Feb 18 01:17:10 PM PST 24
Finished Feb 18 01:23:19 PM PST 24
Peak memory 201484 kb
Host smart-deb525ea-6531-4f24-b53e-d5e1f7dba7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781932370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1781932370
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.897724406
Short name T685
Test name
Test status
Simulation time 330023437004 ps
CPU time 370.67 seconds
Started Feb 18 01:17:07 PM PST 24
Finished Feb 18 01:23:18 PM PST 24
Peak memory 201496 kb
Host smart-b45b94fe-3c2a-4e41-a1e3-0b2736248cf6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=897724406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.897724406
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2654835139
Short name T569
Test name
Test status
Simulation time 163912900313 ps
CPU time 362.89 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:23:27 PM PST 24
Peak memory 201456 kb
Host smart-0145f01b-5086-4388-a8a2-d461335e7a4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654835139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2654835139
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4149600318
Short name T208
Test name
Test status
Simulation time 82406826498 ps
CPU time 355.49 seconds
Started Feb 18 01:17:17 PM PST 24
Finished Feb 18 01:23:13 PM PST 24
Peak memory 201800 kb
Host smart-c23d7c77-5f30-4e80-b6cb-acd8ac843f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149600318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4149600318
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2211181533
Short name T675
Test name
Test status
Simulation time 24782869555 ps
CPU time 5.71 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:17:29 PM PST 24
Peak memory 201164 kb
Host smart-21ed2cfe-0c7d-4d92-af30-32972a3c1cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211181533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2211181533
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2059170760
Short name T463
Test name
Test status
Simulation time 4525250009 ps
CPU time 9.41 seconds
Started Feb 18 01:17:22 PM PST 24
Finished Feb 18 01:17:32 PM PST 24
Peak memory 201224 kb
Host smart-7cbd27df-32ba-47f2-947f-40f7fe6b67e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059170760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2059170760
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.4226328510
Short name T443
Test name
Test status
Simulation time 6041597202 ps
CPU time 10.78 seconds
Started Feb 18 01:17:18 PM PST 24
Finished Feb 18 01:17:29 PM PST 24
Peak memory 201184 kb
Host smart-adf099ae-adfd-415f-81a4-863ca2f992d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226328510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.4226328510
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3676075557
Short name T205
Test name
Test status
Simulation time 166744005378 ps
CPU time 357.42 seconds
Started Feb 18 01:17:16 PM PST 24
Finished Feb 18 01:23:14 PM PST 24
Peak memory 201396 kb
Host smart-83d8d08c-265e-4723-b863-5ac8add79ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676075557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3676075557
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3537794176
Short name T455
Test name
Test status
Simulation time 347793329 ps
CPU time 1.45 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:17:25 PM PST 24
Peak memory 201000 kb
Host smart-b303144f-cd67-4742-907b-1131897b61ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537794176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3537794176
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3283738313
Short name T143
Test name
Test status
Simulation time 329829686607 ps
CPU time 732.79 seconds
Started Feb 18 01:17:20 PM PST 24
Finished Feb 18 01:29:34 PM PST 24
Peak memory 201476 kb
Host smart-b8733d2f-264d-4444-9cc3-c73030d57d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283738313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3283738313
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.992431429
Short name T782
Test name
Test status
Simulation time 158016873963 ps
CPU time 135.88 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:19:40 PM PST 24
Peak memory 201452 kb
Host smart-06f9237c-8887-4e38-867f-0532f3ef37fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992431429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.992431429
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2221400342
Short name T752
Test name
Test status
Simulation time 490442335040 ps
CPU time 1152.85 seconds
Started Feb 18 01:17:21 PM PST 24
Finished Feb 18 01:36:35 PM PST 24
Peak memory 201416 kb
Host smart-bbc79abd-66cd-419a-ba44-e2dbab726e02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221400342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2221400342
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1007211667
Short name T473
Test name
Test status
Simulation time 488903507126 ps
CPU time 308.97 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:22:33 PM PST 24
Peak memory 201464 kb
Host smart-35c80178-2864-43d3-a715-2d53189c6f2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007211667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1007211667
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1199691330
Short name T316
Test name
Test status
Simulation time 331168416574 ps
CPU time 192.17 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:20:36 PM PST 24
Peak memory 201476 kb
Host smart-8ca03fa0-2e89-4b51-9998-5176ae18e2b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199691330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1199691330
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1047440609
Short name T96
Test name
Test status
Simulation time 488666499082 ps
CPU time 537.6 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:26:21 PM PST 24
Peak memory 201472 kb
Host smart-13a60d4d-721e-47f5-afb7-8984894c451e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047440609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1047440609
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2855814099
Short name T546
Test name
Test status
Simulation time 78564041460 ps
CPU time 279.98 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:22:03 PM PST 24
Peak memory 201672 kb
Host smart-8f771a94-da9a-4d8c-aa9e-85c993bfe8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855814099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2855814099
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3511322650
Short name T540
Test name
Test status
Simulation time 30005665712 ps
CPU time 73.48 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:18:37 PM PST 24
Peak memory 201236 kb
Host smart-51829da5-1376-4bbe-a8e0-4b9e16ced155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511322650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3511322650
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3023912684
Short name T76
Test name
Test status
Simulation time 3111145656 ps
CPU time 8.26 seconds
Started Feb 18 01:17:26 PM PST 24
Finished Feb 18 01:17:35 PM PST 24
Peak memory 201236 kb
Host smart-add30c9c-1673-47bb-ab1c-b659a2549b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023912684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3023912684
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2962504734
Short name T568
Test name
Test status
Simulation time 5642403190 ps
CPU time 12.23 seconds
Started Feb 18 01:17:23 PM PST 24
Finished Feb 18 01:17:36 PM PST 24
Peak memory 201176 kb
Host smart-f42a4477-986e-431b-a9bb-57d04b31342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962504734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2962504734
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2007576455
Short name T221
Test name
Test status
Simulation time 274081858124 ps
CPU time 825.59 seconds
Started Feb 18 01:17:22 PM PST 24
Finished Feb 18 01:31:08 PM PST 24
Peak memory 211896 kb
Host smart-8d691f60-8be2-43a0-ade1-839c94824486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007576455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2007576455
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1756184543
Short name T489
Test name
Test status
Simulation time 177250807429 ps
CPU time 194.98 seconds
Started Feb 18 01:17:22 PM PST 24
Finished Feb 18 01:20:38 PM PST 24
Peak memory 201384 kb
Host smart-e076ad77-2839-470a-b07f-0beec5b98ed1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756184543 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1756184543
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.242748942
Short name T536
Test name
Test status
Simulation time 513410315 ps
CPU time 1.69 seconds
Started Feb 18 01:17:35 PM PST 24
Finished Feb 18 01:17:38 PM PST 24
Peak memory 201176 kb
Host smart-e1e3531f-45a7-4687-a2aa-7b694abf2c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242748942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.242748942
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.134397385
Short name T282
Test name
Test status
Simulation time 325169082930 ps
CPU time 288.62 seconds
Started Feb 18 01:17:34 PM PST 24
Finished Feb 18 01:22:24 PM PST 24
Peak memory 201424 kb
Host smart-bcfa56ce-4350-43fe-b72c-36f77544c018
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134397385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.134397385
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3990062296
Short name T303
Test name
Test status
Simulation time 161040239486 ps
CPU time 93.32 seconds
Started Feb 18 01:17:36 PM PST 24
Finished Feb 18 01:19:10 PM PST 24
Peak memory 201476 kb
Host smart-a3dd27f9-b2d1-420b-8fa7-7d6c80439368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990062296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3990062296
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3662487161
Short name T161
Test name
Test status
Simulation time 494874062926 ps
CPU time 180.59 seconds
Started Feb 18 01:17:33 PM PST 24
Finished Feb 18 01:20:36 PM PST 24
Peak memory 201472 kb
Host smart-6dd77c35-065e-4d27-ae3b-5d3fa12f4675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662487161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3662487161
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3841181262
Short name T130
Test name
Test status
Simulation time 491272707505 ps
CPU time 181.84 seconds
Started Feb 18 01:17:36 PM PST 24
Finished Feb 18 01:20:39 PM PST 24
Peak memory 201444 kb
Host smart-c66c2e43-ef77-43dc-95b5-106966af04b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841181262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3841181262
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2971135339
Short name T191
Test name
Test status
Simulation time 325844949413 ps
CPU time 305.44 seconds
Started Feb 18 01:17:32 PM PST 24
Finished Feb 18 01:22:40 PM PST 24
Peak memory 201472 kb
Host smart-8cb89a06-db57-44e5-abbd-f7d05b22b7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971135339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2971135339
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.274467847
Short name T157
Test name
Test status
Simulation time 325000559762 ps
CPU time 195.09 seconds
Started Feb 18 01:17:33 PM PST 24
Finished Feb 18 01:20:50 PM PST 24
Peak memory 201420 kb
Host smart-0bf5360f-6888-4ad4-9c7d-1d17cd3fecc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=274467847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.274467847
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.509906738
Short name T244
Test name
Test status
Simulation time 337232929898 ps
CPU time 806.96 seconds
Started Feb 18 01:17:36 PM PST 24
Finished Feb 18 01:31:04 PM PST 24
Peak memory 201500 kb
Host smart-479921e6-2f2b-4cbf-addd-e7710f7a0e98
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509906738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.509906738
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2472587092
Short name T364
Test name
Test status
Simulation time 164635462782 ps
CPU time 363.16 seconds
Started Feb 18 01:17:32 PM PST 24
Finished Feb 18 01:23:36 PM PST 24
Peak memory 201436 kb
Host smart-ed6bd415-170e-4c3a-81d4-08bac1cfff18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472587092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2472587092
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.914389616
Short name T78
Test name
Test status
Simulation time 37870729266 ps
CPU time 86.28 seconds
Started Feb 18 01:17:31 PM PST 24
Finished Feb 18 01:18:59 PM PST 24
Peak memory 201224 kb
Host smart-861a5635-37aa-41a3-bca9-682e8c3fc972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914389616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.914389616
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3715818749
Short name T498
Test name
Test status
Simulation time 4516372458 ps
CPU time 12.11 seconds
Started Feb 18 01:17:32 PM PST 24
Finished Feb 18 01:17:45 PM PST 24
Peak memory 201236 kb
Host smart-8415dfe9-a73e-498b-adeb-b6708cdd96df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715818749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3715818749
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.73721301
Short name T700
Test name
Test status
Simulation time 5607440198 ps
CPU time 4.01 seconds
Started Feb 18 01:17:33 PM PST 24
Finished Feb 18 01:17:38 PM PST 24
Peak memory 201132 kb
Host smart-2409c77b-930c-4c74-ba35-d482aa2fbbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73721301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.73721301
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3662223595
Short name T302
Test name
Test status
Simulation time 407999339151 ps
CPU time 950.39 seconds
Started Feb 18 01:17:42 PM PST 24
Finished Feb 18 01:33:34 PM PST 24
Peak memory 201420 kb
Host smart-d9ef2e14-fa98-41a6-b3f5-37ee7c0e08a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662223595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3662223595
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1710055946
Short name T759
Test name
Test status
Simulation time 267500367990 ps
CPU time 479.57 seconds
Started Feb 18 01:17:42 PM PST 24
Finished Feb 18 01:25:42 PM PST 24
Peak memory 210108 kb
Host smart-045baacf-9140-4001-8238-3d65fc47fc53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710055946 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1710055946
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3372496712
Short name T468
Test name
Test status
Simulation time 480162445 ps
CPU time 1.66 seconds
Started Feb 18 01:17:56 PM PST 24
Finished Feb 18 01:17:59 PM PST 24
Peak memory 201160 kb
Host smart-6584ce9f-d44a-4bc3-b9a3-d073dfd2f25e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372496712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3372496712
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.333464481
Short name T170
Test name
Test status
Simulation time 327432881154 ps
CPU time 171.65 seconds
Started Feb 18 01:17:39 PM PST 24
Finished Feb 18 01:20:32 PM PST 24
Peak memory 201412 kb
Host smart-251ef04f-98b0-4d9d-84d1-0d7b6d004b30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333464481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.333464481
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3673560633
Short name T622
Test name
Test status
Simulation time 174272434485 ps
CPU time 49.97 seconds
Started Feb 18 01:17:53 PM PST 24
Finished Feb 18 01:18:43 PM PST 24
Peak memory 201460 kb
Host smart-4c3b69ed-74e7-4a3c-a207-355965dfee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673560633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3673560633
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1998281474
Short name T681
Test name
Test status
Simulation time 166739150813 ps
CPU time 194.89 seconds
Started Feb 18 01:17:36 PM PST 24
Finished Feb 18 01:20:52 PM PST 24
Peak memory 201428 kb
Host smart-bd244a8e-30c8-4f3e-8eb6-a4f335789faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998281474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1998281474
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.627781794
Short name T736
Test name
Test status
Simulation time 166630617679 ps
CPU time 34.46 seconds
Started Feb 18 01:17:37 PM PST 24
Finished Feb 18 01:18:12 PM PST 24
Peak memory 201392 kb
Host smart-fbe7afe5-2b23-4b60-88d7-483dd880ed1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=627781794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.627781794
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.998464351
Short name T710
Test name
Test status
Simulation time 484313300982 ps
CPU time 1098.59 seconds
Started Feb 18 01:17:35 PM PST 24
Finished Feb 18 01:35:55 PM PST 24
Peak memory 201560 kb
Host smart-40b6af6c-12a0-4ff5-8d3f-b0384947a35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998464351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.998464351
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3874805100
Short name T786
Test name
Test status
Simulation time 332483325912 ps
CPU time 193.34 seconds
Started Feb 18 01:17:41 PM PST 24
Finished Feb 18 01:20:55 PM PST 24
Peak memory 201432 kb
Host smart-68f8d60d-754c-424f-98bd-6afa50735cd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874805100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3874805100
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.703471238
Short name T607
Test name
Test status
Simulation time 547114639425 ps
CPU time 301.63 seconds
Started Feb 18 01:17:41 PM PST 24
Finished Feb 18 01:22:44 PM PST 24
Peak memory 201416 kb
Host smart-e7af72ac-1126-43a9-a964-164902a7b1bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703471238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.703471238
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.610531922
Short name T722
Test name
Test status
Simulation time 328919818910 ps
CPU time 665.99 seconds
Started Feb 18 01:17:37 PM PST 24
Finished Feb 18 01:28:43 PM PST 24
Peak memory 201412 kb
Host smart-34cd099b-ea4f-47a1-9d2e-7a8718e4ab25
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610531922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.610531922
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1722357449
Short name T5
Test name
Test status
Simulation time 123913365050 ps
CPU time 654.22 seconds
Started Feb 18 01:17:43 PM PST 24
Finished Feb 18 01:28:40 PM PST 24
Peak memory 201776 kb
Host smart-ff026795-467e-448f-ae42-b3cb45f5529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722357449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1722357449
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2671935075
Short name T621
Test name
Test status
Simulation time 39159824256 ps
CPU time 88.64 seconds
Started Feb 18 01:17:54 PM PST 24
Finished Feb 18 01:19:23 PM PST 24
Peak memory 201244 kb
Host smart-de1cb85c-47eb-43a1-81af-42ae84bc9fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671935075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2671935075
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2567843813
Short name T122
Test name
Test status
Simulation time 5193136638 ps
CPU time 12.05 seconds
Started Feb 18 01:17:55 PM PST 24
Finished Feb 18 01:18:08 PM PST 24
Peak memory 201216 kb
Host smart-b8136d1f-1a04-4c18-aad0-68cd290e175b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567843813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2567843813
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2171354173
Short name T408
Test name
Test status
Simulation time 5808534424 ps
CPU time 12.81 seconds
Started Feb 18 01:17:46 PM PST 24
Finished Feb 18 01:17:59 PM PST 24
Peak memory 201232 kb
Host smart-0de0386d-5689-437d-a601-66f12fabacd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171354173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2171354173
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2689447310
Short name T249
Test name
Test status
Simulation time 420751110261 ps
CPU time 229.92 seconds
Started Feb 18 01:17:47 PM PST 24
Finished Feb 18 01:21:38 PM PST 24
Peak memory 218256 kb
Host smart-fb2970d7-f5c3-49d3-aea3-149aa6e8ba59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689447310 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2689447310
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2646528404
Short name T704
Test name
Test status
Simulation time 379342534 ps
CPU time 0.79 seconds
Started Feb 18 01:18:05 PM PST 24
Finished Feb 18 01:18:06 PM PST 24
Peak memory 200980 kb
Host smart-664ec603-d55e-4a7d-b2c9-ed7b2174079b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646528404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2646528404
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.518871077
Short name T258
Test name
Test status
Simulation time 321995931126 ps
CPU time 642.59 seconds
Started Feb 18 01:17:58 PM PST 24
Finished Feb 18 01:28:42 PM PST 24
Peak memory 201428 kb
Host smart-a419ed8a-1df2-49be-82b7-6a093a42571f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518871077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.518871077
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3923497763
Short name T242
Test name
Test status
Simulation time 326740685353 ps
CPU time 392.91 seconds
Started Feb 18 01:17:59 PM PST 24
Finished Feb 18 01:24:34 PM PST 24
Peak memory 201396 kb
Host smart-8a3c1023-1b4e-4b64-8f7a-14071005c232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923497763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3923497763
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2740119268
Short name T162
Test name
Test status
Simulation time 488198170718 ps
CPU time 1061 seconds
Started Feb 18 01:17:58 PM PST 24
Finished Feb 18 01:35:42 PM PST 24
Peak memory 201384 kb
Host smart-c4a174bb-fcc0-4e0c-8872-d248b0b69862
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740119268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2740119268
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3505885072
Short name T156
Test name
Test status
Simulation time 163562562546 ps
CPU time 46.28 seconds
Started Feb 18 01:17:55 PM PST 24
Finished Feb 18 01:18:43 PM PST 24
Peak memory 201464 kb
Host smart-a5d60347-e865-41ae-87be-ca991626d3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505885072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3505885072
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2545011510
Short name T639
Test name
Test status
Simulation time 323546722739 ps
CPU time 766.87 seconds
Started Feb 18 01:17:57 PM PST 24
Finished Feb 18 01:30:45 PM PST 24
Peak memory 201448 kb
Host smart-790eeec3-03fd-4045-843f-2973d88673de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545011510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2545011510
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3525017216
Short name T56
Test name
Test status
Simulation time 492028986388 ps
CPU time 1239.3 seconds
Started Feb 18 01:18:00 PM PST 24
Finished Feb 18 01:38:41 PM PST 24
Peak memory 201492 kb
Host smart-72ddd797-4966-43c4-90f7-4cf203a150dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525017216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3525017216
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3037084284
Short name T218
Test name
Test status
Simulation time 116361305234 ps
CPU time 507.46 seconds
Started Feb 18 01:18:12 PM PST 24
Finished Feb 18 01:26:41 PM PST 24
Peak memory 201736 kb
Host smart-a83ca804-ba5a-4035-b4e0-5968cefb4493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037084284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3037084284
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.34386603
Short name T652
Test name
Test status
Simulation time 39844727603 ps
CPU time 95.47 seconds
Started Feb 18 01:17:59 PM PST 24
Finished Feb 18 01:19:36 PM PST 24
Peak memory 201176 kb
Host smart-f428aec9-ca0e-4a6f-95e1-b2a6c06fa179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34386603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.34386603
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3304613237
Short name T472
Test name
Test status
Simulation time 4912546711 ps
CPU time 4.28 seconds
Started Feb 18 01:17:57 PM PST 24
Finished Feb 18 01:18:04 PM PST 24
Peak memory 201204 kb
Host smart-583f590f-7279-4c18-881d-72b4356bef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304613237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3304613237
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.145854409
Short name T529
Test name
Test status
Simulation time 6054435850 ps
CPU time 16.18 seconds
Started Feb 18 01:17:56 PM PST 24
Finished Feb 18 01:18:13 PM PST 24
Peak memory 201176 kb
Host smart-7ffef9c3-a3f2-4f04-9776-202ddc9de394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145854409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.145854409
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.477452605
Short name T318
Test name
Test status
Simulation time 369445989038 ps
CPU time 57.76 seconds
Started Feb 18 01:18:12 PM PST 24
Finished Feb 18 01:19:11 PM PST 24
Peak memory 201436 kb
Host smart-d2ef8cdb-8ec3-4730-95e5-be70f95a97b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477452605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
477452605
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1687088964
Short name T360
Test name
Test status
Simulation time 133896102016 ps
CPU time 524.39 seconds
Started Feb 18 01:18:07 PM PST 24
Finished Feb 18 01:26:52 PM PST 24
Peak memory 210044 kb
Host smart-0e0189ab-d5c4-4781-a856-424fc83ef673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687088964 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1687088964
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4027773489
Short name T509
Test name
Test status
Simulation time 376298453 ps
CPU time 1.4 seconds
Started Feb 18 01:18:16 PM PST 24
Finished Feb 18 01:18:19 PM PST 24
Peak memory 200976 kb
Host smart-8fb96853-3102-4737-99f2-ba11dc5b3e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027773489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4027773489
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.577935523
Short name T77
Test name
Test status
Simulation time 166787134787 ps
CPU time 143.45 seconds
Started Feb 18 01:18:14 PM PST 24
Finished Feb 18 01:20:39 PM PST 24
Peak memory 201480 kb
Host smart-dd4c9b59-910b-4a75-9ad7-1670913f3be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577935523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.577935523
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2471623211
Short name T742
Test name
Test status
Simulation time 493928061308 ps
CPU time 307.25 seconds
Started Feb 18 01:18:05 PM PST 24
Finished Feb 18 01:23:13 PM PST 24
Peak memory 201496 kb
Host smart-e9ff5474-431a-4e22-a11f-2c8648840a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471623211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2471623211
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3359907705
Short name T53
Test name
Test status
Simulation time 489287959191 ps
CPU time 344.77 seconds
Started Feb 18 01:18:12 PM PST 24
Finished Feb 18 01:23:57 PM PST 24
Peak memory 201424 kb
Host smart-949d65a8-0fb9-454c-9ff6-71021cf99c0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359907705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3359907705
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2198810916
Short name T83
Test name
Test status
Simulation time 169903394393 ps
CPU time 194.63 seconds
Started Feb 18 01:18:12 PM PST 24
Finished Feb 18 01:21:27 PM PST 24
Peak memory 201492 kb
Host smart-d76fda5a-a904-4080-b5a2-06897cf2518b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198810916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2198810916
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3531507617
Short name T590
Test name
Test status
Simulation time 166398024297 ps
CPU time 378.8 seconds
Started Feb 18 01:18:06 PM PST 24
Finished Feb 18 01:24:25 PM PST 24
Peak memory 201488 kb
Host smart-e7f19f9a-e565-4713-9ed6-1357164c723c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531507617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3531507617
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.4003384994
Short name T769
Test name
Test status
Simulation time 501823928304 ps
CPU time 63.66 seconds
Started Feb 18 01:18:12 PM PST 24
Finished Feb 18 01:19:17 PM PST 24
Peak memory 201484 kb
Host smart-cd3b8e33-ae2b-4de4-aaae-d6ed22fe5c5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003384994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.4003384994
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.584037577
Short name T741
Test name
Test status
Simulation time 162863035338 ps
CPU time 357.99 seconds
Started Feb 18 01:18:14 PM PST 24
Finished Feb 18 01:24:13 PM PST 24
Peak memory 201440 kb
Host smart-f42a6d86-a405-4cd2-8a32-ca66a61782bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584037577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.584037577
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3705429211
Short name T69
Test name
Test status
Simulation time 84731084770 ps
CPU time 443.6 seconds
Started Feb 18 01:18:14 PM PST 24
Finished Feb 18 01:25:39 PM PST 24
Peak memory 201800 kb
Host smart-03f3cf43-8b6c-4507-8e72-e1b5eb63311e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705429211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3705429211
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3953408198
Short name T558
Test name
Test status
Simulation time 35636370092 ps
CPU time 43.29 seconds
Started Feb 18 01:18:14 PM PST 24
Finished Feb 18 01:18:58 PM PST 24
Peak memory 201236 kb
Host smart-86645a00-0f73-4d45-aaee-8b30913d6c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953408198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3953408198
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.833070494
Short name T560
Test name
Test status
Simulation time 3789881541 ps
CPU time 4.88 seconds
Started Feb 18 01:18:14 PM PST 24
Finished Feb 18 01:18:20 PM PST 24
Peak memory 201236 kb
Host smart-b1139913-e4b6-4302-b1f6-5feb4b1afb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833070494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.833070494
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3556987974
Short name T444
Test name
Test status
Simulation time 6184741662 ps
CPU time 2.71 seconds
Started Feb 18 01:18:13 PM PST 24
Finished Feb 18 01:18:17 PM PST 24
Peak memory 201188 kb
Host smart-d796c76a-b3a1-4fd9-bae5-8c09bf2e36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556987974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3556987974
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2739959041
Short name T259
Test name
Test status
Simulation time 350596887443 ps
CPU time 1024.97 seconds
Started Feb 18 01:18:15 PM PST 24
Finished Feb 18 01:35:21 PM PST 24
Peak memory 201732 kb
Host smart-a8c930b9-6cd6-4ee4-a163-59e8d45c1a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739959041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2739959041
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2338220684
Short name T126
Test name
Test status
Simulation time 35252401197 ps
CPU time 78.99 seconds
Started Feb 18 01:18:14 PM PST 24
Finished Feb 18 01:19:34 PM PST 24
Peak memory 201616 kb
Host smart-294f830a-1a35-494f-9c25-fbda68b0b882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338220684 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2338220684
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1575860349
Short name T580
Test name
Test status
Simulation time 333338310 ps
CPU time 0.79 seconds
Started Feb 18 01:18:28 PM PST 24
Finished Feb 18 01:18:31 PM PST 24
Peak memory 201104 kb
Host smart-bcb57eed-5039-4a7a-9667-e91531d93402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575860349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1575860349
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3261618648
Short name T764
Test name
Test status
Simulation time 166840265979 ps
CPU time 75.83 seconds
Started Feb 18 01:18:20 PM PST 24
Finished Feb 18 01:19:36 PM PST 24
Peak memory 201452 kb
Host smart-8b2b2ee8-0e1c-4949-97ef-9c81a989480f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261618648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3261618648
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4068569809
Short name T181
Test name
Test status
Simulation time 505143469949 ps
CPU time 315.51 seconds
Started Feb 18 01:18:24 PM PST 24
Finished Feb 18 01:23:41 PM PST 24
Peak memory 201348 kb
Host smart-cb109f74-2d19-4c05-a6cd-1df42de23819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068569809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4068569809
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.4084118270
Short name T326
Test name
Test status
Simulation time 490167503978 ps
CPU time 263.26 seconds
Started Feb 18 01:18:16 PM PST 24
Finished Feb 18 01:22:41 PM PST 24
Peak memory 201272 kb
Host smart-5b799214-ded5-4aaa-8684-96b81c1ec92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084118270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.4084118270
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1802150592
Short name T406
Test name
Test status
Simulation time 490877814790 ps
CPU time 1149.96 seconds
Started Feb 18 01:18:24 PM PST 24
Finished Feb 18 01:37:35 PM PST 24
Peak memory 201424 kb
Host smart-4385303a-4e91-4841-b6f9-64b2d1802225
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802150592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1802150592
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4231403006
Short name T440
Test name
Test status
Simulation time 318371961512 ps
CPU time 609.21 seconds
Started Feb 18 01:18:13 PM PST 24
Finished Feb 18 01:28:23 PM PST 24
Peak memory 201444 kb
Host smart-8bf4396f-a602-44cb-bc98-32fcd5d23f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231403006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4231403006
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.346869132
Short name T605
Test name
Test status
Simulation time 162822709612 ps
CPU time 167.93 seconds
Started Feb 18 01:18:14 PM PST 24
Finished Feb 18 01:21:02 PM PST 24
Peak memory 201424 kb
Host smart-9be9039d-1089-441d-8b53-71efcc5c7d1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=346869132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.346869132
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3390559480
Short name T285
Test name
Test status
Simulation time 160195631128 ps
CPU time 58.82 seconds
Started Feb 18 01:18:22 PM PST 24
Finished Feb 18 01:19:21 PM PST 24
Peak memory 201476 kb
Host smart-2172b180-082c-41cc-afd9-9a998946e5f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390559480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3390559480
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.637437923
Short name T368
Test name
Test status
Simulation time 331891167709 ps
CPU time 369.95 seconds
Started Feb 18 01:18:20 PM PST 24
Finished Feb 18 01:24:30 PM PST 24
Peak memory 201484 kb
Host smart-565d646a-cfe2-4555-a331-5ebc85baed2b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637437923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.637437923
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2225445135
Short name T215
Test name
Test status
Simulation time 97825464217 ps
CPU time 375.1 seconds
Started Feb 18 01:18:29 PM PST 24
Finished Feb 18 01:24:46 PM PST 24
Peak memory 201772 kb
Host smart-182d9de5-6648-4e60-ac6e-02ac07bedd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225445135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2225445135
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1702713979
Short name T661
Test name
Test status
Simulation time 43600628904 ps
CPU time 15.28 seconds
Started Feb 18 01:18:31 PM PST 24
Finished Feb 18 01:18:47 PM PST 24
Peak memory 201216 kb
Host smart-b308b7dd-f330-4961-a3af-070688e9816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702713979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1702713979
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2334607816
Short name T725
Test name
Test status
Simulation time 3897483461 ps
CPU time 9.59 seconds
Started Feb 18 01:18:23 PM PST 24
Finished Feb 18 01:18:33 PM PST 24
Peak memory 201228 kb
Host smart-5b2a57d2-16aa-4fc8-a988-ddcbddb9f103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334607816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2334607816
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2225421724
Short name T131
Test name
Test status
Simulation time 5947845278 ps
CPU time 3.88 seconds
Started Feb 18 01:18:14 PM PST 24
Finished Feb 18 01:18:18 PM PST 24
Peak memory 201212 kb
Host smart-079ea3c9-ad98-4e83-abd6-a0a17cc92668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225421724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2225421724
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2377157981
Short name T480
Test name
Test status
Simulation time 505637011987 ps
CPU time 1022.65 seconds
Started Feb 18 01:18:29 PM PST 24
Finished Feb 18 01:35:33 PM PST 24
Peak memory 210008 kb
Host smart-2d2d6037-6715-4b15-8394-9b4a7d5af29d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377157981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2377157981
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1533095470
Short name T184
Test name
Test status
Simulation time 431641408967 ps
CPU time 509.89 seconds
Started Feb 18 01:18:34 PM PST 24
Finished Feb 18 01:27:05 PM PST 24
Peak memory 210088 kb
Host smart-d4d2e740-77cc-41fa-ad16-735515da361c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533095470 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1533095470
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2088650227
Short name T391
Test name
Test status
Simulation time 385651544 ps
CPU time 1.33 seconds
Started Feb 18 01:18:48 PM PST 24
Finished Feb 18 01:18:51 PM PST 24
Peak memory 201160 kb
Host smart-a464fd1f-40ee-48d9-8d27-4387271f422e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088650227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2088650227
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2338359169
Short name T765
Test name
Test status
Simulation time 170136674725 ps
CPU time 365.82 seconds
Started Feb 18 01:18:40 PM PST 24
Finished Feb 18 01:24:47 PM PST 24
Peak memory 201432 kb
Host smart-ef0a3bcc-ea84-4eaa-8576-bcca91f7d2be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338359169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2338359169
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3185037781
Short name T758
Test name
Test status
Simulation time 162165177551 ps
CPU time 53.7 seconds
Started Feb 18 01:18:40 PM PST 24
Finished Feb 18 01:19:35 PM PST 24
Peak memory 201472 kb
Host smart-ee5bf0e9-fa59-46ad-b769-6fc5829b6bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185037781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3185037781
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.132397753
Short name T346
Test name
Test status
Simulation time 164344106714 ps
CPU time 128.71 seconds
Started Feb 18 01:18:41 PM PST 24
Finished Feb 18 01:20:50 PM PST 24
Peak memory 201476 kb
Host smart-299f0249-513f-4160-93e3-506f6c9ffb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132397753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.132397753
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3095982581
Short name T606
Test name
Test status
Simulation time 492939592509 ps
CPU time 578.2 seconds
Started Feb 18 01:18:46 PM PST 24
Finished Feb 18 01:28:27 PM PST 24
Peak memory 201412 kb
Host smart-7d79ba3a-11e6-47b9-8060-0a8771f7bc99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095982581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3095982581
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.316346862
Short name T453
Test name
Test status
Simulation time 331858009729 ps
CPU time 341.14 seconds
Started Feb 18 01:18:40 PM PST 24
Finished Feb 18 01:24:22 PM PST 24
Peak memory 201496 kb
Host smart-a40f0df3-00cb-4a0f-901a-6705395e811f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316346862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.316346862
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3545029928
Short name T450
Test name
Test status
Simulation time 493934021549 ps
CPU time 531.15 seconds
Started Feb 18 01:18:39 PM PST 24
Finished Feb 18 01:27:31 PM PST 24
Peak memory 201504 kb
Host smart-682f4454-fdbe-4016-95c5-c85b31b5c639
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545029928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3545029928
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1611074671
Short name T744
Test name
Test status
Simulation time 343042238187 ps
CPU time 188.06 seconds
Started Feb 18 01:18:40 PM PST 24
Finished Feb 18 01:21:49 PM PST 24
Peak memory 201500 kb
Host smart-ef8d3caf-5446-40ca-af92-bde56efc5aae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611074671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1611074671
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3302908445
Short name T204
Test name
Test status
Simulation time 319810086189 ps
CPU time 519.39 seconds
Started Feb 18 01:18:41 PM PST 24
Finished Feb 18 01:27:21 PM PST 24
Peak memory 201368 kb
Host smart-0da174e0-ef87-4bdb-a359-be7ecf7ba73a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302908445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3302908445
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1780306588
Short name T51
Test name
Test status
Simulation time 101460933647 ps
CPU time 535.98 seconds
Started Feb 18 01:18:41 PM PST 24
Finished Feb 18 01:27:38 PM PST 24
Peak memory 201780 kb
Host smart-547b69de-bf35-4d1d-8684-87ea21d16b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780306588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1780306588
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4081565868
Short name T699
Test name
Test status
Simulation time 27158245684 ps
CPU time 55.38 seconds
Started Feb 18 01:18:41 PM PST 24
Finished Feb 18 01:19:37 PM PST 24
Peak memory 201216 kb
Host smart-1dd0d0b8-8253-4f5e-9f77-21065a5a4196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081565868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4081565868
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3799339269
Short name T676
Test name
Test status
Simulation time 4806628961 ps
CPU time 6.36 seconds
Started Feb 18 01:18:42 PM PST 24
Finished Feb 18 01:18:49 PM PST 24
Peak memory 201236 kb
Host smart-f8f19a28-4638-4945-816b-9b1b163e7098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799339269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3799339269
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.443724285
Short name T58
Test name
Test status
Simulation time 5930693511 ps
CPU time 1.75 seconds
Started Feb 18 01:18:35 PM PST 24
Finished Feb 18 01:18:37 PM PST 24
Peak memory 201220 kb
Host smart-650e7ad6-abe1-43b2-b2ae-da276ca4c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443724285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.443724285
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1486789272
Short name T696
Test name
Test status
Simulation time 171520732552 ps
CPU time 266.05 seconds
Started Feb 18 01:18:51 PM PST 24
Finished Feb 18 01:23:19 PM PST 24
Peak memory 201496 kb
Host smart-0499a61c-6752-4d83-a22d-fc7efcd63459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486789272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1486789272
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.371374472
Short name T200
Test name
Test status
Simulation time 793674553039 ps
CPU time 701.12 seconds
Started Feb 18 01:18:40 PM PST 24
Finished Feb 18 01:30:23 PM PST 24
Peak memory 210128 kb
Host smart-88790795-8d8a-4f92-ad3b-f70924f8d550
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371374472 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.371374472
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1847213769
Short name T414
Test name
Test status
Simulation time 378381499 ps
CPU time 1.42 seconds
Started Feb 18 01:19:00 PM PST 24
Finished Feb 18 01:19:01 PM PST 24
Peak memory 201156 kb
Host smart-56b3b3fb-1c11-4ec2-9583-2dd11454ff28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847213769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1847213769
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1177542247
Short name T19
Test name
Test status
Simulation time 499859605755 ps
CPU time 148.75 seconds
Started Feb 18 01:18:58 PM PST 24
Finished Feb 18 01:21:28 PM PST 24
Peak memory 201476 kb
Host smart-a1d8b6ce-b53d-4c14-b0bb-5115f824c4ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177542247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1177542247
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2624812490
Short name T345
Test name
Test status
Simulation time 328393270675 ps
CPU time 667.38 seconds
Started Feb 18 01:18:48 PM PST 24
Finished Feb 18 01:29:58 PM PST 24
Peak memory 201536 kb
Host smart-44f917c1-fadd-4bcb-bba9-40be0470db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624812490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2624812490
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2264849051
Short name T631
Test name
Test status
Simulation time 494042240274 ps
CPU time 295.22 seconds
Started Feb 18 01:18:48 PM PST 24
Finished Feb 18 01:23:45 PM PST 24
Peak memory 201424 kb
Host smart-91d68d1f-8d63-461d-ad6e-1fd7c591989e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264849051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2264849051
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2301568372
Short name T677
Test name
Test status
Simulation time 161252411833 ps
CPU time 153.46 seconds
Started Feb 18 01:18:48 PM PST 24
Finished Feb 18 01:21:24 PM PST 24
Peak memory 201260 kb
Host smart-49fadb2d-56b7-4d27-80eb-34d06dec837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301568372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2301568372
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1552601685
Short name T766
Test name
Test status
Simulation time 481911216040 ps
CPU time 555.78 seconds
Started Feb 18 01:18:50 PM PST 24
Finished Feb 18 01:28:07 PM PST 24
Peak memory 201460 kb
Host smart-0ed9c103-f4fb-47cc-865b-e456bd7b0b0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552601685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1552601685
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4289362328
Short name T169
Test name
Test status
Simulation time 327692872304 ps
CPU time 186.85 seconds
Started Feb 18 01:18:48 PM PST 24
Finished Feb 18 01:21:57 PM PST 24
Peak memory 201404 kb
Host smart-6217723a-6f1d-4e30-a0be-d190d7c3358f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289362328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4289362328
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1148985057
Short name T380
Test name
Test status
Simulation time 497908006024 ps
CPU time 1134.55 seconds
Started Feb 18 01:18:58 PM PST 24
Finished Feb 18 01:37:53 PM PST 24
Peak memory 201348 kb
Host smart-038b5d02-984e-4bdc-8ba8-ac00cab2d279
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148985057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1148985057
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3689410678
Short name T93
Test name
Test status
Simulation time 76589136629 ps
CPU time 249.47 seconds
Started Feb 18 01:18:58 PM PST 24
Finished Feb 18 01:23:08 PM PST 24
Peak memory 201708 kb
Host smart-4cf36d43-2820-4a60-b809-b4f758a0004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689410678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3689410678
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3375518564
Short name T712
Test name
Test status
Simulation time 33294778296 ps
CPU time 39.53 seconds
Started Feb 18 01:18:58 PM PST 24
Finished Feb 18 01:19:38 PM PST 24
Peak memory 201208 kb
Host smart-2e0e97f3-4e4c-45d8-9c09-f7cfa2174af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375518564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3375518564
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.520396873
Short name T664
Test name
Test status
Simulation time 4810552790 ps
CPU time 3.6 seconds
Started Feb 18 01:18:58 PM PST 24
Finished Feb 18 01:19:03 PM PST 24
Peak memory 201144 kb
Host smart-5a7aa76e-d83b-4f64-83d2-79192329f45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520396873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.520396873
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.559512795
Short name T82
Test name
Test status
Simulation time 5710315645 ps
CPU time 15.63 seconds
Started Feb 18 01:18:47 PM PST 24
Finished Feb 18 01:19:05 PM PST 24
Peak memory 201228 kb
Host smart-cff25e99-df59-48a4-959e-61317a661ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559512795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.559512795
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.658670453
Short name T179
Test name
Test status
Simulation time 245626207529 ps
CPU time 472.08 seconds
Started Feb 18 01:19:00 PM PST 24
Finished Feb 18 01:26:52 PM PST 24
Peak memory 218088 kb
Host smart-a8b7a31e-706a-4cda-bed4-79c9288b885a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658670453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
658670453
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1668972760
Short name T39
Test name
Test status
Simulation time 823213082532 ps
CPU time 558.41 seconds
Started Feb 18 01:19:02 PM PST 24
Finished Feb 18 01:28:21 PM PST 24
Peak memory 210132 kb
Host smart-c1e30bd6-309c-410d-a9d3-d141ff13e6e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668972760 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1668972760
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2867654537
Short name T638
Test name
Test status
Simulation time 400409728 ps
CPU time 0.89 seconds
Started Feb 18 01:15:00 PM PST 24
Finished Feb 18 01:15:03 PM PST 24
Peak memory 201160 kb
Host smart-068f9702-a2f7-489b-a44f-0893c18e37c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867654537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2867654537
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2554344340
Short name T735
Test name
Test status
Simulation time 489939483357 ps
CPU time 185.55 seconds
Started Feb 18 01:15:06 PM PST 24
Finished Feb 18 01:18:14 PM PST 24
Peak memory 201416 kb
Host smart-84c42f4b-1fa4-40e6-96d7-0eb3e6c6c85d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554344340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2554344340
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.39874637
Short name T305
Test name
Test status
Simulation time 339956421369 ps
CPU time 791.45 seconds
Started Feb 18 01:15:01 PM PST 24
Finished Feb 18 01:28:14 PM PST 24
Peak memory 201432 kb
Host smart-64ef25a3-8841-47cf-ab8d-6c47610d0e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39874637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.39874637
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3705328205
Short name T762
Test name
Test status
Simulation time 488322158334 ps
CPU time 1100.19 seconds
Started Feb 18 01:15:00 PM PST 24
Finished Feb 18 01:33:23 PM PST 24
Peak memory 201540 kb
Host smart-31e5ef45-2779-41f1-a80f-7735df49fe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705328205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3705328205
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.435981060
Short name T394
Test name
Test status
Simulation time 488317989299 ps
CPU time 286.4 seconds
Started Feb 18 01:14:58 PM PST 24
Finished Feb 18 01:19:46 PM PST 24
Peak memory 201380 kb
Host smart-3972d939-2c6a-48b0-ac79-63d0fae5b3be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=435981060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.435981060
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.4221286634
Short name T781
Test name
Test status
Simulation time 492801576935 ps
CPU time 318.78 seconds
Started Feb 18 01:15:04 PM PST 24
Finished Feb 18 01:20:26 PM PST 24
Peak memory 201404 kb
Host smart-077196bd-01a3-425c-9a7d-e7b48256a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221286634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.4221286634
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.62186138
Short name T733
Test name
Test status
Simulation time 162887932220 ps
CPU time 94.67 seconds
Started Feb 18 01:15:06 PM PST 24
Finished Feb 18 01:16:43 PM PST 24
Peak memory 201480 kb
Host smart-bc1ecb15-f421-4ff8-8c62-436beb2bedfd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=62186138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.62186138
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.517644582
Short name T706
Test name
Test status
Simulation time 503980149113 ps
CPU time 107.68 seconds
Started Feb 18 01:15:05 PM PST 24
Finished Feb 18 01:16:55 PM PST 24
Peak memory 201412 kb
Host smart-d75b96fa-6a51-407f-8224-fac26ab012ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517644582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.517644582
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1343527453
Short name T581
Test name
Test status
Simulation time 495581378572 ps
CPU time 1117.95 seconds
Started Feb 18 01:14:59 PM PST 24
Finished Feb 18 01:33:39 PM PST 24
Peak memory 201432 kb
Host smart-ff08fb4a-13ea-4cf0-ad1e-549e5efea53a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343527453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1343527453
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3516102712
Short name T24
Test name
Test status
Simulation time 77380664866 ps
CPU time 262.06 seconds
Started Feb 18 01:15:01 PM PST 24
Finished Feb 18 01:19:25 PM PST 24
Peak memory 201796 kb
Host smart-d41dbf43-34f8-4ce0-b04b-ccd94c597016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516102712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3516102712
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3936623472
Short name T484
Test name
Test status
Simulation time 29264040937 ps
CPU time 34.93 seconds
Started Feb 18 01:15:05 PM PST 24
Finished Feb 18 01:15:42 PM PST 24
Peak memory 201220 kb
Host smart-0f5b3788-b81d-45c2-b938-b91b350257c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936623472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3936623472
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3823829369
Short name T28
Test name
Test status
Simulation time 5403877259 ps
CPU time 13.18 seconds
Started Feb 18 01:15:05 PM PST 24
Finished Feb 18 01:15:20 PM PST 24
Peak memory 201224 kb
Host smart-7079a9c4-445d-4dd2-b1a0-32bfd03acff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823829369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3823829369
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2680421524
Short name T50
Test name
Test status
Simulation time 7762965459 ps
CPU time 4.92 seconds
Started Feb 18 01:15:00 PM PST 24
Finished Feb 18 01:15:07 PM PST 24
Peak memory 217448 kb
Host smart-8070d2e1-a66d-41d8-81a9-6f8c43195b92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680421524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2680421524
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3334274298
Short name T678
Test name
Test status
Simulation time 5887684472 ps
CPU time 8.47 seconds
Started Feb 18 01:15:01 PM PST 24
Finished Feb 18 01:15:12 PM PST 24
Peak memory 201216 kb
Host smart-a204cd00-637d-4364-8da3-86aa4d5436ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334274298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3334274298
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.259446539
Short name T226
Test name
Test status
Simulation time 362247176092 ps
CPU time 109.18 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:16:58 PM PST 24
Peak memory 201492 kb
Host smart-ca64e15a-c72c-49d2-a64c-b3795037353f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259446539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.259446539
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.971740059
Short name T228
Test name
Test status
Simulation time 63427813623 ps
CPU time 170.17 seconds
Started Feb 18 01:15:03 PM PST 24
Finished Feb 18 01:17:57 PM PST 24
Peak memory 211224 kb
Host smart-6b039f7f-6a5d-4085-b898-4e19fba357dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971740059 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.971740059
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1246884111
Short name T789
Test name
Test status
Simulation time 424489591 ps
CPU time 1.66 seconds
Started Feb 18 01:19:17 PM PST 24
Finished Feb 18 01:19:19 PM PST 24
Peak memory 201136 kb
Host smart-9d27ba80-dc3d-4938-a585-5f80a3335b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246884111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1246884111
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.4020382637
Short name T265
Test name
Test status
Simulation time 165151133686 ps
CPU time 99.7 seconds
Started Feb 18 01:19:03 PM PST 24
Finished Feb 18 01:20:43 PM PST 24
Peak memory 201392 kb
Host smart-54c3e9ee-d4e3-43c3-9cd9-4415dec60308
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020382637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.4020382637
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1043476254
Short name T773
Test name
Test status
Simulation time 161514098227 ps
CPU time 400.58 seconds
Started Feb 18 01:18:58 PM PST 24
Finished Feb 18 01:25:39 PM PST 24
Peak memory 201428 kb
Host smart-6275bd5c-ea60-4386-a30c-864dc74a374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043476254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1043476254
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.597417794
Short name T544
Test name
Test status
Simulation time 488479847585 ps
CPU time 587 seconds
Started Feb 18 01:19:01 PM PST 24
Finished Feb 18 01:28:48 PM PST 24
Peak memory 201420 kb
Host smart-0ce40693-cdc1-4203-b3c3-a2ffb6ec448b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=597417794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.597417794
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3806344754
Short name T776
Test name
Test status
Simulation time 491547863396 ps
CPU time 289.57 seconds
Started Feb 18 01:18:58 PM PST 24
Finished Feb 18 01:23:49 PM PST 24
Peak memory 201444 kb
Host smart-7576da95-ec3f-4d26-b26d-67635b7db79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806344754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3806344754
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2111693287
Short name T71
Test name
Test status
Simulation time 162610496323 ps
CPU time 60.56 seconds
Started Feb 18 01:19:00 PM PST 24
Finished Feb 18 01:20:01 PM PST 24
Peak memory 201396 kb
Host smart-5642b4e0-9d6c-4ea1-b445-2458b8fed288
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111693287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2111693287
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3330101525
Short name T695
Test name
Test status
Simulation time 484802300003 ps
CPU time 333.52 seconds
Started Feb 18 01:19:05 PM PST 24
Finished Feb 18 01:24:39 PM PST 24
Peak memory 201472 kb
Host smart-8cbec24f-9cfc-472c-8120-faee86b6bc70
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330101525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3330101525
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.83913560
Short name T663
Test name
Test status
Simulation time 498745931238 ps
CPU time 1104.98 seconds
Started Feb 18 01:19:05 PM PST 24
Finished Feb 18 01:37:31 PM PST 24
Peak memory 201424 kb
Host smart-5f7962f5-ece5-4d7e-a80d-b5670d11a7e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83913560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.a
dc_ctrl_filters_wakeup_fixed.83913560
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.967389270
Short name T25
Test name
Test status
Simulation time 76878401410 ps
CPU time 404.91 seconds
Started Feb 18 01:19:04 PM PST 24
Finished Feb 18 01:25:49 PM PST 24
Peak memory 201740 kb
Host smart-4d76841b-6125-431c-9f1c-f78bbddda827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967389270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.967389270
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3659991987
Short name T462
Test name
Test status
Simulation time 28882444080 ps
CPU time 20.41 seconds
Started Feb 18 01:19:03 PM PST 24
Finished Feb 18 01:19:24 PM PST 24
Peak memory 201224 kb
Host smart-add8493a-41f5-4e5d-a9ff-65fc5edea78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659991987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3659991987
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1319478761
Short name T370
Test name
Test status
Simulation time 4208223721 ps
CPU time 3.18 seconds
Started Feb 18 01:19:04 PM PST 24
Finished Feb 18 01:19:08 PM PST 24
Peak memory 201248 kb
Host smart-d27ad252-b1e2-467b-be56-fb930e99a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319478761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1319478761
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2612573610
Short name T651
Test name
Test status
Simulation time 5753949830 ps
CPU time 14.62 seconds
Started Feb 18 01:18:59 PM PST 24
Finished Feb 18 01:19:14 PM PST 24
Peak memory 201236 kb
Host smart-28587164-92bb-41ba-b7d4-58c323eedf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612573610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2612573610
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.734053771
Short name T320
Test name
Test status
Simulation time 48019573725 ps
CPU time 69.91 seconds
Started Feb 18 01:19:04 PM PST 24
Finished Feb 18 01:20:14 PM PST 24
Peak memory 201580 kb
Host smart-161bf70e-e997-41c7-bcef-ba6d96f41dbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734053771 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.734053771
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.726187989
Short name T436
Test name
Test status
Simulation time 449544297 ps
CPU time 1.63 seconds
Started Feb 18 01:19:20 PM PST 24
Finished Feb 18 01:19:22 PM PST 24
Peak memory 201176 kb
Host smart-334a04a7-a9a6-4ac2-9919-d4615191853c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726187989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.726187989
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.4169626852
Short name T739
Test name
Test status
Simulation time 335785446499 ps
CPU time 402.45 seconds
Started Feb 18 01:19:20 PM PST 24
Finished Feb 18 01:26:03 PM PST 24
Peak memory 201432 kb
Host smart-07b97647-b06a-45b6-a289-cd00fcdd19be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169626852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.4169626852
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.554241481
Short name T284
Test name
Test status
Simulation time 489006911883 ps
CPU time 1184.44 seconds
Started Feb 18 01:19:22 PM PST 24
Finished Feb 18 01:39:07 PM PST 24
Peak memory 201440 kb
Host smart-95353997-2592-448d-9439-98efe4866913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554241481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.554241481
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3718816645
Short name T57
Test name
Test status
Simulation time 485719817803 ps
CPU time 1134.08 seconds
Started Feb 18 01:19:18 PM PST 24
Finished Feb 18 01:38:13 PM PST 24
Peak memory 201408 kb
Host smart-8bc6769b-dd7c-4497-82f8-d0d82daab131
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718816645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3718816645
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3683693575
Short name T160
Test name
Test status
Simulation time 331060113021 ps
CPU time 182.16 seconds
Started Feb 18 01:19:22 PM PST 24
Finished Feb 18 01:22:24 PM PST 24
Peak memory 201392 kb
Host smart-3d9fdf67-5b8a-4634-903c-6455fcc3f1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683693575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3683693575
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3821521491
Short name T2
Test name
Test status
Simulation time 163188350176 ps
CPU time 32.84 seconds
Started Feb 18 01:19:21 PM PST 24
Finished Feb 18 01:19:54 PM PST 24
Peak memory 201464 kb
Host smart-fed0efd3-a094-478e-849d-3ffdad77db7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821521491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3821521491
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.215403145
Short name T283
Test name
Test status
Simulation time 487076395854 ps
CPU time 1116.75 seconds
Started Feb 18 01:19:21 PM PST 24
Finished Feb 18 01:37:58 PM PST 24
Peak memory 201488 kb
Host smart-7649e7b6-87ff-4893-af99-020043086f8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215403145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.215403145
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3757122094
Short name T438
Test name
Test status
Simulation time 497192379192 ps
CPU time 1104.49 seconds
Started Feb 18 01:19:24 PM PST 24
Finished Feb 18 01:37:49 PM PST 24
Peak memory 201480 kb
Host smart-19a7e75d-6363-4a4e-9e3c-6a0261b89198
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757122094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3757122094
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3415926762
Short name T211
Test name
Test status
Simulation time 104691534415 ps
CPU time 426.81 seconds
Started Feb 18 01:19:21 PM PST 24
Finished Feb 18 01:26:28 PM PST 24
Peak memory 201744 kb
Host smart-cffb381f-5895-4a53-a993-04f9369e93c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415926762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3415926762
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3047391727
Short name T389
Test name
Test status
Simulation time 33300834693 ps
CPU time 69.28 seconds
Started Feb 18 01:19:20 PM PST 24
Finished Feb 18 01:20:30 PM PST 24
Peak memory 201228 kb
Host smart-6e33af21-014b-4db4-8d96-340b8cd4fd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047391727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3047391727
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2311088451
Short name T81
Test name
Test status
Simulation time 4630425108 ps
CPU time 3.28 seconds
Started Feb 18 01:19:20 PM PST 24
Finished Feb 18 01:19:24 PM PST 24
Peak memory 201224 kb
Host smart-b520084b-17c1-46fe-9fdb-0d48a5940dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311088451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2311088451
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3090046878
Short name T518
Test name
Test status
Simulation time 5709465950 ps
CPU time 4.17 seconds
Started Feb 18 01:19:17 PM PST 24
Finished Feb 18 01:19:21 PM PST 24
Peak memory 201236 kb
Host smart-cbe4ab55-243f-43c9-9b41-60ff9dc65661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090046878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3090046878
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3502196196
Short name T728
Test name
Test status
Simulation time 332490943124 ps
CPU time 751.38 seconds
Started Feb 18 01:19:26 PM PST 24
Finished Feb 18 01:31:58 PM PST 24
Peak memory 201420 kb
Host smart-c9d35535-7420-4ef3-a1fb-d68fbab55e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502196196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3502196196
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2715872384
Short name T760
Test name
Test status
Simulation time 285030353 ps
CPU time 1.26 seconds
Started Feb 18 01:19:43 PM PST 24
Finished Feb 18 01:19:45 PM PST 24
Peak memory 201164 kb
Host smart-44f3fd4d-c231-4d7d-9919-82b6a10c5016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715872384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2715872384
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.751698256
Short name T500
Test name
Test status
Simulation time 167241760233 ps
CPU time 56.12 seconds
Started Feb 18 01:19:34 PM PST 24
Finished Feb 18 01:20:31 PM PST 24
Peak memory 201424 kb
Host smart-b092861f-4825-4742-8de5-cf77b7958d8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751698256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.751698256
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2313230743
Short name T538
Test name
Test status
Simulation time 161269508488 ps
CPU time 325.27 seconds
Started Feb 18 01:19:44 PM PST 24
Finished Feb 18 01:25:10 PM PST 24
Peak memory 201524 kb
Host smart-92440bf5-4310-4f68-9daa-3228b0131402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313230743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2313230743
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3285781483
Short name T67
Test name
Test status
Simulation time 325870404735 ps
CPU time 513.53 seconds
Started Feb 18 01:19:27 PM PST 24
Finished Feb 18 01:28:01 PM PST 24
Peak memory 201528 kb
Host smart-c8bf9892-6e15-4d51-9e04-0b8a164c1b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285781483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3285781483
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3194037609
Short name T552
Test name
Test status
Simulation time 332418446174 ps
CPU time 207.98 seconds
Started Feb 18 01:19:27 PM PST 24
Finished Feb 18 01:22:56 PM PST 24
Peak memory 201424 kb
Host smart-143e0c31-c2ae-4f38-9a64-4a4807d60d6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194037609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3194037609
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3503824260
Short name T429
Test name
Test status
Simulation time 168886145253 ps
CPU time 362.66 seconds
Started Feb 18 01:19:28 PM PST 24
Finished Feb 18 01:25:31 PM PST 24
Peak memory 201452 kb
Host smart-b9f03867-2486-4a9c-99b0-34135ce5edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503824260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3503824260
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2534648416
Short name T420
Test name
Test status
Simulation time 483421329123 ps
CPU time 240.12 seconds
Started Feb 18 01:19:26 PM PST 24
Finished Feb 18 01:23:26 PM PST 24
Peak memory 201456 kb
Host smart-93d1b2ba-8e29-479c-a6a8-ea8382e4d479
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534648416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2534648416
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2689959143
Short name T148
Test name
Test status
Simulation time 487412683170 ps
CPU time 251.43 seconds
Started Feb 18 01:19:27 PM PST 24
Finished Feb 18 01:23:39 PM PST 24
Peak memory 201400 kb
Host smart-2fcec7d7-0680-449b-b6c6-f8d99aa6a0b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689959143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2689959143
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.27369646
Short name T566
Test name
Test status
Simulation time 163152758394 ps
CPU time 185.66 seconds
Started Feb 18 01:19:33 PM PST 24
Finished Feb 18 01:22:40 PM PST 24
Peak memory 201412 kb
Host smart-4d274125-77c8-4dd9-a2e3-4ea8ce7c933e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27369646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.a
dc_ctrl_filters_wakeup_fixed.27369646
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2192612744
Short name T356
Test name
Test status
Simulation time 126019597582 ps
CPU time 511.64 seconds
Started Feb 18 01:19:40 PM PST 24
Finished Feb 18 01:28:12 PM PST 24
Peak memory 201820 kb
Host smart-0fe46a50-4535-4576-ac38-d838ef00d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192612744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2192612744
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1630081199
Short name T361
Test name
Test status
Simulation time 28932997906 ps
CPU time 64.86 seconds
Started Feb 18 01:19:35 PM PST 24
Finished Feb 18 01:20:40 PM PST 24
Peak memory 201216 kb
Host smart-d6151d68-8fc6-4e61-86f8-37f7109f7306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630081199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1630081199
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2714449804
Short name T724
Test name
Test status
Simulation time 3536337269 ps
CPU time 2.49 seconds
Started Feb 18 01:19:30 PM PST 24
Finished Feb 18 01:19:33 PM PST 24
Peak memory 201176 kb
Host smart-50bd1268-2f7b-4058-83c7-bb99afea24f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714449804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2714449804
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2262482161
Short name T629
Test name
Test status
Simulation time 6155797845 ps
CPU time 4.38 seconds
Started Feb 18 01:19:34 PM PST 24
Finished Feb 18 01:19:39 PM PST 24
Peak memory 201228 kb
Host smart-8c868366-b8f5-46a7-8ba1-39f696611f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262482161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2262482161
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.127084765
Short name T470
Test name
Test status
Simulation time 457439937 ps
CPU time 0.85 seconds
Started Feb 18 01:19:53 PM PST 24
Finished Feb 18 01:19:55 PM PST 24
Peak memory 201084 kb
Host smart-1e9af157-1912-4468-802c-8d2133393152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127084765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.127084765
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.417919085
Short name T334
Test name
Test status
Simulation time 492382938117 ps
CPU time 244.99 seconds
Started Feb 18 01:19:57 PM PST 24
Finished Feb 18 01:24:03 PM PST 24
Peak memory 201484 kb
Host smart-d5a4741f-cd1e-4621-8f05-f1fc201ed4b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417919085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.417919085
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2890989028
Short name T579
Test name
Test status
Simulation time 492039802959 ps
CPU time 187.38 seconds
Started Feb 18 01:19:48 PM PST 24
Finished Feb 18 01:22:57 PM PST 24
Peak memory 201416 kb
Host smart-b0e2e932-ac59-4ae5-81d7-02a7c147b294
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890989028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2890989028
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3353547831
Short name T584
Test name
Test status
Simulation time 488562331260 ps
CPU time 598.96 seconds
Started Feb 18 01:19:48 PM PST 24
Finished Feb 18 01:29:49 PM PST 24
Peak memory 201516 kb
Host smart-759c3279-f6d5-4d10-ad90-3cc3c54e99cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353547831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3353547831
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.4290754281
Short name T526
Test name
Test status
Simulation time 481966420907 ps
CPU time 270.46 seconds
Started Feb 18 01:19:43 PM PST 24
Finished Feb 18 01:24:14 PM PST 24
Peak memory 201416 kb
Host smart-6d1b4af0-106a-4121-938e-16a89f102290
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290754281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.4290754281
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3838699699
Short name T95
Test name
Test status
Simulation time 169076139631 ps
CPU time 231.73 seconds
Started Feb 18 01:19:52 PM PST 24
Finished Feb 18 01:23:45 PM PST 24
Peak memory 201424 kb
Host smart-9c77396f-cb73-4be0-9477-485d0a53092e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838699699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3838699699
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2465088625
Short name T485
Test name
Test status
Simulation time 164109289133 ps
CPU time 364.49 seconds
Started Feb 18 01:19:49 PM PST 24
Finished Feb 18 01:25:55 PM PST 24
Peak memory 201420 kb
Host smart-1024c2a5-e3fe-4b08-ae0e-b54f951e6a0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465088625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2465088625
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3328537560
Short name T539
Test name
Test status
Simulation time 74130968075 ps
CPU time 280.46 seconds
Started Feb 18 01:20:14 PM PST 24
Finished Feb 18 01:24:56 PM PST 24
Peak memory 201712 kb
Host smart-a0c05a60-3b5f-4a1f-bf5c-dac32a116f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328537560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3328537560
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3884220949
Short name T381
Test name
Test status
Simulation time 31159805969 ps
CPU time 20.38 seconds
Started Feb 18 01:19:59 PM PST 24
Finished Feb 18 01:20:19 PM PST 24
Peak memory 201248 kb
Host smart-1fe96690-b106-46ec-bc7c-b83f8822343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884220949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3884220949
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3880780767
Short name T537
Test name
Test status
Simulation time 3478373538 ps
CPU time 2.56 seconds
Started Feb 18 01:19:53 PM PST 24
Finished Feb 18 01:19:56 PM PST 24
Peak memory 201220 kb
Host smart-a9903fc1-5743-4e17-a156-b14b282c303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880780767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3880780767
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1523516306
Short name T698
Test name
Test status
Simulation time 5757704506 ps
CPU time 14.67 seconds
Started Feb 18 01:19:42 PM PST 24
Finished Feb 18 01:19:57 PM PST 24
Peak memory 201224 kb
Host smart-83a85659-f6fd-45ce-9041-2b3e3bb67781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523516306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1523516306
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3598543244
Short name T199
Test name
Test status
Simulation time 157131867334 ps
CPU time 202.52 seconds
Started Feb 18 01:19:55 PM PST 24
Finished Feb 18 01:23:18 PM PST 24
Peak memory 210064 kb
Host smart-c824577f-085c-4c5f-ac41-5dc3d935b3f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598543244 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3598543244
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3487189915
Short name T392
Test name
Test status
Simulation time 343859780 ps
CPU time 0.84 seconds
Started Feb 18 01:20:00 PM PST 24
Finished Feb 18 01:20:01 PM PST 24
Peak memory 201168 kb
Host smart-d389283a-7802-41a9-bb5f-a915af1c81c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487189915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3487189915
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1901530400
Short name T626
Test name
Test status
Simulation time 331607647930 ps
CPU time 215.79 seconds
Started Feb 18 01:20:12 PM PST 24
Finished Feb 18 01:23:49 PM PST 24
Peak memory 201440 kb
Host smart-c16375d5-6ff7-40c7-955f-44b9c7992857
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901530400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1901530400
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1583636953
Short name T298
Test name
Test status
Simulation time 490690891455 ps
CPU time 136.91 seconds
Started Feb 18 01:19:52 PM PST 24
Finished Feb 18 01:22:10 PM PST 24
Peak memory 201508 kb
Host smart-d8afb430-3700-40b2-a6c6-433b5a0a589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583636953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1583636953
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2379307918
Short name T12
Test name
Test status
Simulation time 330596782971 ps
CPU time 165.28 seconds
Started Feb 18 01:19:59 PM PST 24
Finished Feb 18 01:22:46 PM PST 24
Peak memory 201436 kb
Host smart-48e2df22-09a2-4ab4-b1df-426618ad44cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379307918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2379307918
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2205357754
Short name T483
Test name
Test status
Simulation time 172629940634 ps
CPU time 99.76 seconds
Started Feb 18 01:19:52 PM PST 24
Finished Feb 18 01:21:33 PM PST 24
Peak memory 201436 kb
Host smart-9850f2f7-e1fb-4ae5-9e9b-e77b0d065780
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205357754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2205357754
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1681314362
Short name T694
Test name
Test status
Simulation time 489622646161 ps
CPU time 1154.79 seconds
Started Feb 18 01:20:07 PM PST 24
Finished Feb 18 01:39:23 PM PST 24
Peak memory 201468 kb
Host smart-2afd653d-ac5b-4021-847f-ebbdcc8eaa3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681314362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1681314362
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.779239049
Short name T454
Test name
Test status
Simulation time 329126978608 ps
CPU time 735.15 seconds
Started Feb 18 01:20:12 PM PST 24
Finished Feb 18 01:32:29 PM PST 24
Peak memory 201412 kb
Host smart-91a712b8-b2d9-46f0-bbc2-373ed46b408f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779239049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.779239049
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3609517534
Short name T624
Test name
Test status
Simulation time 72873669413 ps
CPU time 393.36 seconds
Started Feb 18 01:20:02 PM PST 24
Finished Feb 18 01:26:37 PM PST 24
Peak memory 201752 kb
Host smart-bfa23993-7f33-49df-890e-7a5ae8742ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609517534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3609517534
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2387048381
Short name T469
Test name
Test status
Simulation time 44549538913 ps
CPU time 98.81 seconds
Started Feb 18 01:20:01 PM PST 24
Finished Feb 18 01:21:41 PM PST 24
Peak memory 201236 kb
Host smart-fd5eddd0-902d-44a5-8fd3-be7d7fcc6f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387048381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2387048381
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2791689208
Short name T172
Test name
Test status
Simulation time 4049339928 ps
CPU time 9.84 seconds
Started Feb 18 01:19:59 PM PST 24
Finished Feb 18 01:20:10 PM PST 24
Peak memory 201224 kb
Host smart-6fee84cd-8688-458c-abbe-509ecad1d9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791689208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2791689208
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.882041450
Short name T373
Test name
Test status
Simulation time 5600287319 ps
CPU time 2.68 seconds
Started Feb 18 01:19:55 PM PST 24
Finished Feb 18 01:19:59 PM PST 24
Peak memory 201136 kb
Host smart-16d94290-ff95-4a1d-ad3f-a411feef7b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882041450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.882041450
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2102696280
Short name T118
Test name
Test status
Simulation time 363218459512 ps
CPU time 402.73 seconds
Started Feb 18 01:20:07 PM PST 24
Finished Feb 18 01:26:51 PM PST 24
Peak memory 201500 kb
Host smart-d9a93860-6f7a-4c17-b883-9e8716f661a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102696280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2102696280
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1799594676
Short name T701
Test name
Test status
Simulation time 45569209548 ps
CPU time 88.23 seconds
Started Feb 18 01:20:01 PM PST 24
Finished Feb 18 01:21:31 PM PST 24
Peak memory 201736 kb
Host smart-5cf47e45-a233-44b3-91e3-f1221e693fc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799594676 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1799594676
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2186834381
Short name T647
Test name
Test status
Simulation time 391318327 ps
CPU time 1.09 seconds
Started Feb 18 01:20:16 PM PST 24
Finished Feb 18 01:20:19 PM PST 24
Peak memory 201196 kb
Host smart-054ffb00-f635-4134-9d94-76c70a1b6e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186834381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2186834381
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.425603082
Short name T616
Test name
Test status
Simulation time 485021042330 ps
CPU time 1103.47 seconds
Started Feb 18 01:20:11 PM PST 24
Finished Feb 18 01:38:35 PM PST 24
Peak memory 201384 kb
Host smart-214b144a-f89d-4e7d-8761-d6ba2182ccd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425603082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.425603082
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2178271144
Short name T778
Test name
Test status
Simulation time 498718053533 ps
CPU time 160.65 seconds
Started Feb 18 01:19:59 PM PST 24
Finished Feb 18 01:22:41 PM PST 24
Peak memory 201472 kb
Host smart-915a1c8e-bb05-4e8d-8e7a-b0f9ae898967
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178271144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2178271144
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4208507603
Short name T333
Test name
Test status
Simulation time 165624445579 ps
CPU time 96.19 seconds
Started Feb 18 01:20:01 PM PST 24
Finished Feb 18 01:21:38 PM PST 24
Peak memory 201388 kb
Host smart-f28310a3-4228-459b-971f-c4e450987621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208507603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4208507603
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.557556877
Short name T91
Test name
Test status
Simulation time 498183975856 ps
CPU time 1230.77 seconds
Started Feb 18 01:20:00 PM PST 24
Finished Feb 18 01:40:32 PM PST 24
Peak memory 201472 kb
Host smart-56381afb-6405-43ce-823e-f6688979b1ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=557556877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.557556877
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2972161275
Short name T492
Test name
Test status
Simulation time 164945219565 ps
CPU time 188.74 seconds
Started Feb 18 01:20:12 PM PST 24
Finished Feb 18 01:23:23 PM PST 24
Peak memory 201392 kb
Host smart-4ff2547d-34ff-4e05-861d-d21c0636948b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972161275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2972161275
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3459640114
Short name T517
Test name
Test status
Simulation time 325111633843 ps
CPU time 393.55 seconds
Started Feb 18 01:20:07 PM PST 24
Finished Feb 18 01:26:42 PM PST 24
Peak memory 201532 kb
Host smart-84027cb2-16c3-42f7-a0b6-abded76299a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459640114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3459640114
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.857697414
Short name T534
Test name
Test status
Simulation time 64545577762 ps
CPU time 265.8 seconds
Started Feb 18 01:20:15 PM PST 24
Finished Feb 18 01:24:44 PM PST 24
Peak memory 201792 kb
Host smart-645fd3cb-9705-4c32-9095-d91d17ae8e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857697414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.857697414
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.86548415
Short name T644
Test name
Test status
Simulation time 39184667558 ps
CPU time 48.02 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:21:07 PM PST 24
Peak memory 201228 kb
Host smart-30c89a41-ffe3-4828-bf15-edaa7ff92e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86548415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.86548415
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.314281619
Short name T432
Test name
Test status
Simulation time 4165737851 ps
CPU time 5.23 seconds
Started Feb 18 01:20:13 PM PST 24
Finished Feb 18 01:20:19 PM PST 24
Peak memory 201232 kb
Host smart-86a2b920-3505-454e-b817-47ae87c86885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314281619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.314281619
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2517776420
Short name T659
Test name
Test status
Simulation time 5969056655 ps
CPU time 3.36 seconds
Started Feb 18 01:20:13 PM PST 24
Finished Feb 18 01:20:18 PM PST 24
Peak memory 201128 kb
Host smart-8f595367-65bc-4768-b1a0-61ff1debf007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517776420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2517776420
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3389248790
Short name T275
Test name
Test status
Simulation time 172198244107 ps
CPU time 198.97 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:23:38 PM PST 24
Peak memory 201488 kb
Host smart-f7c5e2bc-f81a-41b2-b07f-c64fdc526cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389248790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3389248790
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.257923870
Short name T198
Test name
Test status
Simulation time 8565467014 ps
CPU time 21.93 seconds
Started Feb 18 01:20:15 PM PST 24
Finished Feb 18 01:20:39 PM PST 24
Peak memory 209760 kb
Host smart-55c910d0-4aaf-42f0-a8bb-dac8e5b2d216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257923870 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.257923870
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1890334034
Short name T44
Test name
Test status
Simulation time 531874243 ps
CPU time 1.87 seconds
Started Feb 18 01:20:24 PM PST 24
Finished Feb 18 01:20:27 PM PST 24
Peak memory 201156 kb
Host smart-db50bb08-01e2-4f51-b67a-1dcf364dc290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890334034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1890334034
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2249467719
Short name T256
Test name
Test status
Simulation time 339621410484 ps
CPU time 204.34 seconds
Started Feb 18 01:20:16 PM PST 24
Finished Feb 18 01:23:42 PM PST 24
Peak memory 201376 kb
Host smart-70f8752f-877e-490d-9b5b-f37dfe057bd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249467719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2249467719
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3395511305
Short name T586
Test name
Test status
Simulation time 160723728055 ps
CPU time 175.35 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:23:14 PM PST 24
Peak memory 201392 kb
Host smart-78778156-4ecd-42b0-94f6-a3309f2ab7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395511305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3395511305
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2075433367
Short name T147
Test name
Test status
Simulation time 495381537081 ps
CPU time 304.11 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:25:23 PM PST 24
Peak memory 201436 kb
Host smart-614c92a7-d9d1-46e7-b18d-4d1cfff4aa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075433367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2075433367
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.98982363
Short name T749
Test name
Test status
Simulation time 331258594900 ps
CPU time 380.79 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:26:40 PM PST 24
Peak memory 201288 kb
Host smart-25fc4bca-e8d5-4a78-a6fe-2bbde89cd960
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=98982363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt
_fixed.98982363
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.875248738
Short name T178
Test name
Test status
Simulation time 485396341017 ps
CPU time 243.32 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:24:23 PM PST 24
Peak memory 201488 kb
Host smart-54d8b58f-9974-4ea2-8a27-75d57495503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875248738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.875248738
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1681508360
Short name T447
Test name
Test status
Simulation time 492944515111 ps
CPU time 579.14 seconds
Started Feb 18 01:20:15 PM PST 24
Finished Feb 18 01:29:56 PM PST 24
Peak memory 201460 kb
Host smart-deb951c7-16ab-4c45-a55d-02cd1bddc485
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681508360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1681508360
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1934628942
Short name T246
Test name
Test status
Simulation time 168348410650 ps
CPU time 97.45 seconds
Started Feb 18 01:20:16 PM PST 24
Finished Feb 18 01:21:56 PM PST 24
Peak memory 201428 kb
Host smart-76dbb1d7-4fe8-4327-a33b-9d023d18c205
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934628942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1934628942
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.134983129
Short name T154
Test name
Test status
Simulation time 170651320482 ps
CPU time 415.04 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:27:15 PM PST 24
Peak memory 201384 kb
Host smart-e04392f5-c5d6-42f8-aeae-b5fabad1a3b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134983129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.134983129
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1217489419
Short name T783
Test name
Test status
Simulation time 95411406519 ps
CPU time 415.68 seconds
Started Feb 18 01:20:15 PM PST 24
Finished Feb 18 01:27:12 PM PST 24
Peak memory 201800 kb
Host smart-d8199be3-ea61-4282-9621-336b39ee4082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217489419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1217489419
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.943313050
Short name T434
Test name
Test status
Simulation time 42614949958 ps
CPU time 27.55 seconds
Started Feb 18 01:20:16 PM PST 24
Finished Feb 18 01:20:46 PM PST 24
Peak memory 201116 kb
Host smart-8941c0e6-0323-4bb0-a481-55a34405d64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943313050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.943313050
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3091105445
Short name T445
Test name
Test status
Simulation time 5332740861 ps
CPU time 1.36 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:20:20 PM PST 24
Peak memory 201220 kb
Host smart-79e5f388-1ec8-4a16-820d-435552f42557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091105445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3091105445
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.816565962
Short name T397
Test name
Test status
Simulation time 5937892773 ps
CPU time 13.95 seconds
Started Feb 18 01:20:17 PM PST 24
Finished Feb 18 01:20:33 PM PST 24
Peak memory 201224 kb
Host smart-72d6e359-c2f5-4816-8052-0dfc73306e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816565962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.816565962
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.7054276
Short name T650
Test name
Test status
Simulation time 501331999 ps
CPU time 0.86 seconds
Started Feb 18 01:20:41 PM PST 24
Finished Feb 18 01:20:43 PM PST 24
Peak memory 201156 kb
Host smart-76e5857a-f681-456d-b58a-cfde0f104727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7054276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.7054276
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3299195036
Short name T59
Test name
Test status
Simulation time 326258802468 ps
CPU time 709.28 seconds
Started Feb 18 01:20:39 PM PST 24
Finished Feb 18 01:32:31 PM PST 24
Peak memory 201516 kb
Host smart-d8268570-698a-4582-a143-765e3a905ca5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299195036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3299195036
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2157167174
Short name T611
Test name
Test status
Simulation time 154994293276 ps
CPU time 102 seconds
Started Feb 18 01:20:36 PM PST 24
Finished Feb 18 01:22:20 PM PST 24
Peak memory 201492 kb
Host smart-f7431dcd-b049-4d7c-8e82-e4c3fbc8847a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157167174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2157167174
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.392808419
Short name T227
Test name
Test status
Simulation time 329872395098 ps
CPU time 407.23 seconds
Started Feb 18 01:20:27 PM PST 24
Finished Feb 18 01:27:15 PM PST 24
Peak memory 201432 kb
Host smart-fecb5bea-43de-410d-8c59-deb954196352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392808419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.392808419
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2306149708
Short name T714
Test name
Test status
Simulation time 481523741168 ps
CPU time 1160.33 seconds
Started Feb 18 01:20:29 PM PST 24
Finished Feb 18 01:39:50 PM PST 24
Peak memory 201400 kb
Host smart-82bcad5b-3d90-4f74-9c0a-0e67ccfb1a13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306149708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2306149708
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3439989404
Short name T653
Test name
Test status
Simulation time 333554462777 ps
CPU time 737.25 seconds
Started Feb 18 01:20:25 PM PST 24
Finished Feb 18 01:32:43 PM PST 24
Peak memory 201364 kb
Host smart-23fc72e0-6bb5-4ad6-a981-944ffd4eb2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439989404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3439989404
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2041511540
Short name T524
Test name
Test status
Simulation time 495434987928 ps
CPU time 1148.56 seconds
Started Feb 18 01:20:28 PM PST 24
Finished Feb 18 01:39:37 PM PST 24
Peak memory 201420 kb
Host smart-e4876822-d5d3-465a-ab2e-887824016324
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041511540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2041511540
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3581512677
Short name T634
Test name
Test status
Simulation time 492164648704 ps
CPU time 306.47 seconds
Started Feb 18 01:20:31 PM PST 24
Finished Feb 18 01:25:39 PM PST 24
Peak memory 201480 kb
Host smart-1c064f11-fab7-4812-9536-766acfbb670e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581512677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3581512677
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2862937870
Short name T732
Test name
Test status
Simulation time 106820643822 ps
CPU time 586.25 seconds
Started Feb 18 01:20:32 PM PST 24
Finished Feb 18 01:30:19 PM PST 24
Peak memory 201720 kb
Host smart-5bd2fafa-234c-466c-acd2-238654d2b34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862937870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2862937870
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.217888213
Short name T642
Test name
Test status
Simulation time 30118482091 ps
CPU time 68.16 seconds
Started Feb 18 01:20:39 PM PST 24
Finished Feb 18 01:21:49 PM PST 24
Peak memory 201232 kb
Host smart-84bb278a-b0ee-4901-9bce-69a1889123b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217888213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.217888213
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1125885711
Short name T784
Test name
Test status
Simulation time 3297746424 ps
CPU time 2.33 seconds
Started Feb 18 01:20:39 PM PST 24
Finished Feb 18 01:20:42 PM PST 24
Peak memory 201200 kb
Host smart-a62fd69c-8631-42d4-ae79-d0828bf9d566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125885711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1125885711
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.580469058
Short name T6
Test name
Test status
Simulation time 5681030150 ps
CPU time 13.56 seconds
Started Feb 18 01:20:23 PM PST 24
Finished Feb 18 01:20:37 PM PST 24
Peak memory 201172 kb
Host smart-b0c5be27-c719-4556-a07e-57dbb168e892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580469058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.580469058
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3961753911
Short name T261
Test name
Test status
Simulation time 196455499035 ps
CPU time 482.85 seconds
Started Feb 18 01:20:31 PM PST 24
Finished Feb 18 01:28:35 PM PST 24
Peak memory 201384 kb
Host smart-e770d64a-4998-4d65-85b6-58250f11e8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961753911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3961753911
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3503824672
Short name T195
Test name
Test status
Simulation time 33040116237 ps
CPU time 53.4 seconds
Started Feb 18 01:20:39 PM PST 24
Finished Feb 18 01:21:35 PM PST 24
Peak memory 210124 kb
Host smart-4e2c06c0-883f-41b3-90f5-3c92f4565d73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503824672 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3503824672
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2730415455
Short name T471
Test name
Test status
Simulation time 481491923 ps
CPU time 0.78 seconds
Started Feb 18 01:20:59 PM PST 24
Finished Feb 18 01:21:00 PM PST 24
Peak memory 201160 kb
Host smart-3ec86124-1fca-48b8-95bd-a6bc034eb4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730415455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2730415455
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.983124926
Short name T180
Test name
Test status
Simulation time 489006889575 ps
CPU time 96.67 seconds
Started Feb 18 01:20:53 PM PST 24
Finished Feb 18 01:22:31 PM PST 24
Peak memory 201484 kb
Host smart-29c42933-4f3c-463b-b058-120863948c55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983124926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.983124926
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1090564780
Short name T603
Test name
Test status
Simulation time 321095936212 ps
CPU time 206.83 seconds
Started Feb 18 01:20:49 PM PST 24
Finished Feb 18 01:24:16 PM PST 24
Peak memory 201524 kb
Host smart-11493e17-1f38-4123-b555-a78cd3caed8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090564780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1090564780
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3931936277
Short name T276
Test name
Test status
Simulation time 162210584592 ps
CPU time 92.23 seconds
Started Feb 18 01:20:41 PM PST 24
Finished Feb 18 01:22:15 PM PST 24
Peak memory 201376 kb
Host smart-b5a97cef-3e56-4ecb-ab92-d2ef70242c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931936277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3931936277
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1005640411
Short name T510
Test name
Test status
Simulation time 167964867457 ps
CPU time 194.4 seconds
Started Feb 18 01:20:39 PM PST 24
Finished Feb 18 01:23:55 PM PST 24
Peak memory 201436 kb
Host smart-fa67607d-95eb-4d85-af3e-6d497c0a3f23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005640411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1005640411
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1623586600
Short name T523
Test name
Test status
Simulation time 335052222284 ps
CPU time 288.9 seconds
Started Feb 18 01:20:53 PM PST 24
Finished Feb 18 01:25:44 PM PST 24
Peak memory 201432 kb
Host smart-130f490e-c8a4-41fe-8ddf-ff17bd476350
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623586600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1623586600
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1168727966
Short name T9
Test name
Test status
Simulation time 169828921718 ps
CPU time 86.76 seconds
Started Feb 18 01:20:49 PM PST 24
Finished Feb 18 01:22:17 PM PST 24
Peak memory 201508 kb
Host smart-0a5bf259-0e9d-4857-b94f-a02e7bdcb47d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168727966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1168727966
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.57337444
Short name T10
Test name
Test status
Simulation time 77044570064 ps
CPU time 268.84 seconds
Started Feb 18 01:20:58 PM PST 24
Finished Feb 18 01:25:28 PM PST 24
Peak memory 201740 kb
Host smart-284a170d-9ae2-41f7-bf9d-c8e1c2a7c29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57337444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.57337444
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3264191560
Short name T527
Test name
Test status
Simulation time 36412258592 ps
CPU time 77.2 seconds
Started Feb 18 01:21:00 PM PST 24
Finished Feb 18 01:22:17 PM PST 24
Peak memory 201144 kb
Host smart-cb415f56-eeab-41ca-b3ec-738b1f03b061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264191560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3264191560
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.854892617
Short name T615
Test name
Test status
Simulation time 5182001947 ps
CPU time 3.4 seconds
Started Feb 18 01:20:59 PM PST 24
Finished Feb 18 01:21:03 PM PST 24
Peak memory 201244 kb
Host smart-d1a2257c-d1af-441f-92fd-1e934db2a576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854892617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.854892617
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3512991031
Short name T379
Test name
Test status
Simulation time 5884946953 ps
CPU time 13.02 seconds
Started Feb 18 01:20:41 PM PST 24
Finished Feb 18 01:20:55 PM PST 24
Peak memory 201188 kb
Host smart-b85fff48-73b3-407b-a9f8-f0a2be49f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512991031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3512991031
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3762996943
Short name T206
Test name
Test status
Simulation time 256275981031 ps
CPU time 544.42 seconds
Started Feb 18 01:20:58 PM PST 24
Finished Feb 18 01:30:03 PM PST 24
Peak memory 210000 kb
Host smart-e0d58c3a-bf8d-4baf-be91-a95f9956998a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762996943 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3762996943
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2775505639
Short name T587
Test name
Test status
Simulation time 367438332 ps
CPU time 0.75 seconds
Started Feb 18 01:21:02 PM PST 24
Finished Feb 18 01:21:03 PM PST 24
Peak memory 201184 kb
Host smart-8ff69e33-1ea0-4cb4-846d-c4d07f85a05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775505639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2775505639
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3568628623
Short name T745
Test name
Test status
Simulation time 162701001782 ps
CPU time 94.59 seconds
Started Feb 18 01:20:58 PM PST 24
Finished Feb 18 01:22:33 PM PST 24
Peak memory 201448 kb
Host smart-6ecdafdb-148c-43c3-a056-757329b56d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568628623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3568628623
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3746251373
Short name T390
Test name
Test status
Simulation time 487376500265 ps
CPU time 74.95 seconds
Started Feb 18 01:21:05 PM PST 24
Finished Feb 18 01:22:22 PM PST 24
Peak memory 201392 kb
Host smart-ff8d7e50-a7f8-405c-8683-9047e82371f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746251373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3746251373
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3179827698
Short name T435
Test name
Test status
Simulation time 161429793823 ps
CPU time 387.24 seconds
Started Feb 18 01:21:00 PM PST 24
Finished Feb 18 01:27:28 PM PST 24
Peak memory 201456 kb
Host smart-a44285ee-b24e-4670-b18f-77bd6c71d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179827698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3179827698
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2641945447
Short name T460
Test name
Test status
Simulation time 326557412809 ps
CPU time 232.59 seconds
Started Feb 18 01:20:57 PM PST 24
Finished Feb 18 01:24:51 PM PST 24
Peak memory 201476 kb
Host smart-cc32cdd4-d75d-4f01-8e28-9a242f0b8153
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641945447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2641945447
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3215871403
Short name T747
Test name
Test status
Simulation time 167159434068 ps
CPU time 362.24 seconds
Started Feb 18 01:21:04 PM PST 24
Finished Feb 18 01:27:08 PM PST 24
Peak memory 201516 kb
Host smart-6608584c-4143-4ba7-99c0-ffc6302296da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215871403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3215871403
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1608557268
Short name T488
Test name
Test status
Simulation time 483562657753 ps
CPU time 511.28 seconds
Started Feb 18 01:21:07 PM PST 24
Finished Feb 18 01:29:39 PM PST 24
Peak memory 201464 kb
Host smart-07c21522-f42f-43f7-8b72-642a96404f10
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608557268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1608557268
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.45450892
Short name T597
Test name
Test status
Simulation time 123432754537 ps
CPU time 644.24 seconds
Started Feb 18 01:21:10 PM PST 24
Finished Feb 18 01:31:55 PM PST 24
Peak memory 201724 kb
Host smart-730e9205-ffc4-4b99-ad67-c7faf383298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45450892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.45450892
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2308060867
Short name T367
Test name
Test status
Simulation time 35537163239 ps
CPU time 79.88 seconds
Started Feb 18 01:21:08 PM PST 24
Finished Feb 18 01:22:29 PM PST 24
Peak memory 201224 kb
Host smart-fa459387-1bfe-4035-9eae-f7cf9282cb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308060867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2308060867
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3613733723
Short name T738
Test name
Test status
Simulation time 4465526117 ps
CPU time 5.9 seconds
Started Feb 18 01:21:07 PM PST 24
Finished Feb 18 01:21:14 PM PST 24
Peak memory 201228 kb
Host smart-dd535323-f589-466a-8522-e304eb10b0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613733723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3613733723
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1619000605
Short name T545
Test name
Test status
Simulation time 6018458276 ps
CPU time 14.8 seconds
Started Feb 18 01:20:59 PM PST 24
Finished Feb 18 01:21:14 PM PST 24
Peak memory 201212 kb
Host smart-7b13e98e-6db0-4aca-bac8-1031a94bcf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619000605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1619000605
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.687139039
Short name T342
Test name
Test status
Simulation time 328969867207 ps
CPU time 386.41 seconds
Started Feb 18 01:21:06 PM PST 24
Finished Feb 18 01:27:34 PM PST 24
Peak memory 201408 kb
Host smart-ca9d47e1-12bb-49f7-9565-6b1c8c7bcf84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687139039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
687139039
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1244969114
Short name T610
Test name
Test status
Simulation time 403686352 ps
CPU time 0.83 seconds
Started Feb 18 01:15:14 PM PST 24
Finished Feb 18 01:15:16 PM PST 24
Peak memory 201164 kb
Host smart-1fc3b4f0-8110-4c63-9889-f1d134accc78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244969114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1244969114
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3157133535
Short name T474
Test name
Test status
Simulation time 169674262215 ps
CPU time 412.9 seconds
Started Feb 18 01:15:02 PM PST 24
Finished Feb 18 01:21:59 PM PST 24
Peak memory 201528 kb
Host smart-30d02291-af5f-45e9-9517-27d872a3d5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157133535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3157133535
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3873082218
Short name T667
Test name
Test status
Simulation time 486038583789 ps
CPU time 529.6 seconds
Started Feb 18 01:15:02 PM PST 24
Finished Feb 18 01:23:55 PM PST 24
Peak memory 201264 kb
Host smart-b34ff0e0-559e-42eb-a7b2-571f998b57b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873082218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3873082218
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4088467213
Short name T452
Test name
Test status
Simulation time 161780422387 ps
CPU time 335.01 seconds
Started Feb 18 01:14:58 PM PST 24
Finished Feb 18 01:20:35 PM PST 24
Peak memory 201424 kb
Host smart-4c870f29-347d-4221-88c4-0635761d364f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088467213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4088467213
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.535248870
Short name T451
Test name
Test status
Simulation time 161084311627 ps
CPU time 363.74 seconds
Started Feb 18 01:15:05 PM PST 24
Finished Feb 18 01:21:11 PM PST 24
Peak memory 201484 kb
Host smart-679dd4c1-26a5-4437-8472-78fa4c4a5e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535248870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.535248870
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.546962118
Short name T90
Test name
Test status
Simulation time 501179007409 ps
CPU time 363.96 seconds
Started Feb 18 01:15:06 PM PST 24
Finished Feb 18 01:21:12 PM PST 24
Peak memory 201460 kb
Host smart-490e3f44-39b1-4db6-8436-64397891b545
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=546962118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.546962118
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.332935801
Short name T775
Test name
Test status
Simulation time 166765077517 ps
CPU time 65.16 seconds
Started Feb 18 01:15:06 PM PST 24
Finished Feb 18 01:16:13 PM PST 24
Peak memory 201400 kb
Host smart-2c8a68c4-dce6-476d-b1cc-190a6340bdc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332935801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.332935801
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2178363328
Short name T514
Test name
Test status
Simulation time 487024202207 ps
CPU time 283.5 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:19:52 PM PST 24
Peak memory 201372 kb
Host smart-95be8af1-c746-45aa-b3bf-16cdca775fd3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178363328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2178363328
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2740441044
Short name T359
Test name
Test status
Simulation time 117404917973 ps
CPU time 656.26 seconds
Started Feb 18 01:15:02 PM PST 24
Finished Feb 18 01:26:02 PM PST 24
Peak memory 201772 kb
Host smart-c091f7a4-aedd-46d5-8351-6f89d3bb4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740441044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2740441044
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2767716755
Short name T4
Test name
Test status
Simulation time 38470179402 ps
CPU time 27.1 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:15:42 PM PST 24
Peak memory 201220 kb
Host smart-8bd112bf-cfab-4a39-adea-90f654e362e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767716755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2767716755
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.946873606
Short name T84
Test name
Test status
Simulation time 3904347373 ps
CPU time 2.7 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:15:11 PM PST 24
Peak memory 201220 kb
Host smart-1788e2de-defe-4821-8ba5-e4f53fc26581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946873606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.946873606
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3960937637
Short name T48
Test name
Test status
Simulation time 8466108020 ps
CPU time 5.89 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:15:15 PM PST 24
Peak memory 216412 kb
Host smart-ab47c02b-51dd-43a0-b181-52441b31bc7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960937637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3960937637
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2137487837
Short name T557
Test name
Test status
Simulation time 5485423558 ps
CPU time 12.58 seconds
Started Feb 18 01:15:06 PM PST 24
Finished Feb 18 01:15:20 PM PST 24
Peak memory 201220 kb
Host smart-df8c15bc-29fa-4427-8b21-e95ccdfefb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137487837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2137487837
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1801535952
Short name T366
Test name
Test status
Simulation time 5770102713 ps
CPU time 7.54 seconds
Started Feb 18 01:15:05 PM PST 24
Finished Feb 18 01:15:15 PM PST 24
Peak memory 201160 kb
Host smart-5ef5183e-e3ee-45e2-86fd-e31bfdbbd814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801535952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1801535952
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2823048075
Short name T791
Test name
Test status
Simulation time 297645442344 ps
CPU time 314.88 seconds
Started Feb 18 01:15:02 PM PST 24
Finished Feb 18 01:20:20 PM PST 24
Peak memory 210084 kb
Host smart-751c2d4d-28fa-48af-9491-8f9a593b6a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823048075 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2823048075
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.329192751
Short name T42
Test name
Test status
Simulation time 354241376 ps
CPU time 0.82 seconds
Started Feb 18 01:21:17 PM PST 24
Finished Feb 18 01:21:19 PM PST 24
Peak memory 201148 kb
Host smart-72db445a-695c-422c-b6b2-999bf18fe791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329192751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.329192751
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.928068669
Short name T94
Test name
Test status
Simulation time 165876699326 ps
CPU time 200.64 seconds
Started Feb 18 01:21:10 PM PST 24
Finished Feb 18 01:24:32 PM PST 24
Peak memory 201476 kb
Host smart-d0180fbe-ba8a-4550-8c22-40acb1a5eac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928068669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.928068669
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2548481440
Short name T602
Test name
Test status
Simulation time 162845274419 ps
CPU time 105.15 seconds
Started Feb 18 01:21:11 PM PST 24
Finished Feb 18 01:22:57 PM PST 24
Peak memory 201524 kb
Host smart-a555a2e9-00f0-49d6-a2b0-7e47869de661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548481440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2548481440
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3121802634
Short name T750
Test name
Test status
Simulation time 333590447547 ps
CPU time 767.09 seconds
Started Feb 18 01:21:08 PM PST 24
Finished Feb 18 01:33:57 PM PST 24
Peak memory 201424 kb
Host smart-dfe30307-2a5a-419d-b110-204be74d8d7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121802634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3121802634
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3726437364
Short name T416
Test name
Test status
Simulation time 164229539806 ps
CPU time 360.23 seconds
Started Feb 18 01:21:11 PM PST 24
Finished Feb 18 01:27:12 PM PST 24
Peak memory 201336 kb
Host smart-45d323e4-a9ad-403a-88f6-3e5e2ccb6a3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726437364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3726437364
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.353556114
Short name T709
Test name
Test status
Simulation time 488099885559 ps
CPU time 1143.59 seconds
Started Feb 18 01:21:10 PM PST 24
Finished Feb 18 01:40:15 PM PST 24
Peak memory 201480 kb
Host smart-fe76b428-f171-4df5-9c46-82e1e267361b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353556114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.353556114
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4159742274
Short name T385
Test name
Test status
Simulation time 489772713924 ps
CPU time 103.49 seconds
Started Feb 18 01:21:11 PM PST 24
Finished Feb 18 01:22:55 PM PST 24
Peak memory 201508 kb
Host smart-3ccd160c-9012-42f7-8e9d-df3cc149e1a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159742274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4159742274
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2146983754
Short name T689
Test name
Test status
Simulation time 137464748111 ps
CPU time 602.9 seconds
Started Feb 18 01:21:21 PM PST 24
Finished Feb 18 01:31:25 PM PST 24
Peak memory 201824 kb
Host smart-09383c7e-b342-4754-bab7-9cf3a2a732ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146983754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2146983754
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4163702682
Short name T715
Test name
Test status
Simulation time 27936485237 ps
CPU time 60.33 seconds
Started Feb 18 01:21:11 PM PST 24
Finished Feb 18 01:22:12 PM PST 24
Peak memory 201144 kb
Host smart-ab99b6c0-06bf-4ef5-a675-2d9f8f2e06a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163702682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4163702682
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3297784531
Short name T89
Test name
Test status
Simulation time 3605905163 ps
CPU time 4.77 seconds
Started Feb 18 01:21:12 PM PST 24
Finished Feb 18 01:21:17 PM PST 24
Peak memory 201220 kb
Host smart-0a00e481-3bcd-4b43-9e28-d357a43f91e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297784531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3297784531
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3263825068
Short name T658
Test name
Test status
Simulation time 6052917096 ps
CPU time 4.28 seconds
Started Feb 18 01:21:01 PM PST 24
Finished Feb 18 01:21:06 PM PST 24
Peak memory 201172 kb
Host smart-3c0cb421-7ff0-4d39-bc96-82c20f3ca4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263825068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3263825068
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.4067126303
Short name T382
Test name
Test status
Simulation time 476842555 ps
CPU time 0.88 seconds
Started Feb 18 01:21:29 PM PST 24
Finished Feb 18 01:21:31 PM PST 24
Peak memory 201116 kb
Host smart-3cf69a66-0a2c-46fc-8acc-0dd48d41eedb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067126303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.4067126303
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1043100223
Short name T14
Test name
Test status
Simulation time 330695749458 ps
CPU time 773.93 seconds
Started Feb 18 01:21:18 PM PST 24
Finished Feb 18 01:34:13 PM PST 24
Peak memory 201472 kb
Host smart-ff75870d-9336-446f-b236-6d80933cc3b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043100223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1043100223
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1772893927
Short name T153
Test name
Test status
Simulation time 324392555784 ps
CPU time 126.43 seconds
Started Feb 18 01:21:19 PM PST 24
Finished Feb 18 01:23:26 PM PST 24
Peak memory 201468 kb
Host smart-7356cfb1-e3d8-4e07-bc2e-5dd6d3964e7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772893927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1772893927
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2062832687
Short name T313
Test name
Test status
Simulation time 329054095704 ps
CPU time 179.11 seconds
Started Feb 18 01:21:18 PM PST 24
Finished Feb 18 01:24:17 PM PST 24
Peak memory 201392 kb
Host smart-221cc037-a801-4d45-80fe-efd1e8a6427c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062832687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2062832687
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1832185024
Short name T609
Test name
Test status
Simulation time 162221179283 ps
CPU time 51 seconds
Started Feb 18 01:21:19 PM PST 24
Finished Feb 18 01:22:10 PM PST 24
Peak memory 201424 kb
Host smart-077c8106-5e08-4183-aaba-861d0bbb675f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832185024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1832185024
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2200378502
Short name T134
Test name
Test status
Simulation time 330384020642 ps
CPU time 124.65 seconds
Started Feb 18 01:21:19 PM PST 24
Finished Feb 18 01:23:24 PM PST 24
Peak memory 201452 kb
Host smart-339c0674-39ef-4353-b07c-cfdc202c5185
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200378502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2200378502
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.751795132
Short name T589
Test name
Test status
Simulation time 496527077939 ps
CPU time 1207.38 seconds
Started Feb 18 01:21:18 PM PST 24
Finished Feb 18 01:41:26 PM PST 24
Peak memory 201468 kb
Host smart-4215da43-4de4-493c-8f1f-64996b23a8ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751795132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.751795132
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2387890319
Short name T224
Test name
Test status
Simulation time 138829144607 ps
CPU time 440.51 seconds
Started Feb 18 01:21:18 PM PST 24
Finished Feb 18 01:28:39 PM PST 24
Peak memory 201784 kb
Host smart-879255c7-72cf-476a-8f00-9e533abf62b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387890319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2387890319
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3967553127
Short name T668
Test name
Test status
Simulation time 24852024555 ps
CPU time 10.75 seconds
Started Feb 18 01:21:19 PM PST 24
Finished Feb 18 01:21:30 PM PST 24
Peak memory 201204 kb
Host smart-83f3b793-13ce-441d-8d58-0112896a2250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967553127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3967553127
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2864950459
Short name T456
Test name
Test status
Simulation time 3629729425 ps
CPU time 2.8 seconds
Started Feb 18 01:21:18 PM PST 24
Finished Feb 18 01:21:22 PM PST 24
Peak memory 201224 kb
Host smart-67edc089-a114-4399-8447-7f55942a2082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864950459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2864950459
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.240545240
Short name T459
Test name
Test status
Simulation time 5824281248 ps
CPU time 3.43 seconds
Started Feb 18 01:21:23 PM PST 24
Finished Feb 18 01:21:28 PM PST 24
Peak memory 200940 kb
Host smart-c5d81077-02a7-4e43-9edc-65cfc6b9b181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240545240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.240545240
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1767291264
Short name T212
Test name
Test status
Simulation time 298781505871 ps
CPU time 1047.82 seconds
Started Feb 18 01:21:29 PM PST 24
Finished Feb 18 01:38:58 PM PST 24
Peak memory 212056 kb
Host smart-a3ad57fa-df88-43ab-8898-0e9c5a36632d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767291264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1767291264
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2558006015
Short name T315
Test name
Test status
Simulation time 78088198580 ps
CPU time 82.73 seconds
Started Feb 18 01:21:28 PM PST 24
Finished Feb 18 01:22:52 PM PST 24
Peak memory 210088 kb
Host smart-e1d7d3b7-d2a3-4dcb-b863-b4f5ba5d03e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558006015 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2558006015
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.697178640
Short name T617
Test name
Test status
Simulation time 348358477 ps
CPU time 0.64 seconds
Started Feb 18 01:21:34 PM PST 24
Finished Feb 18 01:21:36 PM PST 24
Peak memory 201168 kb
Host smart-2f0d2a84-7170-4764-813b-47ae096ba427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697178640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.697178640
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2725106918
Short name T314
Test name
Test status
Simulation time 164660228359 ps
CPU time 79.05 seconds
Started Feb 18 01:21:29 PM PST 24
Finished Feb 18 01:22:49 PM PST 24
Peak memory 201376 kb
Host smart-2937fd0e-a856-4212-94c7-0aba34fe63e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725106918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2725106918
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3841277270
Short name T175
Test name
Test status
Simulation time 331547735132 ps
CPU time 47.82 seconds
Started Feb 18 01:21:30 PM PST 24
Finished Feb 18 01:22:19 PM PST 24
Peak memory 201532 kb
Host smart-908b4c46-e729-4cc8-83bb-4cce1ea3e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841277270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3841277270
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.353896900
Short name T746
Test name
Test status
Simulation time 163791738651 ps
CPU time 99.38 seconds
Started Feb 18 01:21:30 PM PST 24
Finished Feb 18 01:23:10 PM PST 24
Peak memory 201400 kb
Host smart-126b85df-6a9c-41fb-892b-d1ff7e0cc24e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=353896900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.353896900
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2328909216
Short name T138
Test name
Test status
Simulation time 501661170733 ps
CPU time 618.49 seconds
Started Feb 18 01:21:30 PM PST 24
Finished Feb 18 01:31:49 PM PST 24
Peak memory 201504 kb
Host smart-6dbe0e34-717c-4c07-af8f-4799893513e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328909216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2328909216
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2173810998
Short name T141
Test name
Test status
Simulation time 161231020284 ps
CPU time 184.56 seconds
Started Feb 18 01:21:30 PM PST 24
Finished Feb 18 01:24:35 PM PST 24
Peak memory 201440 kb
Host smart-4e7aeae9-8ea8-42e1-aba7-4ac31a46ed79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173810998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2173810998
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3811470576
Short name T245
Test name
Test status
Simulation time 490823787794 ps
CPU time 270.05 seconds
Started Feb 18 01:21:29 PM PST 24
Finished Feb 18 01:26:00 PM PST 24
Peak memory 201388 kb
Host smart-b8eafa06-e393-4f5e-a1b3-b516cc149980
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811470576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3811470576
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3208563788
Short name T363
Test name
Test status
Simulation time 325403705174 ps
CPU time 809.87 seconds
Started Feb 18 01:21:29 PM PST 24
Finished Feb 18 01:35:00 PM PST 24
Peak memory 201468 kb
Host smart-d823c3af-1d64-4249-b6c7-7a271808f498
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208563788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3208563788
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1542240269
Short name T357
Test name
Test status
Simulation time 131312242427 ps
CPU time 451.44 seconds
Started Feb 18 01:21:36 PM PST 24
Finished Feb 18 01:29:08 PM PST 24
Peak memory 201724 kb
Host smart-f85f9735-fec5-4cd9-985c-842a886e2a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542240269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1542240269
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3100144351
Short name T437
Test name
Test status
Simulation time 44800321259 ps
CPU time 94.21 seconds
Started Feb 18 01:21:30 PM PST 24
Finished Feb 18 01:23:05 PM PST 24
Peak memory 201232 kb
Host smart-a12937d3-3e26-4724-925e-66c991f7b826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100144351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3100144351
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3086808496
Short name T398
Test name
Test status
Simulation time 5779726654 ps
CPU time 2.69 seconds
Started Feb 18 01:21:28 PM PST 24
Finished Feb 18 01:21:32 PM PST 24
Peak memory 201232 kb
Host smart-94009db6-1407-4a9c-bdd4-6f0ab766a64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086808496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3086808496
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.996348811
Short name T431
Test name
Test status
Simulation time 6191787205 ps
CPU time 3.38 seconds
Started Feb 18 01:21:35 PM PST 24
Finished Feb 18 01:21:39 PM PST 24
Peak memory 201228 kb
Host smart-2a1396c6-a7d9-4126-bd94-07b4e4c5344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996348811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.996348811
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3779364752
Short name T301
Test name
Test status
Simulation time 345398280402 ps
CPU time 222.62 seconds
Started Feb 18 01:21:32 PM PST 24
Finished Feb 18 01:25:15 PM PST 24
Peak memory 201460 kb
Host smart-e6135109-668d-471b-9d3e-f3c4d2415485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779364752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3779364752
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2029311227
Short name T26
Test name
Test status
Simulation time 115426730108 ps
CPU time 195.41 seconds
Started Feb 18 01:21:33 PM PST 24
Finished Feb 18 01:24:48 PM PST 24
Peak memory 217324 kb
Host smart-ecf4331b-a94e-4503-b125-ac5258615398
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029311227 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2029311227
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.478618580
Short name T52
Test name
Test status
Simulation time 307568469 ps
CPU time 0.84 seconds
Started Feb 18 01:21:48 PM PST 24
Finished Feb 18 01:21:49 PM PST 24
Peak memory 201044 kb
Host smart-48d409ac-f618-4240-bbf1-0c7ff511b7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478618580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.478618580
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2751193070
Short name T633
Test name
Test status
Simulation time 165132555419 ps
CPU time 375.93 seconds
Started Feb 18 01:21:48 PM PST 24
Finished Feb 18 01:28:05 PM PST 24
Peak memory 201444 kb
Host smart-1842ac0c-a134-455e-bd78-5132cafc919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751193070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2751193070
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.4078973556
Short name T241
Test name
Test status
Simulation time 161730100389 ps
CPU time 97.59 seconds
Started Feb 18 01:21:35 PM PST 24
Finished Feb 18 01:23:14 PM PST 24
Peak memory 201496 kb
Host smart-411b6e7a-8615-4f92-a7e7-93a91c499618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078973556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.4078973556
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1149916239
Short name T372
Test name
Test status
Simulation time 164746211194 ps
CPU time 93.21 seconds
Started Feb 18 01:21:36 PM PST 24
Finished Feb 18 01:23:10 PM PST 24
Peak memory 201364 kb
Host smart-074f0278-158b-4a82-a437-6b6bc9d22b3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149916239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1149916239
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.339823710
Short name T323
Test name
Test status
Simulation time 491601338476 ps
CPU time 263.25 seconds
Started Feb 18 01:21:33 PM PST 24
Finished Feb 18 01:25:57 PM PST 24
Peak memory 201492 kb
Host smart-3bfa6cf4-e79f-4752-91f3-eb1d3d140f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339823710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.339823710
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2844022253
Short name T574
Test name
Test status
Simulation time 489936350142 ps
CPU time 1130.23 seconds
Started Feb 18 01:21:33 PM PST 24
Finished Feb 18 01:40:24 PM PST 24
Peak memory 201424 kb
Host smart-27869516-e760-481d-9b82-0823a4671100
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844022253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2844022253
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1653021189
Short name T726
Test name
Test status
Simulation time 168266625434 ps
CPU time 377.01 seconds
Started Feb 18 01:21:48 PM PST 24
Finished Feb 18 01:28:06 PM PST 24
Peak memory 201428 kb
Host smart-07691164-2a5d-40e2-8ce4-0fa18b3ff147
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653021189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1653021189
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.756170275
Short name T774
Test name
Test status
Simulation time 170844381066 ps
CPU time 407.15 seconds
Started Feb 18 01:21:47 PM PST 24
Finished Feb 18 01:28:35 PM PST 24
Peak memory 201528 kb
Host smart-bdd7a9ac-e84b-424a-ad74-c30ac10ecc51
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756170275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.756170275
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2678353271
Short name T209
Test name
Test status
Simulation time 107203709358 ps
CPU time 577.72 seconds
Started Feb 18 01:21:46 PM PST 24
Finished Feb 18 01:31:24 PM PST 24
Peak memory 201752 kb
Host smart-0d588414-93dc-4634-9084-fd2f5c277684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678353271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2678353271
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.136441095
Short name T417
Test name
Test status
Simulation time 36477458885 ps
CPU time 85.45 seconds
Started Feb 18 01:21:49 PM PST 24
Finished Feb 18 01:23:16 PM PST 24
Peak memory 201236 kb
Host smart-96758933-69ae-4b70-b06d-2bbb89f7a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136441095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.136441095
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3723183647
Short name T194
Test name
Test status
Simulation time 2845996565 ps
CPU time 7.21 seconds
Started Feb 18 01:21:47 PM PST 24
Finished Feb 18 01:21:54 PM PST 24
Peak memory 201220 kb
Host smart-2e57e575-0f8f-4d85-8161-b020362c3448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723183647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3723183647
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1633646764
Short name T121
Test name
Test status
Simulation time 5591818832 ps
CPU time 14.17 seconds
Started Feb 18 01:21:35 PM PST 24
Finished Feb 18 01:21:50 PM PST 24
Peak memory 201172 kb
Host smart-7ada042e-84f9-49ac-bb94-019a44706aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633646764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1633646764
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2009234893
Short name T521
Test name
Test status
Simulation time 204064142314 ps
CPU time 435.92 seconds
Started Feb 18 01:21:47 PM PST 24
Finished Feb 18 01:29:03 PM PST 24
Peak memory 201396 kb
Host smart-5c390f42-ba3f-4d42-9536-bc02c42750a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009234893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2009234893
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.938562147
Short name T441
Test name
Test status
Simulation time 99429923604 ps
CPU time 186.75 seconds
Started Feb 18 01:21:48 PM PST 24
Finished Feb 18 01:24:55 PM PST 24
Peak memory 218232 kb
Host smart-b57dfcfa-f8e2-4a23-835c-dd439ba625cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938562147 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.938562147
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1751817529
Short name T520
Test name
Test status
Simulation time 487358064 ps
CPU time 1.08 seconds
Started Feb 18 01:21:52 PM PST 24
Finished Feb 18 01:21:54 PM PST 24
Peak memory 201152 kb
Host smart-57f9d473-d216-4830-9e5c-a392d42aa15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751817529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1751817529
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1177326494
Short name T202
Test name
Test status
Simulation time 158985782647 ps
CPU time 380.5 seconds
Started Feb 18 01:22:00 PM PST 24
Finished Feb 18 01:28:22 PM PST 24
Peak memory 201448 kb
Host smart-fa849cd9-5e62-4b98-96d5-3df2c63befdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177326494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1177326494
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.67595771
Short name T237
Test name
Test status
Simulation time 489985259222 ps
CPU time 1255.48 seconds
Started Feb 18 01:22:00 PM PST 24
Finished Feb 18 01:42:56 PM PST 24
Peak memory 201524 kb
Host smart-df8f035a-a998-4f7a-bef4-aad2f391039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67595771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.67595771
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1012307355
Short name T532
Test name
Test status
Simulation time 156865404900 ps
CPU time 366.66 seconds
Started Feb 18 01:22:00 PM PST 24
Finished Feb 18 01:28:07 PM PST 24
Peak memory 201340 kb
Host smart-e5935629-90d2-4988-bde2-ac09ce34bb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012307355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1012307355
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3905143778
Short name T477
Test name
Test status
Simulation time 330922423597 ps
CPU time 385.39 seconds
Started Feb 18 01:22:01 PM PST 24
Finished Feb 18 01:28:27 PM PST 24
Peak memory 201472 kb
Host smart-b9ffd079-bbcb-4d7e-85d1-d81917550efe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905143778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3905143778
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2224838861
Short name T428
Test name
Test status
Simulation time 328658241974 ps
CPU time 107.38 seconds
Started Feb 18 01:21:47 PM PST 24
Finished Feb 18 01:23:35 PM PST 24
Peak memory 201440 kb
Host smart-ffa16501-cbf6-402d-950d-5049dbd37e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224838861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2224838861
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.773608382
Short name T502
Test name
Test status
Simulation time 163417079405 ps
CPU time 394.23 seconds
Started Feb 18 01:22:02 PM PST 24
Finished Feb 18 01:28:37 PM PST 24
Peak memory 201452 kb
Host smart-93ece9e3-ab60-42d1-b81f-c3639777f5a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=773608382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.773608382
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2053478142
Short name T247
Test name
Test status
Simulation time 326207986653 ps
CPU time 188.5 seconds
Started Feb 18 01:22:01 PM PST 24
Finished Feb 18 01:25:10 PM PST 24
Peak memory 201488 kb
Host smart-4628fa74-24bb-4a56-b817-2967027d9e8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053478142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2053478142
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1343407778
Short name T576
Test name
Test status
Simulation time 166144360776 ps
CPU time 191.57 seconds
Started Feb 18 01:21:54 PM PST 24
Finished Feb 18 01:25:07 PM PST 24
Peak memory 201468 kb
Host smart-7bbd96c6-73b8-44ef-b308-2b85d8af5422
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343407778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1343407778
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3575280909
Short name T731
Test name
Test status
Simulation time 108708002334 ps
CPU time 565.08 seconds
Started Feb 18 01:22:01 PM PST 24
Finished Feb 18 01:31:26 PM PST 24
Peak memory 201708 kb
Host smart-3d36bd52-9847-45bc-b048-3a467f5eb535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575280909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3575280909
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.994063617
Short name T679
Test name
Test status
Simulation time 29986923026 ps
CPU time 13.56 seconds
Started Feb 18 01:21:54 PM PST 24
Finished Feb 18 01:22:08 PM PST 24
Peak memory 201244 kb
Host smart-3ba51af4-9b3c-41ff-8afc-c65cad1b9ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994063617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.994063617
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2177842281
Short name T446
Test name
Test status
Simulation time 3068311755 ps
CPU time 1.14 seconds
Started Feb 18 01:22:03 PM PST 24
Finished Feb 18 01:22:05 PM PST 24
Peak memory 201208 kb
Host smart-8a400814-6e0f-4d22-8cb4-02e460a58666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177842281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2177842281
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1283382480
Short name T193
Test name
Test status
Simulation time 5910491525 ps
CPU time 12 seconds
Started Feb 18 01:21:49 PM PST 24
Finished Feb 18 01:22:02 PM PST 24
Peak memory 201188 kb
Host smart-29b26c0a-9a30-4261-bf9b-fffdc60ae62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283382480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1283382480
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3899236992
Short name T219
Test name
Test status
Simulation time 427603306939 ps
CPU time 800.43 seconds
Started Feb 18 01:22:01 PM PST 24
Finished Feb 18 01:35:22 PM PST 24
Peak memory 212652 kb
Host smart-3335a313-a296-49c3-aaf8-029f22c8ff24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899236992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3899236992
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1452777906
Short name T188
Test name
Test status
Simulation time 1157212280 ps
CPU time 3.18 seconds
Started Feb 18 01:21:53 PM PST 24
Finished Feb 18 01:21:57 PM PST 24
Peak memory 201280 kb
Host smart-820693aa-ac6a-4f43-8d05-17a04bdcfe80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452777906 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1452777906
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1314595293
Short name T711
Test name
Test status
Simulation time 489792813 ps
CPU time 1.21 seconds
Started Feb 18 01:22:06 PM PST 24
Finished Feb 18 01:22:09 PM PST 24
Peak memory 201144 kb
Host smart-93630a42-e9d7-49a2-99ab-5f0415b3f539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314595293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1314595293
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2854753092
Short name T127
Test name
Test status
Simulation time 167567762570 ps
CPU time 150.22 seconds
Started Feb 18 01:22:03 PM PST 24
Finished Feb 18 01:24:34 PM PST 24
Peak memory 201416 kb
Host smart-2feeaeee-08bf-4d6e-a9c5-5c264f89f008
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854753092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2854753092
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1975032347
Short name T254
Test name
Test status
Simulation time 495909169415 ps
CPU time 1184.05 seconds
Started Feb 18 01:22:06 PM PST 24
Finished Feb 18 01:41:53 PM PST 24
Peak memory 201516 kb
Host smart-bc1fc793-f758-4daf-b2c1-4513466f4b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975032347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1975032347
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.802349267
Short name T528
Test name
Test status
Simulation time 488358461075 ps
CPU time 88.72 seconds
Started Feb 18 01:22:01 PM PST 24
Finished Feb 18 01:23:31 PM PST 24
Peak memory 201424 kb
Host smart-430db2a6-c517-4cd0-a3bc-98f5e04b72f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802349267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.802349267
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.512498400
Short name T393
Test name
Test status
Simulation time 328137862797 ps
CPU time 766.61 seconds
Started Feb 18 01:22:01 PM PST 24
Finished Feb 18 01:34:49 PM PST 24
Peak memory 201416 kb
Host smart-0dbf5601-5285-4796-93fc-767dbeb0d2cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=512498400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.512498400
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.75976079
Short name T442
Test name
Test status
Simulation time 325102489634 ps
CPU time 203.75 seconds
Started Feb 18 01:22:00 PM PST 24
Finished Feb 18 01:25:24 PM PST 24
Peak memory 201468 kb
Host smart-32614151-0c18-43a8-a7fa-5666e251b626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75976079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.75976079
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1292778595
Short name T68
Test name
Test status
Simulation time 324916125213 ps
CPU time 150.15 seconds
Started Feb 18 01:22:00 PM PST 24
Finished Feb 18 01:24:32 PM PST 24
Peak memory 201392 kb
Host smart-282bb64d-a9b4-42eb-ae73-2c317ccb763d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292778595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1292778595
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2504905401
Short name T80
Test name
Test status
Simulation time 519769895392 ps
CPU time 594.4 seconds
Started Feb 18 01:21:59 PM PST 24
Finished Feb 18 01:31:55 PM PST 24
Peak memory 201228 kb
Host smart-79d82cda-eb63-49d9-8a51-e4077753a79d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504905401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2504905401
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1630743149
Short name T535
Test name
Test status
Simulation time 160446571872 ps
CPU time 31.17 seconds
Started Feb 18 01:22:06 PM PST 24
Finished Feb 18 01:22:39 PM PST 24
Peak memory 201424 kb
Host smart-6035b7a0-b56a-4678-b9a9-4a81645a0aec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630743149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1630743149
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.176865551
Short name T625
Test name
Test status
Simulation time 124314834140 ps
CPU time 629.97 seconds
Started Feb 18 01:22:05 PM PST 24
Finished Feb 18 01:32:35 PM PST 24
Peak memory 201700 kb
Host smart-1b3cb7d9-4fac-47c9-8ba2-575d65f90026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176865551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.176865551
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3718101295
Short name T482
Test name
Test status
Simulation time 30520888015 ps
CPU time 68.98 seconds
Started Feb 18 01:22:06 PM PST 24
Finished Feb 18 01:23:17 PM PST 24
Peak memory 201232 kb
Host smart-b341b949-21f9-43a9-a81b-e300c7eace7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718101295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3718101295
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1114532152
Short name T511
Test name
Test status
Simulation time 3469807078 ps
CPU time 8.2 seconds
Started Feb 18 01:22:06 PM PST 24
Finished Feb 18 01:22:17 PM PST 24
Peak memory 201232 kb
Host smart-a72c85c7-6e33-4217-bec9-e5791a64d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114532152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1114532152
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1090542739
Short name T494
Test name
Test status
Simulation time 5874021919 ps
CPU time 14.21 seconds
Started Feb 18 01:21:55 PM PST 24
Finished Feb 18 01:22:10 PM PST 24
Peak memory 201228 kb
Host smart-b71d45dc-f9bc-4c31-8fb9-2973824cdf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090542739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1090542739
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3702872547
Short name T551
Test name
Test status
Simulation time 174280397348 ps
CPU time 414.31 seconds
Started Feb 18 01:22:04 PM PST 24
Finished Feb 18 01:28:59 PM PST 24
Peak memory 201524 kb
Host smart-0ae7d93b-1403-40d0-958f-28f5d8d5a3c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702872547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3702872547
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1781261700
Short name T185
Test name
Test status
Simulation time 61300196023 ps
CPU time 104.71 seconds
Started Feb 18 01:22:06 PM PST 24
Finished Feb 18 01:23:53 PM PST 24
Peak memory 209804 kb
Host smart-570df20b-80f6-488c-abc9-a0bc7fa7ed08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781261700 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1781261700
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3099908962
Short name T542
Test name
Test status
Simulation time 384981398 ps
CPU time 1.06 seconds
Started Feb 18 01:22:33 PM PST 24
Finished Feb 18 01:22:35 PM PST 24
Peak memory 201140 kb
Host smart-f9ccec61-659a-4959-a792-2f61a43ed7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099908962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3099908962
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3039978534
Short name T570
Test name
Test status
Simulation time 327951201056 ps
CPU time 789.64 seconds
Started Feb 18 01:22:20 PM PST 24
Finished Feb 18 01:35:31 PM PST 24
Peak memory 201412 kb
Host smart-3bcac225-99d4-4b5a-ae81-cb8506e22d43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039978534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3039978534
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.372344373
Short name T269
Test name
Test status
Simulation time 172044229471 ps
CPU time 108.79 seconds
Started Feb 18 01:22:18 PM PST 24
Finished Feb 18 01:24:07 PM PST 24
Peak memory 201512 kb
Host smart-be2df176-86b3-4059-aa04-2f10b703f2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372344373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.372344373
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1279623263
Short name T413
Test name
Test status
Simulation time 169272655799 ps
CPU time 353.91 seconds
Started Feb 18 01:22:14 PM PST 24
Finished Feb 18 01:28:10 PM PST 24
Peak memory 201476 kb
Host smart-88b41e54-5d7f-4a48-a576-c16dc8b0b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279623263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1279623263
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.966797116
Short name T723
Test name
Test status
Simulation time 324896198250 ps
CPU time 780.89 seconds
Started Feb 18 01:22:11 PM PST 24
Finished Feb 18 01:35:13 PM PST 24
Peak memory 201444 kb
Host smart-53624fb5-64f1-4630-9706-30f422c6ab65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=966797116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.966797116
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1457595900
Short name T761
Test name
Test status
Simulation time 479148665060 ps
CPU time 1107.78 seconds
Started Feb 18 01:22:18 PM PST 24
Finished Feb 18 01:40:46 PM PST 24
Peak memory 201504 kb
Host smart-036abf32-f953-4ee0-90a3-c5546259f818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457595900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1457595900
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1408030810
Short name T401
Test name
Test status
Simulation time 163980130149 ps
CPU time 399.11 seconds
Started Feb 18 01:22:14 PM PST 24
Finished Feb 18 01:28:55 PM PST 24
Peak memory 201424 kb
Host smart-8f60de75-4a29-46a9-b368-741e3c5e27d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408030810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1408030810
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3144066357
Short name T481
Test name
Test status
Simulation time 504027375965 ps
CPU time 1226.24 seconds
Started Feb 18 01:22:15 PM PST 24
Finished Feb 18 01:42:43 PM PST 24
Peak memory 201408 kb
Host smart-498347b6-557e-4cb1-878c-0caf80f0820a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144066357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3144066357
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1613858154
Short name T457
Test name
Test status
Simulation time 115695870790 ps
CPU time 429.2 seconds
Started Feb 18 01:22:10 PM PST 24
Finished Feb 18 01:29:20 PM PST 24
Peak memory 201828 kb
Host smart-893b1ae4-4ce2-4ce6-b2b8-60b96bdc95ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613858154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1613858154
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1770039265
Short name T422
Test name
Test status
Simulation time 23296553052 ps
CPU time 13.62 seconds
Started Feb 18 01:22:19 PM PST 24
Finished Feb 18 01:22:33 PM PST 24
Peak memory 201100 kb
Host smart-7b438577-3eff-4330-96bb-374ebc22ca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770039265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1770039265
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2042759774
Short name T600
Test name
Test status
Simulation time 3321307149 ps
CPU time 8.9 seconds
Started Feb 18 01:22:19 PM PST 24
Finished Feb 18 01:22:29 PM PST 24
Peak memory 201220 kb
Host smart-e1bf4cee-4fec-4590-a770-59921b24b33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042759774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2042759774
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3607542542
Short name T593
Test name
Test status
Simulation time 5823430136 ps
CPU time 7.67 seconds
Started Feb 18 01:22:05 PM PST 24
Finished Feb 18 01:22:13 PM PST 24
Peak memory 201164 kb
Host smart-a480d520-0ac8-497a-97e9-a7a66506d535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607542542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3607542542
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3154838859
Short name T327
Test name
Test status
Simulation time 167808686318 ps
CPU time 194.76 seconds
Started Feb 18 01:22:17 PM PST 24
Finished Feb 18 01:25:33 PM PST 24
Peak memory 201420 kb
Host smart-83aef59c-2160-403b-b640-8211316768c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154838859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3154838859
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2437318341
Short name T41
Test name
Test status
Simulation time 433003439 ps
CPU time 1.61 seconds
Started Feb 18 01:22:37 PM PST 24
Finished Feb 18 01:22:40 PM PST 24
Peak memory 201128 kb
Host smart-11e7bc3e-3af3-49f0-8be2-538c24f87382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437318341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2437318341
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.308068131
Short name T311
Test name
Test status
Simulation time 166714044795 ps
CPU time 403.19 seconds
Started Feb 18 01:22:35 PM PST 24
Finished Feb 18 01:29:19 PM PST 24
Peak memory 201492 kb
Host smart-dd741995-8ee2-46ad-a993-50e938651279
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308068131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.308068131
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.663257073
Short name T176
Test name
Test status
Simulation time 330514556234 ps
CPU time 120.4 seconds
Started Feb 18 01:22:36 PM PST 24
Finished Feb 18 01:24:37 PM PST 24
Peak memory 201520 kb
Host smart-bd6024c7-3f69-4fd9-a326-2a36517addf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663257073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.663257073
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1630484404
Short name T530
Test name
Test status
Simulation time 476571363013 ps
CPU time 192.13 seconds
Started Feb 18 01:22:25 PM PST 24
Finished Feb 18 01:25:38 PM PST 24
Peak memory 201300 kb
Host smart-6efa491b-4040-422e-97b5-e7776d5d5182
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630484404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1630484404
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.410958231
Short name T273
Test name
Test status
Simulation time 157078125448 ps
CPU time 69.66 seconds
Started Feb 18 01:22:30 PM PST 24
Finished Feb 18 01:23:41 PM PST 24
Peak memory 201472 kb
Host smart-15b1a803-7c0e-4084-8a80-a7c5678d698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410958231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.410958231
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3452468368
Short name T559
Test name
Test status
Simulation time 165756948949 ps
CPU time 91.63 seconds
Started Feb 18 01:22:24 PM PST 24
Finished Feb 18 01:23:58 PM PST 24
Peak memory 201404 kb
Host smart-6c8baeca-2825-465a-8634-e0defabf0490
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452468368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3452468368
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3542142828
Short name T655
Test name
Test status
Simulation time 522955090393 ps
CPU time 298.47 seconds
Started Feb 18 01:22:23 PM PST 24
Finished Feb 18 01:27:23 PM PST 24
Peak memory 201500 kb
Host smart-80153aef-481b-429f-bbbc-30d45cb66be9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542142828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3542142828
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2795219083
Short name T572
Test name
Test status
Simulation time 165090003645 ps
CPU time 365.9 seconds
Started Feb 18 01:22:36 PM PST 24
Finished Feb 18 01:28:42 PM PST 24
Peak memory 201388 kb
Host smart-d1e908c6-6298-49d6-a0c7-81388bcaf529
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795219083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2795219083
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1834072342
Short name T608
Test name
Test status
Simulation time 113629014420 ps
CPU time 433.95 seconds
Started Feb 18 01:22:39 PM PST 24
Finished Feb 18 01:29:55 PM PST 24
Peak memory 201608 kb
Host smart-72fdc57b-e827-4cb0-9f8a-196076de1312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834072342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1834072342
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3623266641
Short name T550
Test name
Test status
Simulation time 23054037350 ps
CPU time 54.36 seconds
Started Feb 18 01:22:35 PM PST 24
Finished Feb 18 01:23:30 PM PST 24
Peak memory 201224 kb
Host smart-5c132cd2-d47e-42b0-8466-94789aa7c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623266641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3623266641
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2979122776
Short name T599
Test name
Test status
Simulation time 5628961710 ps
CPU time 4.72 seconds
Started Feb 18 01:22:35 PM PST 24
Finished Feb 18 01:22:40 PM PST 24
Peak memory 201168 kb
Host smart-5ba1d516-278a-4c5d-8920-c3fd4c72eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979122776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2979122776
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3675441131
Short name T688
Test name
Test status
Simulation time 6045450322 ps
CPU time 5.19 seconds
Started Feb 18 01:22:30 PM PST 24
Finished Feb 18 01:22:36 PM PST 24
Peak memory 201132 kb
Host smart-247147cc-9c1c-402d-9d7b-b4435bf9a4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675441131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3675441131
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1731841387
Short name T29
Test name
Test status
Simulation time 62624553065 ps
CPU time 297.01 seconds
Started Feb 18 01:22:37 PM PST 24
Finished Feb 18 01:27:35 PM PST 24
Peak memory 210060 kb
Host smart-9edb0d77-8378-4621-95fc-185252e0213b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731841387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1731841387
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1746910687
Short name T684
Test name
Test status
Simulation time 420945897 ps
CPU time 1.26 seconds
Started Feb 18 01:22:44 PM PST 24
Finished Feb 18 01:22:46 PM PST 24
Peak memory 201160 kb
Host smart-233b54ca-69e9-404f-8e3d-e060ad6c4f66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746910687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1746910687
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.628105149
Short name T336
Test name
Test status
Simulation time 163015562250 ps
CPU time 8.1 seconds
Started Feb 18 01:22:42 PM PST 24
Finished Feb 18 01:22:51 PM PST 24
Peak memory 201484 kb
Host smart-36898019-1574-462b-91d4-63144a211c19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628105149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.628105149
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1694593463
Short name T173
Test name
Test status
Simulation time 328596171576 ps
CPU time 191.33 seconds
Started Feb 18 01:22:44 PM PST 24
Finished Feb 18 01:25:56 PM PST 24
Peak memory 201392 kb
Host smart-b8b3ce26-6950-4080-bfd4-42a4163cb0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694593463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1694593463
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1831311858
Short name T295
Test name
Test status
Simulation time 322347054209 ps
CPU time 739.62 seconds
Started Feb 18 01:22:39 PM PST 24
Finished Feb 18 01:35:00 PM PST 24
Peak memory 201368 kb
Host smart-d063ad17-60c3-4161-adeb-50cfae086da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831311858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1831311858
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.380899018
Short name T555
Test name
Test status
Simulation time 168123999303 ps
CPU time 261.4 seconds
Started Feb 18 01:22:36 PM PST 24
Finished Feb 18 01:26:58 PM PST 24
Peak memory 201376 kb
Host smart-25ccab4d-485a-4edf-a518-cf2c1de7a81b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=380899018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.380899018
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1670926368
Short name T573
Test name
Test status
Simulation time 328953712102 ps
CPU time 523.98 seconds
Started Feb 18 01:22:30 PM PST 24
Finished Feb 18 01:31:14 PM PST 24
Peak memory 201492 kb
Host smart-7eafc5a0-8ea9-4619-9d70-0cf2d8eabd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670926368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1670926368
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3414217175
Short name T386
Test name
Test status
Simulation time 331445905281 ps
CPU time 184.1 seconds
Started Feb 18 01:22:37 PM PST 24
Finished Feb 18 01:25:42 PM PST 24
Peak memory 201508 kb
Host smart-e2020f09-98c4-47bf-bcbc-04c9dee6301a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414217175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3414217175
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3754783430
Short name T253
Test name
Test status
Simulation time 326528413105 ps
CPU time 154.02 seconds
Started Feb 18 01:22:36 PM PST 24
Finished Feb 18 01:25:11 PM PST 24
Peak memory 201532 kb
Host smart-1dc6af3b-d079-4ca2-a324-75f971c8fc7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754783430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3754783430
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4277727814
Short name T132
Test name
Test status
Simulation time 494178038761 ps
CPU time 313.35 seconds
Started Feb 18 01:22:34 PM PST 24
Finished Feb 18 01:27:48 PM PST 24
Peak memory 201452 kb
Host smart-790df68c-9878-4684-a4c7-6a0c5b59185b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277727814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.4277727814
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3923241760
Short name T666
Test name
Test status
Simulation time 39496740872 ps
CPU time 22.33 seconds
Started Feb 18 01:22:42 PM PST 24
Finished Feb 18 01:23:06 PM PST 24
Peak memory 201216 kb
Host smart-84198170-e683-419c-ae3b-f853613d71e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923241760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3923241760
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1248173560
Short name T467
Test name
Test status
Simulation time 3411221676 ps
CPU time 2.88 seconds
Started Feb 18 01:22:38 PM PST 24
Finished Feb 18 01:22:43 PM PST 24
Peak memory 201236 kb
Host smart-89fd38e5-079f-4bab-873d-52c42a835d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248173560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1248173560
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1446397597
Short name T748
Test name
Test status
Simulation time 5633219596 ps
CPU time 6.97 seconds
Started Feb 18 01:22:36 PM PST 24
Finished Feb 18 01:22:44 PM PST 24
Peak memory 201240 kb
Host smart-790dcd67-ecb9-451f-92e4-6a7c3f789f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446397597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1446397597
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3261720494
Short name T686
Test name
Test status
Simulation time 592456466537 ps
CPU time 2069.91 seconds
Started Feb 18 01:22:41 PM PST 24
Finished Feb 18 01:57:12 PM PST 24
Peak memory 201876 kb
Host smart-77c6c980-9fe8-46b2-94a5-e8be74e76fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261720494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3261720494
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.479550314
Short name T251
Test name
Test status
Simulation time 19729833272 ps
CPU time 24.42 seconds
Started Feb 18 01:22:41 PM PST 24
Finished Feb 18 01:23:07 PM PST 24
Peak memory 201628 kb
Host smart-1f2bfe00-f2ce-4ed6-8bfd-39f3087c872c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479550314 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.479550314
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3836637010
Short name T43
Test name
Test status
Simulation time 600513744 ps
CPU time 0.71 seconds
Started Feb 18 01:22:45 PM PST 24
Finished Feb 18 01:22:46 PM PST 24
Peak memory 201148 kb
Host smart-7d476034-fc6d-4b09-b619-577bdca29f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836637010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3836637010
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2165856226
Short name T230
Test name
Test status
Simulation time 325035934050 ps
CPU time 182.77 seconds
Started Feb 18 01:22:42 PM PST 24
Finished Feb 18 01:25:46 PM PST 24
Peak memory 201524 kb
Host smart-c4d0aa1f-290a-4d21-ac15-3c9a978db3a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165856226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2165856226
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.916468721
Short name T264
Test name
Test status
Simulation time 499121376208 ps
CPU time 287.17 seconds
Started Feb 18 01:22:45 PM PST 24
Finished Feb 18 01:27:33 PM PST 24
Peak memory 201428 kb
Host smart-6672d035-eeb2-41e8-9f9a-1695ed44f6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916468721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.916468721
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.4230294038
Short name T308
Test name
Test status
Simulation time 493317550840 ps
CPU time 1089.71 seconds
Started Feb 18 01:22:43 PM PST 24
Finished Feb 18 01:40:53 PM PST 24
Peak memory 201500 kb
Host smart-88cc6752-db7b-47a7-b7d3-5985f3688be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230294038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.4230294038
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1829229652
Short name T662
Test name
Test status
Simulation time 322790223406 ps
CPU time 762.03 seconds
Started Feb 18 01:22:44 PM PST 24
Finished Feb 18 01:35:27 PM PST 24
Peak memory 201416 kb
Host smart-ff9901f9-2062-4e36-8d5c-fdc7717d2b29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829229652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1829229652
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1469047634
Short name T150
Test name
Test status
Simulation time 324916090857 ps
CPU time 276.03 seconds
Started Feb 18 01:22:42 PM PST 24
Finished Feb 18 01:27:19 PM PST 24
Peak memory 201476 kb
Host smart-b8469369-dbdb-4760-b9ba-4f390579a40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469047634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1469047634
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3864255468
Short name T501
Test name
Test status
Simulation time 327411402958 ps
CPU time 368.28 seconds
Started Feb 18 01:22:42 PM PST 24
Finished Feb 18 01:28:51 PM PST 24
Peak memory 201424 kb
Host smart-45e6a986-d35b-41d8-966d-1869413dcd23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864255468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3864255468
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.208191162
Short name T149
Test name
Test status
Simulation time 158370743700 ps
CPU time 90.12 seconds
Started Feb 18 01:22:45 PM PST 24
Finished Feb 18 01:24:16 PM PST 24
Peak memory 201484 kb
Host smart-0c993426-03c4-41e9-b751-96d6be4a703a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208191162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.208191162
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1218657123
Short name T376
Test name
Test status
Simulation time 493699195935 ps
CPU time 555.49 seconds
Started Feb 18 01:22:38 PM PST 24
Finished Feb 18 01:31:55 PM PST 24
Peak memory 201512 kb
Host smart-c2eba2d7-f0d0-4f4d-8dce-91663c97df1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218657123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1218657123
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4089612356
Short name T717
Test name
Test status
Simulation time 140648189095 ps
CPU time 705.4 seconds
Started Feb 18 01:22:45 PM PST 24
Finished Feb 18 01:34:31 PM PST 24
Peak memory 201708 kb
Host smart-99a93d1d-1315-4801-b5ff-bc50114dbe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089612356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4089612356
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1405398078
Short name T72
Test name
Test status
Simulation time 42335893091 ps
CPU time 9.34 seconds
Started Feb 18 01:22:45 PM PST 24
Finished Feb 18 01:22:55 PM PST 24
Peak memory 201240 kb
Host smart-2bd83040-ce14-4325-a5b2-db756ea4aeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405398078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1405398078
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.684385550
Short name T371
Test name
Test status
Simulation time 3684344347 ps
CPU time 9.02 seconds
Started Feb 18 01:22:45 PM PST 24
Finished Feb 18 01:22:55 PM PST 24
Peak memory 201228 kb
Host smart-f7989b47-2f0c-47b9-a676-4b8cffd151c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684385550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.684385550
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3020250803
Short name T519
Test name
Test status
Simulation time 5710903249 ps
CPU time 14.26 seconds
Started Feb 18 01:22:42 PM PST 24
Finished Feb 18 01:22:57 PM PST 24
Peak memory 201212 kb
Host smart-2f20f949-9f1a-4e95-bac0-1a79f56c786b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020250803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3020250803
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.480811299
Short name T646
Test name
Test status
Simulation time 397273898 ps
CPU time 1.33 seconds
Started Feb 18 01:15:11 PM PST 24
Finished Feb 18 01:15:14 PM PST 24
Peak memory 201176 kb
Host smart-cac51250-e669-4c42-a3af-79f0c8f1e27d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480811299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.480811299
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3161658772
Short name T279
Test name
Test status
Simulation time 485614608292 ps
CPU time 1006.57 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:31:56 PM PST 24
Peak memory 201380 kb
Host smart-b8c4a5e1-a952-4553-a460-6f44a2d4a1f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161658772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3161658772
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2008893842
Short name T240
Test name
Test status
Simulation time 485398457410 ps
CPU time 1202.43 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:35:17 PM PST 24
Peak memory 201440 kb
Host smart-eb4badb3-74bd-4d7a-b7ab-56ca786b485b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008893842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2008893842
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2388882723
Short name T619
Test name
Test status
Simulation time 164418369116 ps
CPU time 409.52 seconds
Started Feb 18 01:15:05 PM PST 24
Finished Feb 18 01:21:57 PM PST 24
Peak memory 201392 kb
Host smart-712b0de0-dbb6-4c06-ab28-1502a1f183b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388882723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2388882723
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.338516416
Short name T713
Test name
Test status
Simulation time 167464191105 ps
CPU time 108.03 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:16:57 PM PST 24
Peak memory 201492 kb
Host smart-8d46f8c1-fdb9-4756-ba4d-54c954b851eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338516416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.338516416
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.257203411
Short name T636
Test name
Test status
Simulation time 496365547923 ps
CPU time 1178.68 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:34:48 PM PST 24
Peak memory 201456 kb
Host smart-9eee5c9d-fad9-4846-80c6-8c4f9a6999f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=257203411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.257203411
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.358581036
Short name T267
Test name
Test status
Simulation time 166550297270 ps
CPU time 55.48 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:16:09 PM PST 24
Peak memory 201488 kb
Host smart-74e2e7c2-2572-49e3-95e5-6a4e9b329faa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358581036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.358581036
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1881809439
Short name T399
Test name
Test status
Simulation time 325660106290 ps
CPU time 722.87 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:27:17 PM PST 24
Peak memory 201492 kb
Host smart-c512bb06-1394-4e47-b863-28774839ad43
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881809439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1881809439
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2626804296
Short name T719
Test name
Test status
Simulation time 83584286249 ps
CPU time 273.44 seconds
Started Feb 18 01:15:02 PM PST 24
Finished Feb 18 01:19:39 PM PST 24
Peak memory 201724 kb
Host smart-567c3d41-85cb-478c-82a6-c2e79b0928a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626804296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2626804296
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.935874718
Short name T495
Test name
Test status
Simulation time 21566709974 ps
CPU time 5.57 seconds
Started Feb 18 01:15:03 PM PST 24
Finished Feb 18 01:15:12 PM PST 24
Peak memory 201208 kb
Host smart-3c62da23-a982-4019-b18e-0b85b8583303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935874718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.935874718
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1945325591
Short name T400
Test name
Test status
Simulation time 3555789262 ps
CPU time 5 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:15:20 PM PST 24
Peak memory 201228 kb
Host smart-7b227ddb-7cfd-4c6e-ad0d-ef40cbc55a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945325591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1945325591
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2570699220
Short name T730
Test name
Test status
Simulation time 5793239173 ps
CPU time 3.87 seconds
Started Feb 18 01:15:08 PM PST 24
Finished Feb 18 01:15:13 PM PST 24
Peak memory 201176 kb
Host smart-1272f405-1f66-4435-af5b-2af3a33a9e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570699220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2570699220
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2549003805
Short name T304
Test name
Test status
Simulation time 400142615508 ps
CPU time 315.51 seconds
Started Feb 18 01:15:03 PM PST 24
Finished Feb 18 01:20:22 PM PST 24
Peak memory 209980 kb
Host smart-fbe6bc0b-4869-4e28-a034-31d2b380ebe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549003805 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2549003805
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2165145841
Short name T458
Test name
Test status
Simulation time 461148989 ps
CPU time 0.93 seconds
Started Feb 18 01:15:05 PM PST 24
Finished Feb 18 01:15:08 PM PST 24
Peak memory 201076 kb
Host smart-ea42f5e8-3e24-49ca-a4fe-61680fd7331d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165145841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2165145841
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2860969772
Short name T751
Test name
Test status
Simulation time 165078884667 ps
CPU time 92.07 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:16:41 PM PST 24
Peak memory 201408 kb
Host smart-968ee80a-616b-48b3-a700-9b61911209aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860969772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2860969772
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1102260753
Short name T767
Test name
Test status
Simulation time 169890515615 ps
CPU time 100.11 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:16:54 PM PST 24
Peak memory 201476 kb
Host smart-e0378ebe-2edb-473b-adec-f96459359c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102260753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1102260753
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1438800368
Short name T374
Test name
Test status
Simulation time 167359473086 ps
CPU time 102.42 seconds
Started Feb 18 01:15:03 PM PST 24
Finished Feb 18 01:16:49 PM PST 24
Peak memory 201396 kb
Host smart-f8621065-01d1-45f1-8d85-89e8b8980554
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438800368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1438800368
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3372982727
Short name T317
Test name
Test status
Simulation time 333704005485 ps
CPU time 358.17 seconds
Started Feb 18 01:15:07 PM PST 24
Finished Feb 18 01:21:08 PM PST 24
Peak memory 201516 kb
Host smart-ce861dd2-d776-4ec4-b700-02dae0f64eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372982727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3372982727
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3313485407
Short name T682
Test name
Test status
Simulation time 167103500531 ps
CPU time 97.87 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:16:53 PM PST 24
Peak memory 201460 kb
Host smart-dce72ca1-27e5-4d52-ac68-64b5b0b86bef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313485407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3313485407
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1578385419
Short name T321
Test name
Test status
Simulation time 333194233465 ps
CPU time 407.9 seconds
Started Feb 18 01:15:03 PM PST 24
Finished Feb 18 01:21:54 PM PST 24
Peak memory 201400 kb
Host smart-c6f21375-e7b7-4e21-bb04-71cea47e6571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578385419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1578385419
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1720053367
Short name T755
Test name
Test status
Simulation time 325208376353 ps
CPU time 738.62 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:27:33 PM PST 24
Peak memory 201380 kb
Host smart-20c2b336-7030-40c3-bc68-fd7202877e15
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720053367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1720053367
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1546598150
Short name T648
Test name
Test status
Simulation time 113238436509 ps
CPU time 392.63 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:21:47 PM PST 24
Peak memory 201780 kb
Host smart-f86de733-cc09-430f-9b44-b8feb0fde273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546598150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1546598150
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.664891141
Short name T674
Test name
Test status
Simulation time 24695357422 ps
CPU time 52.21 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:16:07 PM PST 24
Peak memory 201228 kb
Host smart-dd14cca7-556b-404a-96d8-1b4d7c28d8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664891141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.664891141
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2584433425
Short name T692
Test name
Test status
Simulation time 3820737835 ps
CPU time 1.91 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:15:15 PM PST 24
Peak memory 201232 kb
Host smart-398631d3-b816-4c37-9b08-683e6ff02557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584433425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2584433425
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3643957620
Short name T1
Test name
Test status
Simulation time 5989648568 ps
CPU time 4.16 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:15:18 PM PST 24
Peak memory 201228 kb
Host smart-9fb44d2c-b149-423a-a17e-5c37d132ae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643957620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3643957620
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1923473871
Short name T601
Test name
Test status
Simulation time 208270467749 ps
CPU time 261.8 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:19:36 PM PST 24
Peak memory 201492 kb
Host smart-a90c54f8-2868-4b75-88c3-87bca12a2677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923473871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1923473871
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3302765180
Short name T595
Test name
Test status
Simulation time 453519067 ps
CPU time 1.15 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:15:16 PM PST 24
Peak memory 201168 kb
Host smart-7a956140-860b-4d82-8b7a-c3769a5758a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302765180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3302765180
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.544245706
Short name T163
Test name
Test status
Simulation time 160080550221 ps
CPU time 372.49 seconds
Started Feb 18 01:15:10 PM PST 24
Finished Feb 18 01:21:23 PM PST 24
Peak memory 201464 kb
Host smart-53ce866c-b876-434b-ab14-84b5a7bb8bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544245706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.544245706
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.4037472859
Short name T612
Test name
Test status
Simulation time 329978690622 ps
CPU time 204.01 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:18:37 PM PST 24
Peak memory 201448 kb
Host smart-f14a7e34-13e5-4b88-a05f-64809d0fa110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037472859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.4037472859
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3609623396
Short name T129
Test name
Test status
Simulation time 488526980422 ps
CPU time 1220.46 seconds
Started Feb 18 01:15:14 PM PST 24
Finished Feb 18 01:35:36 PM PST 24
Peak memory 201480 kb
Host smart-8c0e7cc6-c001-4cbc-ac12-051e0503b9cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609623396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3609623396
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2402730223
Short name T493
Test name
Test status
Simulation time 164551367504 ps
CPU time 48.67 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:16:03 PM PST 24
Peak memory 201440 kb
Host smart-5f8183d2-6df6-4323-8284-c78787249729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402730223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2402730223
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2885741961
Short name T562
Test name
Test status
Simulation time 335811355928 ps
CPU time 384.82 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:21:39 PM PST 24
Peak memory 201432 kb
Host smart-fdd4d9ab-3f34-4472-83a3-8573ba6589d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885741961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2885741961
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2865036210
Short name T274
Test name
Test status
Simulation time 494934123166 ps
CPU time 353.13 seconds
Started Feb 18 01:15:11 PM PST 24
Finished Feb 18 01:21:05 PM PST 24
Peak memory 201492 kb
Host smart-69a606ca-7a56-4cce-b77a-ac67c29c6cc3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865036210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2865036210
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.785529863
Short name T411
Test name
Test status
Simulation time 499586056560 ps
CPU time 1233.46 seconds
Started Feb 18 01:15:11 PM PST 24
Finished Feb 18 01:35:45 PM PST 24
Peak memory 201496 kb
Host smart-fd6cd7ee-8060-4ac1-991d-9f4b4811934d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785529863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.785529863
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2331966357
Short name T214
Test name
Test status
Simulation time 105617682591 ps
CPU time 429.59 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:22:22 PM PST 24
Peak memory 201744 kb
Host smart-58d7b0aa-1c89-4c89-bd78-e5274eb23ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331966357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2331966357
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3580390968
Short name T491
Test name
Test status
Simulation time 40072928399 ps
CPU time 93.62 seconds
Started Feb 18 01:15:09 PM PST 24
Finished Feb 18 01:16:44 PM PST 24
Peak memory 201224 kb
Host smart-618a6559-4534-48b2-b27e-10a1daf0ae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580390968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3580390968
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.4149368852
Short name T396
Test name
Test status
Simulation time 4887919557 ps
CPU time 1.29 seconds
Started Feb 18 01:15:15 PM PST 24
Finished Feb 18 01:15:17 PM PST 24
Peak memory 201228 kb
Host smart-d20ec927-46bb-48dc-803c-5f14ae30ca18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149368852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.4149368852
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2641088875
Short name T598
Test name
Test status
Simulation time 5784644360 ps
CPU time 3.96 seconds
Started Feb 18 01:15:12 PM PST 24
Finished Feb 18 01:15:17 PM PST 24
Peak memory 201228 kb
Host smart-55b24051-cea3-4b8c-86b1-e1551864fe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641088875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2641088875
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.4280770798
Short name T548
Test name
Test status
Simulation time 231273720805 ps
CPU time 326.09 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:20:41 PM PST 24
Peak memory 201740 kb
Host smart-27736aa8-654c-427d-8916-335e7586e3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280770798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
4280770798
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1214205481
Short name T61
Test name
Test status
Simulation time 15191237177 ps
CPU time 36.55 seconds
Started Feb 18 01:15:13 PM PST 24
Finished Feb 18 01:15:51 PM PST 24
Peak memory 209812 kb
Host smart-1bd490dc-befe-4895-9567-0683423edaaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214205481 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1214205481
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2624453655
Short name T702
Test name
Test status
Simulation time 525904894 ps
CPU time 0.91 seconds
Started Feb 18 01:15:21 PM PST 24
Finished Feb 18 01:15:25 PM PST 24
Peak memory 200776 kb
Host smart-d6c42385-1210-4a22-af25-098f363c2e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624453655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2624453655
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1793918180
Short name T335
Test name
Test status
Simulation time 163828415209 ps
CPU time 16.06 seconds
Started Feb 18 01:15:18 PM PST 24
Finished Feb 18 01:15:35 PM PST 24
Peak memory 201436 kb
Host smart-16ff1409-d54c-42dd-8487-909599c2c46c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793918180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1793918180
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1005941416
Short name T145
Test name
Test status
Simulation time 167471147076 ps
CPU time 323.96 seconds
Started Feb 18 01:15:21 PM PST 24
Finished Feb 18 01:20:48 PM PST 24
Peak memory 200976 kb
Host smart-35d7a60f-607e-4e78-b0f1-b7cf89e808ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005941416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1005941416
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.639582888
Short name T190
Test name
Test status
Simulation time 161142276812 ps
CPU time 30.67 seconds
Started Feb 18 01:15:17 PM PST 24
Finished Feb 18 01:15:49 PM PST 24
Peak memory 201476 kb
Host smart-952b1fb0-2d67-45a0-9b7a-2f8d80169708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639582888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.639582888
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3381716456
Short name T426
Test name
Test status
Simulation time 161972137507 ps
CPU time 383.98 seconds
Started Feb 18 01:15:24 PM PST 24
Finished Feb 18 01:21:49 PM PST 24
Peak memory 201288 kb
Host smart-8662696f-52cf-40aa-bb5a-cb538adbf069
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381716456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3381716456
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.748000890
Short name T262
Test name
Test status
Simulation time 326228817856 ps
CPU time 342.84 seconds
Started Feb 18 01:15:17 PM PST 24
Finished Feb 18 01:21:01 PM PST 24
Peak memory 201476 kb
Host smart-f6533984-5355-4acf-aa68-75b88acc3c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748000890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.748000890
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.4098023901
Short name T737
Test name
Test status
Simulation time 492622143189 ps
CPU time 1180.56 seconds
Started Feb 18 01:15:17 PM PST 24
Finished Feb 18 01:34:58 PM PST 24
Peak memory 201512 kb
Host smart-ba4f8957-0913-43a9-9014-e67b41bbd35f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098023901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.4098023901
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3068887634
Short name T365
Test name
Test status
Simulation time 500605249109 ps
CPU time 599.23 seconds
Started Feb 18 01:15:24 PM PST 24
Finished Feb 18 01:25:25 PM PST 24
Peak memory 201360 kb
Host smart-5d9796e7-378f-44f3-801a-5f4ea060c918
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068887634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3068887634
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.398420819
Short name T486
Test name
Test status
Simulation time 100174580623 ps
CPU time 496.49 seconds
Started Feb 18 01:15:20 PM PST 24
Finished Feb 18 01:23:38 PM PST 24
Peak memory 201780 kb
Host smart-965f8607-adcf-4dbb-8f49-a135a8925b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398420819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.398420819
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3398753095
Short name T7
Test name
Test status
Simulation time 36510851820 ps
CPU time 22.4 seconds
Started Feb 18 01:15:20 PM PST 24
Finished Feb 18 01:15:45 PM PST 24
Peak memory 201156 kb
Host smart-6db4a659-ab9f-46df-a9e5-c713f2478012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398753095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3398753095
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.379183168
Short name T567
Test name
Test status
Simulation time 4730193909 ps
CPU time 12.48 seconds
Started Feb 18 01:15:19 PM PST 24
Finished Feb 18 01:15:34 PM PST 24
Peak memory 201200 kb
Host smart-54a20d25-e2b9-4365-884b-8606aa88fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379183168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.379183168
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3881489553
Short name T88
Test name
Test status
Simulation time 5678684129 ps
CPU time 2.42 seconds
Started Feb 18 01:15:19 PM PST 24
Finished Feb 18 01:15:23 PM PST 24
Peak memory 201216 kb
Host smart-fb48edbb-6a9b-4620-bbe5-b547ef978feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881489553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3881489553
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1871824110
Short name T779
Test name
Test status
Simulation time 333259635003 ps
CPU time 190.94 seconds
Started Feb 18 01:15:16 PM PST 24
Finished Feb 18 01:18:28 PM PST 24
Peak memory 201352 kb
Host smart-cae1605f-2e10-4996-94ad-bc6652b173ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871824110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1871824110
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3881424318
Short name T531
Test name
Test status
Simulation time 444445372 ps
CPU time 1.35 seconds
Started Feb 18 01:15:24 PM PST 24
Finished Feb 18 01:15:27 PM PST 24
Peak memory 201144 kb
Host smart-9714ed3c-82ad-43c2-9739-94c71cda0f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881424318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3881424318
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.413907420
Short name T322
Test name
Test status
Simulation time 163567325445 ps
CPU time 99.83 seconds
Started Feb 18 01:15:25 PM PST 24
Finished Feb 18 01:17:06 PM PST 24
Peak memory 201444 kb
Host smart-38aa0239-dc09-4123-83a2-8bfe9f65853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413907420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.413907420
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3148651108
Short name T703
Test name
Test status
Simulation time 485990268123 ps
CPU time 318.64 seconds
Started Feb 18 01:15:16 PM PST 24
Finished Feb 18 01:20:36 PM PST 24
Peak memory 201408 kb
Host smart-eca2b882-6e60-42df-bc29-892e15aa7d38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148651108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3148651108
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1760706590
Short name T135
Test name
Test status
Simulation time 335455237278 ps
CPU time 745.57 seconds
Started Feb 18 01:15:17 PM PST 24
Finished Feb 18 01:27:43 PM PST 24
Peak memory 201480 kb
Host smart-eb60f3f4-6f68-4b15-bc01-38e25cef25a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760706590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1760706590
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.828534078
Short name T657
Test name
Test status
Simulation time 162851707906 ps
CPU time 106.56 seconds
Started Feb 18 01:15:17 PM PST 24
Finished Feb 18 01:17:05 PM PST 24
Peak memory 201472 kb
Host smart-3a5aa634-16bc-461b-867e-849145f679c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=828534078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.828534078
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1454901609
Short name T287
Test name
Test status
Simulation time 323377012651 ps
CPU time 788.9 seconds
Started Feb 18 01:15:21 PM PST 24
Finished Feb 18 01:28:32 PM PST 24
Peak memory 201336 kb
Host smart-62aba5d7-6c2b-4285-b0ea-0a78862bd7ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454901609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1454901609
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2401494946
Short name T424
Test name
Test status
Simulation time 332857810269 ps
CPU time 49.09 seconds
Started Feb 18 01:15:16 PM PST 24
Finished Feb 18 01:16:06 PM PST 24
Peak memory 201420 kb
Host smart-046c4b96-68de-4b3a-a5f6-04516820a1ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401494946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2401494946
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2709567366
Short name T192
Test name
Test status
Simulation time 40162669683 ps
CPU time 22.94 seconds
Started Feb 18 01:15:29 PM PST 24
Finished Feb 18 01:15:53 PM PST 24
Peak memory 201236 kb
Host smart-c2cc5d97-d65e-48f4-b187-060bf8690c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709567366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2709567366
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.457942606
Short name T632
Test name
Test status
Simulation time 3984426589 ps
CPU time 3.63 seconds
Started Feb 18 01:15:25 PM PST 24
Finished Feb 18 01:15:30 PM PST 24
Peak memory 201224 kb
Host smart-784e35c3-c8bf-4051-9579-e976a64410e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457942606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.457942606
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3149617088
Short name T410
Test name
Test status
Simulation time 5956643510 ps
CPU time 13.8 seconds
Started Feb 18 01:15:20 PM PST 24
Finished Feb 18 01:15:36 PM PST 24
Peak memory 201116 kb
Host smart-b268de6e-81a1-4b34-a4c2-8e961da41a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149617088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3149617088
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.619657028
Short name T727
Test name
Test status
Simulation time 199365913399 ps
CPU time 311.01 seconds
Started Feb 18 01:15:24 PM PST 24
Finished Feb 18 01:20:36 PM PST 24
Peak memory 201420 kb
Host smart-c0f7c0de-7a6e-48eb-95e4-121458876062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619657028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.619657028
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.46321618
Short name T79
Test name
Test status
Simulation time 83176535801 ps
CPU time 178.35 seconds
Started Feb 18 01:15:25 PM PST 24
Finished Feb 18 01:18:25 PM PST 24
Peak memory 201548 kb
Host smart-1ad168b6-4aca-4792-a356-aa7865d06da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46321618 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.46321618
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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