Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7119	1			T1	20		T2	20		T6	93
testmodes[AdcCtrlTestmodeNormal]	5501	1			T6	34		T8	5		T9	2
testmodes[AdcCtrlTestmodeLowpower]	5598	1			T3	2		T4	1		T5	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3928	1			T1	19		T2	19		T6	68
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1764	1			T6	7		T8	5		T14	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1328	1			T6	18		T14	3		T19	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1744	1			T6	15		T8	5		T14	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1982	1			T6	14		T10	2		T14	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1437	1			T6	5		T9	1		T14	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1326	1			T6	10		T14	3		T19	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1420	1			T6	13		T9	1		T14	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2595	1			T3	1		T5	2		T6	19