Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22275

1

T1

20

T2

20

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3254

1

T6

8

T9

16

T16

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20162

1

T1

20

T2

20

T3

6

auto[1]

5367

1

T3

14

T4

12

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T241	8		-	-		-	-
values[0]	143	1			T91	32		T65	25		T242	6
values[1]	702	1			T243	24		T51	14		T58	4
values[2]	642	1			T9	16		T18	3		T139	13
values[3]	706	1			T3	14		T100	1		T133	8
values[4]	2459	1			T5	26		T10	3		T12	12
values[5]	683	1			T4	12		T6	8		T9	2
values[6]	481	1			T9	7		T134	9		T151	1
values[7]	539	1			T9	17		T11	16		T133	1
values[8]	511	1			T131	4		T149	25		T30	29
values[9]	1292	1			T3	6		T133	8		T132	28
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	909	1			T9	16		T243	24		T222	5
values[1]	808	1			T133	8		T18	3		T139	13
values[2]	606	1			T3	14		T100	1		T18	1
values[3]	2519	1			T5	26		T6	8		T9	2
values[4]	676	1			T4	12		T9	7		T134	9
values[5]	484	1			T9	17		T199	24		T151	1
values[6]	532	1			T11	16		T131	1		T133	1
values[7]	428	1			T30	29		T31	10		T135	1
values[8]	938	1			T3	6		T131	3		T133	8
values[9]	266	1			T140	9		T244	23		T241	8
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T222	4		T51	12		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T9	12		T243	13		T58	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T133	1		T139	1		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T18	3		T203	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	14		T135	1		T51	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T100	1		T18	1		T31	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T5	26		T9	2		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	5		T16	6		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	12		T9	1		T134	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T139	1		T58	14		T171	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	9		T199	10		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T151	1		T123	1		T32	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	14		T131	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T149	13		T228	1		T156	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T135	1		T152	1		T53	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T30	14		T31	3		T136	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	6		T131	1		T132	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T133	1		T204	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T140	9		T244	11		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T241	8		T246	1		T247	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T222	1		T51	2		T248	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	4		T243	11		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T133	7		T139	12		T237	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T203	11		T91	2		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T51	7		T172	9		T248	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T31	17		T148	16		T174	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T12	11		T59	10		T193	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	3		T210	4		T249	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	6		T31	4		T169	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T139	11		T58	15		T171	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	8		T199	14		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T123	6		T32	10		T192	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	2		T149	11		T136	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T149	12		T228	3		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T251	13		T154	3		T252	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T30	15		T31	7		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T131	2		T132	14		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T133	7		T199	13		T169	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T244	12		T253	9		T254	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T246	13		T247	4		T255	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T241	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T91	15		T242	5		T256	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T65	12		T257	9		T258	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T51	12		T182	1		T248	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T243	13		T58	4		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T139	1		T222	4		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	12		T18	3		T56	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	14		T133	1		T172	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T100	1		T18	1		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T5	26		T10	3		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T31	17		T150	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	12		T9	2		T100	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	5		T16	6		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	1		T134	9		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T151	1		T32	9		T171	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	9		T11	14		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T228	1		T259	1		T226	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T131	2		T135	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T149	13		T30	14		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T3	6		T132	14		T134	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T133	1		T204	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T91	17		T242	1		T260	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T65	13		T257	9		T258	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T51	2		T248	16		T261	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T243	11		T167	12		T262	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T139	12		T222	1		T237	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	4		T142	13		T91	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T133	7		T172	16		T248	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T203	11		T174	13		T263	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T12	11		T59	10		T193	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T31	17		T148	16		T249	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T31	4		T199	14		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	3		T139	11		T123	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	6		T169	2		T171	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T32	10		T171	12		T264	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	8		T11	2		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T228	3		T259	8		T226	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T131	2		T122	1		T251	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T149	12		T30	15		T31	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T132	14		T244	12		T265	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T133	7		T199	13		T169	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T222	2		T51	3		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T9	5		T243	12		T58	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T133	8		T139	13		T237	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T18	1		T203	12		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	1		T135	1		T51	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T100	1		T18	1		T31	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T5	3		T9	1		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	5		T16	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	1		T9	7		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T139	12		T58	16		T171	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	9		T199	15		T122	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T151	1		T123	7		T32	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	3		T131	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T149	13		T228	4		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T135	1		T152	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T30	16		T31	8		T136	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T3	1		T131	3		T132	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T133	8		T204	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T140	1		T244	13		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T241	1		T246	14		T247	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T222	3		T51	11		T248	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	11		T243	12		T58	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T172	10		T261	5		T216	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T18	2		T56	10		T91	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	13		T51	12		T172	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T31	16		T148	12		T266	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T5	23		T9	1		T13	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	3		T16	5		T210	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	11		T134	8		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T58	13		T171	2		T216	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T9	8		T199	9		T91	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T32	8		T192	1		T226	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	13		T18	12		T136	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T149	12		T156	12		T173	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T53	12		T154	6		T241	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T30	13		T31	2		T136	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	5		T132	13		T134	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T199	9		T146	7		T267	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T140	8		T244	10		T268	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T241	7		T247	14		T255	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T241	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T91	18		T242	5		T256	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T65	14		T257	10		T258	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T51	3		T182	1		T248	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T243	12		T58	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T139	13		T222	2		T237	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	5		T18	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T133	8		T172	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T100	1		T18	1		T203	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T5	3		T10	3		T12	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T31	18		T150	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	1		T9	1		T100	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	5		T16	1		T139	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	7		T134	1		T169	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T151	1		T32	11		T171	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	9		T11	3		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T228	4		T259	9		T226	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T131	4		T135	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T149	13		T30	16		T31	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T3	1		T132	15		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T133	8		T204	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T241	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T91	14		T242	1		T260	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T65	11		T257	8		T258	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T51	11		T248	11		T261	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T243	12		T58	3		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T222	3		T257	14		T175	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	11		T18	2		T56	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	13		T172	19		T248	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T269	17		T270	15		T263	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T5	23		T13	10		T17	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T31	16		T148	12		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	11		T9	1		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	3		T16	5		T58	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T134	8		T171	11		T91	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T32	8		T171	2		T264	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	8		T11	13		T18	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T226	1		T195	8		T271	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T219	12		T122	1		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T149	12		T30	13		T31	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T3	5		T132	13		T134	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T199	9		T190	2		T146	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22299

1

T1

20

T2

20

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3230

1

T9

2

T100

3

T131

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19794

1

T1

20

T2

20

T4

12

auto[1]

5735

1

T3

20

T5

26

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	795	1			T3	14		T6	8		T14	5
values[0]	1	1			T206	1		-	-		-	-
values[1]	726	1			T149	25		T31	10		T150	1
values[2]	2554	1			T5	26		T6	8		T9	2
values[3]	506	1			T9	16		T16	6		T100	1
values[4]	639	1			T3	6		T9	7		T149	12
values[5]	582	1			T100	1		T139	12		T152	1
values[6]	639	1			T4	12		T131	3		T133	16
values[7]	598	1			T100	1		T133	1		T132	28
values[8]	759	1			T11	16		T131	1		T139	13
values[9]	813	1			T9	17		T18	13		T30	29
minimum	16917	1			T1	20		T2	20		T6	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	661	1			T149	25		T31	34		T123	7
values[1]	2507	1			T5	26		T9	2		T10	3
values[2]	614	1			T3	6		T6	8		T9	16
values[3]	600	1			T9	7		T149	12		T199	23
values[4]	594	1			T4	12		T100	1		T133	8
values[5]	588	1			T100	1		T131	3		T133	8
values[6]	632	1			T133	1		T134	6		T204	1
values[7]	717	1			T9	17		T11	16		T131	1
values[8]	891	1			T3	14		T18	13		T30	29
values[9]	144	1			T153	1		T172	21		T248	12
minimum	17581	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T149	13		T31	17		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T123	1		T169	1		T72	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T5	26		T10	3		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	2		T34	2		T170	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	6		T6	5		T9	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T100	1		T134	9		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T149	1		T172	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T199	10		T152	2		T171	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	12		T133	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T100	1		T139	1		T222	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T131	1		T18	3		T136	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T100	1		T133	1		T199	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T133	1		T134	6		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T204	1		T151	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	9		T11	14		T132	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T131	1		T31	3		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	14		T18	13		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T30	14		T135	1		T140	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T153	1		T172	11		T248	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T205	1		T266	11		T272	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17265	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T219	13		T58	4		T90	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T149	12		T31	17		T154	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T123	6		T169	2		T257	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	901	1			T12	11		T59	10		T193	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T170	16		T214	8		T65	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	3		T9	4		T51	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T251	13		T273	11		T274	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	6		T149	11		T172	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T199	13		T171	4		T192	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T133	7		T122	1		T142	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T139	11		T222	1		T171	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T131	2		T136	6		T237	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T133	7		T199	14		T169	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T139	12		T143	3		T227	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T203	11		T51	2		T32	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T9	8		T11	2		T132	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T31	4		T145	17		T98	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T122	1		T33	1		T250	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T30	15		T142	13		T251	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T172	10		T248	7		T188	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T266	11		T272	13		T275	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	1		T31	7		T182	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T276	7		T277	14		T278	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	549	1			T3	14		T6	8		T14	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T53	1		T142	1		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T206	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T149	13		T31	3		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T219	13		T58	4		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T5	26		T6	5		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	2		T34	2		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	12		T16	6		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T100	1		T134	9		T251	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	6		T9	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T199	10		T152	1		T208	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T122	1		T142	2		T172	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T100	1		T139	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	12		T131	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T133	1		T169	1		T262	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T133	1		T132	14		T134	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T100	1		T204	1		T199	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	14		T139	1		T202	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T131	1		T203	1		T51	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	9		T18	13		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T30	14		T31	3		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16770	1			T1	20		T2	20		T6	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T33	1		T265	6		T279	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T142	13		T266	11		T280	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T149	12		T31	7		T154	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T169	2		T257	23		T252	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T6	3		T12	11		T59	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T123	6		T170	16		T214	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T9	4		T237	12		T91	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T251	13		T273	11		T281	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	6		T149	11		T51	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T199	13		T174	13		T265	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T122	1		T142	21		T172	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T139	11		T222	1		T171	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T131	2		T133	7		T136	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T133	7		T169	12		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T132	14		T237	6		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T199	14		T32	10		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	2		T139	12		T202	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T203	11		T51	2		T145	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	8		T122	1		T172	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T30	15		T31	4		T251	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1