Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22415

1

T1

20

T2

20

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

3114

1

T3

20

T9

24

T131

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20291

1

T1

20

T2

20

T3

6

auto[1]

5238

1

T3

14

T4

12

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	308	1			T9	17		T204	1		T222	5
values[0]	84	1			T135	1		T53	13		T205	1
values[1]	510	1			T18	13		T31	7		T152	1
values[2]	623	1			T139	12		T135	1		T151	1
values[3]	684	1			T100	1		T135	1		T243	24
values[4]	775	1			T3	20		T9	23		T132	28
values[5]	518	1			T100	1		T131	3		T134	6
values[6]	556	1			T6	8		T16	6		T131	1
values[7]	603	1			T136	22		T32	1		T154	10
values[8]	2600	1			T5	26		T10	3		T12	12
values[9]	905	1			T4	12		T9	2		T11	16
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	551	1			T18	13		T31	7		T152	1
values[1]	625	1			T139	12		T135	2		T151	1
values[2]	673	1			T100	1		T243	24		T140	16
values[3]	823	1			T3	20		T9	23		T131	3
values[4]	416	1			T16	6		T100	1		T131	1
values[5]	578	1			T6	8		T149	12		T152	1
values[6]	2616	1			T5	26		T10	3		T12	12
values[7]	673	1			T133	16		T31	34		T53	1
values[8]	822	1			T4	12		T9	2		T11	16
values[9]	185	1			T9	17		T222	5		T172	18
minimum	17567	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T18	13		T31	3		T32	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T152	1		T56	6		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T139	1		T135	2		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T51	13		T122	4		T208	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T100	1		T140	7		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T243	13		T140	9		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	12		T131	1		T31	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	20		T9	1		T132	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T16	6		T100	1		T199	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T131	1		T134	6		T171	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	5		T149	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T162	2		T147	1		T264	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T5	26		T10	3		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T32	1		T154	7		T298	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T133	2		T169	1		T94	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T31	17		T53	1		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	12		T9	2		T11	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T18	4		T149	13		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T222	4		T172	11		T229	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T9	9		T192	1		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17289	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T135	1		T142	1		T192	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T31	4		T32	10		T169	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T142	13		T94	5		T228	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T139	11		T136	11		T143	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T51	7		T122	1		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T167	12		T259	15		T281	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T243	11		T169	2		T170	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	4		T131	2		T31	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T9	6		T132	14		T30	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T199	13		T202	9		T266	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T171	12		T33	1		T232	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	3		T149	11		T172	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T264	12		T308	7		T338	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T12	11		T59	10		T193	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T154	3		T298	6		T91	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T133	14		T169	9		T94	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	17		T237	12		T251	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	2		T199	14		T58	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T149	12		T123	6		T146	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T222	1		T172	7		T229	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T9	8		T192	7		T277	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T182	3		T143	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T142	8		T192	6		T271	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T222	4		T58	14		T172	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	9		T204	1		T192	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T53	13		T205	1		T277	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T135	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T18	13		T31	3		T219	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T152	1		T56	6		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T139	1		T135	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T122	4		T142	1		T208	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T100	1		T135	1		T140	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T243	13		T51	13		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	12		T31	3		T248	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	20		T9	1		T132	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T100	1		T131	1		T202	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T134	6		T237	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	5		T16	6		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T131	1		T162	2		T336	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	16		T145	1		T172	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T32	1		T154	7		T298	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T5	26		T10	3		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T53	1		T237	1		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T4	12		T9	2		T11	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T18	4		T149	13		T31	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T222	1		T58	15		T172	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T9	8		T192	7		T257	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T277	8		T121	13		T339	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T31	4		T32	10		T169	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T142	8		T94	5		T192	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T139	11		T136	11		T122	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T122	1		T142	13		T210	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T167	12		T259	15		T257	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T243	11		T51	7		T169	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	4		T31	7		T248	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	6		T132	14		T30	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T131	2		T202	9		T203	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T237	6		T142	13		T171	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	3		T149	11		T199	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T246	13		T308	7		T338	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T136	6		T145	17		T172	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T154	3		T298	6		T65	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T12	11		T59	10		T133	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T237	12		T251	2		T91	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	2		T199	14		T248	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T149	12		T31	17		T123	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T18	1		T31	5		T32	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T152	1		T56	1		T142	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T139	12		T135	2		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T51	8		T122	4		T208	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T100	1		T140	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T243	12		T140	1		T169	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	5		T131	3		T31	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T3	2		T9	7		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	1		T100	1		T199	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T131	1		T134	1		T171	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	5		T149	12		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T162	2		T147	1		T264	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T5	3		T10	3		T12	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T32	1		T154	4		T298	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T133	16		T169	10		T94	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T31	18		T53	1		T237	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	1		T9	1		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T18	2		T149	13		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T222	2		T172	8		T229	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T9	9		T192	8		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17414	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T135	1		T142	9		T192	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T18	12		T31	2		T32	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T56	5		T228	5		T230	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	1		T58	3		T143	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T51	12		T122	1		T210	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	6		T167	12		T66	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T243	12		T140	8		T170	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	11		T31	2		T248	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	18		T132	13		T134	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T16	5		T199	9		T202	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T134	5		T171	2		T146	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	3		T172	10		T241	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T264	11		T312	6		T338	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T5	23		T13	10		T17	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T154	6		T91	14		T65	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T94	10		T156	12		T61	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T31	16		T216	10		T244	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	11		T9	1		T11	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T18	2		T149	12		T56	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T222	3		T172	10		T229	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T9	8		T277	12		T345	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T219	12		T53	12		T156	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T192	8		T241	7		T271	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T222	2		T58	16		T172	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T9	9		T204	1		T192	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T53	1		T205	1		T277	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T135	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T18	1		T31	5		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T152	1		T56	1		T142	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T139	12		T135	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T122	4		T142	14		T208	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T100	1		T135	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T243	12		T51	8		T169	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	5		T31	8		T248	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	2		T9	7		T132	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T100	1		T131	3		T202	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T134	1		T237	7		T142	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	5		T16	1		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T131	1		T162	2		T336	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	7		T145	18		T172	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T32	1		T154	4		T298	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T5	3		T10	3		T12	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T53	1		T237	13		T251	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T4	1		T9	1		T11	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T18	2		T149	13		T31	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T222	3		T58	13		T172	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T9	8		T257	14		T277	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T53	12		T277	6		T121	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T18	12		T31	2		T219	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T56	5		T192	8		T228	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T136	1		T58	3		T171	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T122	1		T210	11		T173	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T140	6		T167	12		T257	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T243	12		T51	12		T170	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	11		T31	2		T248	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	18		T132	13		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T202	7		T221	6		T252	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T134	5		T171	2		T146	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	3		T16	5		T199	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T312	6		T338	9		T195	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T136	15		T172	10		T293	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T154	6		T65	11		T264	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T5	23		T13	10		T17	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T91	14		T216	10		T244	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	11		T9	1		T11	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T18	2		T149	12		T31	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23