Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20074

1

T1

20

T2

20

T3

6

auto[ADC_CTRL_FILTER_COND_OUT]

5455

1

T3

14

T5

26

T9

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20357

1

T1

20

T2

20

T3

14

auto[1]

5172

1

T3

6

T4

12

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	300	1			T140	9		T202	17		T33	1
values[0]	17	1			T135	1		T259	9		T346	4
values[1]	617	1			T4	12		T16	6		T34	2
values[2]	654	1			T100	1		T243	24		T58	4
values[3]	816	1			T3	6		T9	16		T100	1
values[4]	753	1			T18	3		T134	9		T31	7
values[5]	560	1			T100	1		T123	7		T136	22
values[6]	474	1			T3	14		T6	8		T9	7
values[7]	609	1			T9	2		T11	16		T133	8
values[8]	519	1			T9	17		T133	1		T18	13
values[9]	2847	1			T5	26		T10	3		T12	12
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	637	1			T4	12		T135	1		T243	24
values[1]	2677	1			T5	26		T10	3		T12	12
values[2]	855	1			T3	6		T9	16		T100	1
values[3]	637	1			T18	3		T134	9		T31	7
values[4]	522	1			T6	8		T9	7		T100	1
values[5]	552	1			T3	14		T53	1		T32	19
values[6]	534	1			T9	2		T11	16		T133	8
values[7]	678	1			T9	17		T133	1		T134	6
values[8]	795	1			T131	4		T31	34		T139	12
values[9]	163	1			T222	5		T169	3		T306	1
minimum	17479	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T4	12		T243	13		T34	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T135	1		T136	2		T53	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T169	1		T170	7		T143	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1355	1			T5	26		T10	3		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	6		T133	1		T132	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T9	12		T100	1		T149	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T18	3		T31	3		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T134	9		T140	7		T199	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	5		T9	1		T91	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T100	1		T123	1		T136	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T53	1		T273	1		T248	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	14		T32	9		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	2		T11	14		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T149	1		T50	1		T122	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T134	6		T151	1		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	9		T133	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T131	1		T221	7		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T131	1		T31	17		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T222	4		T169	1		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T146	8		T191	1		T265	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17250	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T16	6		T51	12		T142	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T243	11		T251	13		T167	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T136	11		T210	4		T261	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T169	12		T170	16		T143	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1049	1			T12	11		T59	10		T193	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T133	7		T132	14		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	4		T149	12		T30	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T31	4		T203	11		T214	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T199	13		T51	7		T172	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	3		T9	6		T91	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T123	6		T136	6		T192	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T273	11		T248	7		T216	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T32	10		T142	8		T91	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	2		T133	7		T31	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T149	11		T122	2		T171	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T284	18		T280	15		T341	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	8		T199	14		T58	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T131	2		T171	12		T227	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T31	17		T139	11		T202	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T222	1		T169	2		T148	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T146	8		T265	10		T198	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T182	3		T143	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T51	2		T142	13		T347	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T33	1		T148	13		T288	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T140	9		T202	8		T146	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T259	1		T346	4		T348	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T135	1		T349	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T4	12		T34	2		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T16	6		T136	2		T51	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T243	13		T32	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T100	1		T58	4		T237	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	6		T133	1		T132	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	12		T100	1		T149	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T18	3		T31	3		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T134	9		T140	7		T199	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T214	10		T248	12		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T100	1		T123	1		T136	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	5		T9	1		T248	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T3	14		T32	9		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	2		T11	14		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T50	1		T122	4		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T18	13		T134	6		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	9		T133	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T131	1		T151	1		T221	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1394	1			T5	26		T10	3		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T148	16		T288	13		T250	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T202	9		T146	8		T198	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T259	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T251	13		T167	12		T154	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T136	11		T51	2		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T243	11		T169	12		T170	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T237	12		T210	4		T94	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T133	7		T132	14		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T9	4		T149	12		T30	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T31	4		T203	11		T91	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T199	13		T51	7		T172	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T214	8		T248	16		T266	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T123	6		T136	6		T192	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	3		T9	6		T248	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T32	10		T148	1		T230	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	2		T133	7		T31	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T122	1		T142	8		T154	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T232	6		T280	15		T350	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	8		T149	11		T58	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T131	2		T222	1		T169	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1093	1			T12	11		T59	10		T193	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	1		T243	12		T34	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T135	1		T136	12		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T169	13		T170	18		T143	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1366	1			T5	3		T10	3		T12	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T133	8		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T9	5		T100	1		T149	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T18	1		T31	5		T203	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T134	1		T140	1		T199	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	5		T9	7		T91	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T100	1		T123	7		T136	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T53	1		T273	12		T248	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	1		T32	11		T142	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	1		T11	3		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	12		T50	1		T122	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T134	1		T151	1		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	9		T133	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T131	3		T221	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T131	1		T31	18		T139	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T222	2		T169	3		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T146	9		T191	1		T265	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17394	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T16	1		T51	3		T142	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T4	11		T243	12		T167	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T136	1		T53	12		T210	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T170	5		T143	3		T172	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1038	1			T5	23		T13	10		T17	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	5		T132	13		T94	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	11		T149	12		T30	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T18	2		T31	2		T56	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T134	8		T140	6		T199	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	3		T91	8		T320	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T136	15		T192	1		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T248	4		T216	10		T252	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T3	13		T32	8		T91	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	1		T11	13		T18	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T122	1		T171	11		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T134	5		T285	10		T284	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	8		T199	9		T58	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T221	6		T171	2		T286	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T31	16		T140	8		T202	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T222	3		T148	12		T288	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T146	7		T198	9		T344	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T154	6		T226	1		T351	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T16	5		T51	11		T60	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T33	1		T148	17		T288	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T140	1		T202	10		T146	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T259	9		T346	1		T348	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T135	1		T349	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	1		T34	2		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T16	1		T136	12		T51	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T243	12		T32	1		T169	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T100	1		T58	1		T237	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T133	8		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T9	5		T100	1		T149	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	1		T31	5		T203	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T134	1		T140	1		T199	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T214	9		T248	17		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T100	1		T123	7		T136	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	5		T9	7		T248	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T3	1		T32	11		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	1		T11	3		T133	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	1		T122	4		T142	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T18	1		T134	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	9		T133	1		T149	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T131	3		T151	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1435	1			T5	3		T10	3		T12	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T148	12		T288	13		T321	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T140	8		T202	7		T146	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T346	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T4	11		T167	12		T154	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T16	5		T136	1		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T243	12		T170	5		T143	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T58	3		T210	11		T65	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	5		T132	13		T94	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	11		T149	12		T30	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T18	2		T31	2		T56	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T134	8		T140	6		T199	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T214	9		T248	11		T266	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T136	15		T192	1		T157	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	3		T248	4		T91	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T3	13		T32	8		T148	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	1		T11	13		T31	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T122	1		T91	14		T94	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T18	12		T134	5		T232	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	8		T58	13		T171	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T221	6		T222	3		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1052	1			T5	23		T13	10		T17	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23