Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22607

1

T1

20

T2

20

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

2922

1

T9

24

T11

16

T100

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19973

1

T1

20

T2

20

T6

168

auto[1]

5556

1

T3

20

T4

12

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	275	1			T140	7		T53	13		T214	18
values[0]	38	1			T199	23		T300	1		T304	13
values[1]	629	1			T11	16		T16	6		T100	1
values[2]	551	1			T100	1		T132	28		T149	12
values[3]	592	1			T3	14		T134	9		T140	9
values[4]	479	1			T9	16		T131	1		T134	6
values[5]	2634	1			T5	26		T9	9		T10	3
values[6]	613	1			T30	29		T34	2		T123	7
values[7]	629	1			T3	6		T4	12		T31	34
values[8]	510	1			T9	17		T100	1		T204	1
values[9]	1216	1			T6	8		T133	9		T18	16
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	481	1			T11	16		T131	3		T149	25
values[1]	690	1			T100	1		T132	28		T149	12
values[2]	537	1			T3	14		T131	1		T134	6
values[3]	2555	1			T5	26		T9	16		T10	3
values[4]	592	1			T9	9		T133	8		T18	1
values[5]	584	1			T3	6		T30	29		T31	34
values[6]	623	1			T4	12		T135	1		T151	1
values[7]	526	1			T6	8		T9	17		T100	1
values[8]	1273	1			T133	9		T18	16		T135	2
values[9]	71	1			T140	7		T60	1		T352	1
minimum	17597	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T171	12		T261	6		T216	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	14		T131	1		T149	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T132	14		T134	9		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T100	1		T149	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	14		T142	1		T306	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T131	1		T134	6		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T5	26		T9	12		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T56	6		T182	1		T33	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	2		T31	3		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T9	1		T133	1		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	6		T30	14		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T31	17		T199	10		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	12		T135	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T151	1		T58	14		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	5		T139	1		T243	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T9	9		T100	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T133	2		T18	16		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T53	13		T122	4		T214	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T140	7		T353	1		T81	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T60	1		T352	1		T299	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17295	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T199	10		T245	1		T230	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T171	4		T261	8		T216	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	2		T131	2		T149	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T132	14		T139	11		T51	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T149	11		T94	7		T148	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T142	13		T248	16		T250	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T192	4		T228	6		T281	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T9	4		T12	11		T59	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T33	1		T190	5		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T31	4		T122	1		T210	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	6		T133	7		T31	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T30	15		T123	6		T51	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T31	17		T199	14		T237	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T142	8		T143	3		T251	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T58	15		T142	13		T286	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	3		T139	12		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	8		T203	11		T154	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T133	7		T136	6		T237	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T122	1		T214	8		T172	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T81	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T299	14		T354	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	1		T182	3		T143	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T199	13		T253	9		T338	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T140	7		T252	11		T247	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T53	13		T214	10		T94	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T300	1		T304	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T199	10		T355	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	6		T100	1		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	14		T131	1		T149	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	14		T139	1		T221	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T100	1		T149	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	14		T134	9		T51	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T140	9		T32	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	12		T202	8		T32	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T131	1		T134	6		T56	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T5	26		T9	2		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T133	1		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T30	14		T123	1		T51	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T34	2		T152	1		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	6		T4	12		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T31	17		T199	10		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T139	1		T243	13		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	9		T100	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T6	5		T133	2		T18	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T122	4		T162	2		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T252	11		T232	6		T356	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T214	8		T94	5		T242	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T199	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T171	4		T244	12		T174	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	2		T131	2		T149	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	14		T139	11		T169	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T149	11		T94	7		T148	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T51	7		T142	13		T298	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T228	6		T329	10		T271	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	4		T202	9		T32	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T33	1		T190	5		T192	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T12	11		T59	10		T193	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	6		T133	7		T31	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T30	15		T123	6		T51	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T237	12		T229	4		T277	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T142	8		T143	3		T251	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T31	17		T199	14		T142	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T139	12		T243	11		T264	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	8		T203	11		T58	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T6	3		T133	7		T136	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T122	1		T154	16		T172	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T171	5		T261	9		T216	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	3		T131	3		T149	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T132	15		T134	1		T139	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T100	1		T149	12		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T142	14		T306	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T131	1		T134	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T5	3		T9	5		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T56	1		T182	1		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	1		T31	5		T122	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	7		T133	8		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T30	16		T123	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T31	18		T199	15		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T135	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T151	1		T58	16		T142	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	5		T139	13		T243	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	9		T100	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	445	1			T133	9		T18	2		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T53	1		T122	4		T214	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T140	1		T353	1		T81	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T60	1		T352	1		T299	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17420	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T199	14		T245	1		T230	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T171	11		T261	5		T216	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	13		T149	12		T136	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T132	13		T134	8		T221	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T94	10		T146	3		T148	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T3	13		T248	11		T278	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T134	5		T140	8		T192	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T5	23		T9	11		T13	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T56	5		T190	2		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	1		T31	2		T210	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T31	2		T91	14		T192	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	5		T30	13		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T31	16		T199	9		T229	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	11		T219	12		T143	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T58	13		T286	23		T252	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T6	3		T243	12		T222	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T9	8		T172	9		T91	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T18	14		T136	15		T171	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T53	12		T122	1		T214	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T140	6		T81	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T299	12		T354	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T16	5		T257	8		T175	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T199	9		T230	1		T338	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T140	1		T252	12		T247	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T53	1		T214	9		T94	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T300	1		T304	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T199	14		T355	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	1		T100	1		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	3		T131	3		T149	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T132	15		T139	12		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T100	1		T149	12		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T134	1		T51	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T140	1		T32	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	5		T202	10		T32	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T131	1		T134	1		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T5	3		T9	1		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	7		T133	8		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T30	16		T123	7		T51	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T34	2		T152	1		T237	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	1		T4	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T31	18		T199	15		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T139	13		T243	12		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	9		T100	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	453	1			T6	5		T133	9		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T122	4		T162	2		T154	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T140	6		T252	10		T232	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T53	12		T214	9		T242	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T304	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T199	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T16	5		T171	11		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	13		T149	12		T136	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T132	13		T221	6		T170	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T94	10		T148	12		T157	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	13		T134	8		T51	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	8		T146	3		T228	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T9	11		T202	7		T32	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T134	5		T56	5		T190	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T5	23		T9	1		T13	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T31	2		T91	14		T192	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T30	13		T51	11		T56	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T229	2		T320	12		T277	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	5		T4	11		T219	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T31	16		T199	9		T286	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T243	12		T60	2		T264	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T9	8		T58	13		T172	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T6	3		T18	14		T136	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T122	1		T172	20		T91	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23