Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21943

1

T1

20

T2

20

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

3586

1

T3

20

T9

16

T11

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19870

1

T1

20

T2

20

T4

12

auto[1]

5659

1

T3

20

T5

26

T9

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	354	1			T140	9		T199	24		T32	20
values[0]	105	1			T4	12		T247	3		T277	27
values[1]	547	1			T9	19		T135	1		T123	7
values[2]	632	1			T11	16		T132	28		T31	10
values[3]	485	1			T131	1		T35	1		T33	2
values[4]	759	1			T131	3		T133	9		T18	3
values[5]	2607	1			T5	26		T6	8		T9	7
values[6]	705	1			T9	16		T18	14		T149	12
values[7]	482	1			T139	13		T202	17		T203	12
values[8]	659	1			T3	20		T100	2		T133	8
values[9]	831	1			T16	6		T100	1		T134	9
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	625	1			T132	28		T135	1		T140	7
values[1]	525	1			T11	16		T131	1		T31	10
values[2]	581	1			T131	3		T149	25		T30	29
values[3]	2539	1			T5	26		T9	7		T10	3
values[4]	708	1			T6	8		T152	1		T222	5
values[5]	654	1			T9	16		T18	14		T149	12
values[6]	638	1			T100	1		T202	17		T203	12
values[7]	583	1			T3	20		T16	6		T100	2
values[8]	841	1			T139	12		T140	9		T199	24
values[9]	205	1			T134	9		T31	7		T32	20
minimum	17630	1			T1	20		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T132	14		T135	1		T261	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T140	7		T123	1		T51	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T131	1		T170	1		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	14		T31	3		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T131	1		T162	2		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T149	13		T30	14		T136	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T5	26		T9	1		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T133	2		T204	1		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	5		T222	4		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T152	1		T142	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T170	7		T208	3		T306	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	12		T18	14		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T202	8		T142	1		T171	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T100	1		T203	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T16	6		T100	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	20		T100	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T152	1		T219	13		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T139	1		T140	9		T199	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T134	9		T31	3		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T32	9		T308	1		T332	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17317	1			T1	20		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T97	1		T173	4		T229	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T132	14		T261	8		T262	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T123	6		T51	2		T171	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T192	6		T281	15		T301	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	2		T31	7		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T131	2		T172	10		T250	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T149	12		T30	15		T136	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T9	6		T12	11		T59	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T133	7		T143	3		T172	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	3		T222	1		T169	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T142	13		T248	16		T264	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T170	16		T94	9		T98	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	4		T149	11		T139	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T202	9		T142	8		T171	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T203	11		T122	1		T210	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T58	15		T244	12		T175	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T133	7		T31	17		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T51	7		T172	9		T61	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T139	11		T199	14		T169	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T31	4		T249	7		T307	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T32	10		T308	7		T332	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	9		T182	3		T171	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T229	4		T257	14		T283	17

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T32	1		T172	10		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T140	9		T199	10		T32	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T4	12		T277	13		T231	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	1		T309	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	11		T135	1		T171	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T123	1		T51	12		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T132	14		T170	1		T273	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	14		T31	3		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T131	1		T162	2		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T35	1		T33	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T131	1		T18	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T133	2		T149	13		T30	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T5	26		T6	5		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T204	1		T34	2		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T122	4		T170	7		T208	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	12		T18	14		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T202	8		T142	1		T171	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T139	1		T203	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T135	1		T298	1		T244	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	20		T100	2		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T16	6		T100	1		T134	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T139	1		T221	7		T53	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T172	9		T249	7		T276	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T199	14		T32	10		T169	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T277	14		T231	12		T357	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	8		T171	12		T261	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T123	6		T51	2		T146	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T132	14		T262	13		T281	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	2		T31	7		T171	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T250	8		T279	11		T311	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T33	1		T154	16		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T131	2		T172	10		T248	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T133	7		T149	12		T30	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T6	3		T9	6		T12	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T142	13		T248	16		T159	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T122	1		T170	16		T94	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	4		T149	11		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T202	9		T142	8		T171	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T139	12		T203	11		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T298	6		T244	12		T266	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T133	7		T31	17		T243	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T31	4		T51	7		T58	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T139	11		T228	6		T250	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T132	15		T135	1		T261	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T140	1		T123	7		T51	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T131	1		T170	1		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	3		T31	8		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T131	3		T162	2		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T149	13		T30	16		T136	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T5	3		T9	7		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T133	9		T204	1		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	5		T222	2		T169	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T152	1		T142	14		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T170	18		T208	3		T306	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	5		T18	2		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T202	10		T142	9		T171	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T100	1		T203	12		T122	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T16	1		T100	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	2		T100	1		T133	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T152	1		T219	1		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T139	12		T140	1		T199	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T134	1		T31	5		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T32	11		T308	8		T332	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17453	1			T1	20		T2	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T97	1		T173	1		T229	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T132	13		T261	5		T262	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T140	6		T51	11		T171	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T192	8		T301	6		T297	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	13		T31	2		T241	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T172	10		T274	6		T311	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T149	12		T30	13		T136	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	918	1			T5	23		T13	10		T17	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T143	3		T172	10		T241	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	3		T222	3		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T248	11		T264	11		T157	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T170	5		T94	12		T216	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	11		T18	12		T134	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T202	7		T171	11		T190	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T210	11		T167	12		T91	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T16	5		T58	13		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	18		T31	16		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T219	12		T51	12		T56	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T140	8		T199	9		T221	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T134	8		T31	2		T307	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T32	8		T332	9		T81	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T4	11		T9	9		T171	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T173	3		T229	2		T257	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T32	1		T172	10		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T140	1		T199	15		T32	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T4	1		T277	15		T231	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T247	3		T309	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	10		T135	1		T171	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T123	7		T51	3		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T132	15		T170	1		T273	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	3		T31	8		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	1		T162	2		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T35	1		T33	2		T154	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T131	3		T18	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T133	9		T149	13		T30	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T5	3		T6	5		T9	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T204	1		T34	2		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T122	4		T170	18		T208	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	5		T18	2		T149	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T202	10		T142	9		T171	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T139	13		T203	12		T122	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T135	1		T298	7		T244	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T3	2		T100	2		T133	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T16	1		T100	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T139	12		T221	1		T53	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T172	9		T276	8		T358	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T140	8		T199	9		T32	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T4	11		T277	12		T231	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T9	9		T171	2		T261	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	11		T146	7		T173	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T132	13		T262	13		T297	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	13		T31	2		T140	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T279	8		T311	11		T301	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T244	7		T252	3		T285	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T18	2		T172	10		T248	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T149	12		T30	13		T136	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T5	23		T6	3		T13	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T248	11		T157	19		T270	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T122	1		T170	5		T94	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	11		T18	12		T134	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T202	7		T171	11		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T167	12		T242	1		T313	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T244	10		T266	25		T278	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	18		T31	16		T243	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T16	5		T134	8		T31	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T221	6		T53	12		T56	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23