Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22302

1

T1

20

T2

20

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3227

1

T6

8

T9

16

T16

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20186

1

T1

20

T2

20

T3

6

auto[1]

5343

1

T3

14

T4

12

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	315	1			T134	6		T135	1		T140	9
values[0]	10	1			T281	6		T359	3		T360	1
values[1]	824	1			T9	16		T243	24		T222	5
values[2]	639	1			T18	3		T203	12		T53	1
values[3]	736	1			T3	14		T100	1		T133	8
values[4]	2418	1			T5	26		T9	2		T10	3
values[5]	748	1			T4	12		T6	8		T16	6
values[6]	442	1			T9	7		T134	9		T151	1
values[7]	494	1			T9	17		T11	16		T133	1
values[8]	573	1			T131	4		T149	25		T30	29
values[9]	967	1			T3	6		T133	8		T132	28
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	720	1			T9	16		T243	24		T222	5
values[1]	743	1			T133	8		T18	3		T139	13
values[2]	620	1			T3	14		T100	1		T18	1
values[3]	2487	1			T5	26		T6	8		T9	2
values[4]	711	1			T4	12		T9	7		T134	9
values[5]	422	1			T149	12		T199	24		T151	1
values[6]	582	1			T9	17		T11	16		T133	1
values[7]	524	1			T131	4		T30	29		T31	10
values[8]	929	1			T3	6		T133	8		T132	28
values[9]	182	1			T140	9		T169	10		T191	1
minimum	17609	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T222	4		T51	12		T261	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T9	12		T243	13		T58	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T133	1		T139	1		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T18	3		T203	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	14		T135	1		T51	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T100	1		T18	1		T31	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T5	26		T9	2		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	5		T16	6		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	12		T9	1		T134	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T139	1		T123	1		T58	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T149	1		T199	10		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T151	1		T32	9		T259	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	9		T11	14		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T149	13		T228	1		T156	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T131	2		T135	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T30	14		T31	3		T136	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	6		T132	14		T134	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T133	1		T204	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T140	9		T191	1		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T169	1		T241	8		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17296	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T298	1		T94	11		T98	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T222	1		T51	2		T261	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	4		T243	11		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T133	7		T139	12		T237	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T203	11		T91	2		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T51	7		T172	16		T248	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T31	17		T148	16		T174	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T12	11		T59	10		T193	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	3		T249	7		T229	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	6		T31	4		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T139	11		T123	6		T58	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T149	11		T199	14		T169	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T32	10		T259	8		T226	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	8		T11	2		T136	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T149	12		T228	3		T232	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T131	2		T122	1		T251	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T30	15		T31	7		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T132	14		T244	12		T265	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T133	7		T199	13		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T253	9		T254	1		T355	31
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T169	9		T246	13		T255	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	1		T182	3		T143	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T94	7		T98	1		T286	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T134	6		T140	9		T265	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T135	1		T169	2		T267	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T281	1		T360	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T359	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T222	4		T51	12		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T9	12		T243	13		T58	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T237	1		T273	1		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T18	3		T203	1		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	14		T133	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T100	1		T18	1		T162	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T5	26		T9	2		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T31	17		T150	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	12		T31	3		T140	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	5		T16	6		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	1		T134	9		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T151	1		T32	9		T171	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	9		T11	14		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T228	1		T156	13		T259	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T131	2		T135	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T149	13		T30	14		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T3	6		T132	14		T53	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T133	1		T204	1		T199	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T265	10		T271	4		T355	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T169	21		T250	9		T252	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T281	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T359	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T222	1		T51	2		T248	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	4		T243	11		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T237	12		T273	11		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T203	11		T142	13		T91	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T133	7		T139	12		T51	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T148	16		T174	13		T266	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T12	11		T59	10		T193	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T31	17		T249	7		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T31	4		T199	14		T237	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	3		T139	11		T123	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T9	6		T169	2		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T32	10		T171	12		T192	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	8		T11	2		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T228	3		T259	8		T226	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T131	2		T122	1		T251	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T149	12		T30	15		T31	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T132	14		T244	12		T293	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T133	7		T199	13		T142	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T222	2		T51	3		T261	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T9	5		T243	12		T58	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T133	8		T139	13		T237	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T18	1		T203	12		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	1		T135	1		T51	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T100	1		T18	1		T31	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T5	3		T9	1		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	5		T16	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	1		T9	7		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T139	12		T123	7		T58	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T149	12		T199	15		T169	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T151	1		T32	11		T259	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	9		T11	3		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T149	13		T228	4		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	4		T135	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T30	16		T31	8		T136	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T132	15		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T133	8		T204	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T140	1		T191	1		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T169	10		T241	1		T246	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17447	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T298	1		T94	8		T98	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T222	3		T51	11		T261	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	11		T243	12		T58	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T216	10		T257	14		T338	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T18	2		T56	10		T91	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	13		T51	12		T172	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T31	16		T148	12		T266	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T5	23		T9	1		T13	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T6	3		T16	5		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	11		T134	8		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T58	13		T171	2		T210	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T199	9		T91	12		T297	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T32	8		T226	1		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	8		T11	13		T18	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T149	12		T156	12		T173	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T53	12		T122	1		T241	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T30	13		T31	2		T136	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	5		T132	13		T134	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T199	9		T146	7		T267	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T140	8		T268	8		T355	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T241	7		T312	6		T255	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T248	11		T242	1		T342	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T94	10		T286	10		T258	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T134	1		T140	1		T265	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T135	1		T169	23		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T281	6		T360	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T359	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T222	2		T51	3		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	5		T243	12		T58	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T237	13		T273	12		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T18	1		T203	12		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	1		T133	8		T139	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T100	1		T18	1		T162	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T5	3		T9	1		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T31	18		T150	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	1		T31	5		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	5		T16	1		T139	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	7		T134	1		T169	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T151	1		T32	11		T171	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	9		T11	3		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T228	4		T156	1		T259	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T131	4		T135	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T149	13		T30	16		T31	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T3	1		T132	15		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T133	8		T204	1		T199	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T134	5		T140	8		T271	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T267	10		T320	6		T252	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T359	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T222	3		T51	11		T248	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	11		T243	12		T58	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T257	14		T175	11		T195	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T18	2		T56	10		T91	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	13		T51	12		T172	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T148	12		T266	2		T269	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T5	23		T9	1		T13	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T31	16		T229	2		T323	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T4	11		T31	2		T140	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	3		T16	5		T58	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T134	8		T91	12		T60	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T32	8		T171	2		T192	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	8		T11	13		T18	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T156	12		T226	1		T230	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T219	12		T122	1		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T149	12		T30	13		T31	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	5		T132	13		T53	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T199	9		T190	2		T146	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23