Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22462

1

T1

20

T2

20

T5

26

auto[ADC_CTRL_FILTER_COND_OUT]

3067

1

T3

20

T4

12

T9

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20173

1

T1

20

T2

20

T3

6

auto[1]

5356

1

T3

14

T4

12

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	338	1			T134	9		T152	1		T170	23
values[0]	42	1			T148	8		T305	16		T319	11
values[1]	702	1			T4	12		T140	7		T152	1
values[2]	2598	1			T5	26		T6	8		T9	18
values[3]	512	1			T9	17		T100	1		T133	8
values[4]	726	1			T3	6		T149	25		T31	34
values[5]	694	1			T133	8		T18	3		T132	28
values[6]	485	1			T34	2		T203	12		T51	14
values[7]	656	1			T134	6		T135	1		T94	6
values[8]	480	1			T135	1		T202	17		T136	22
values[9]	933	1			T3	14		T9	7		T16	6
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	660	1			T6	8		T9	16		T140	7
values[1]	2568	1			T5	26		T10	3		T11	16
values[2]	573	1			T9	19		T100	1		T133	8
values[3]	803	1			T3	6		T18	3		T149	25
values[4]	568	1			T133	8		T132	28		T149	12
values[5]	543	1			T134	6		T135	1		T34	2
values[6]	608	1			T32	1		T251	3		T273	1
values[7]	468	1			T16	6		T133	1		T31	10
values[8]	976	1			T3	14		T9	7		T100	1
values[9]	182	1			T140	9		T152	1		T90	1
minimum	17580	1			T1	20		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	5		T140	7		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	12		T56	6		T94	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T5	26		T10	3		T11	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T204	1		T237	1		T171	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	9		T100	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	2		T18	13		T199	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T149	13		T31	17		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	6		T18	3		T58	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T133	1		T132	14		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	1		T122	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T203	1		T51	12		T122	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T134	6		T135	1		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T251	1		T91	9		T146	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T32	1		T273	1		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T16	6		T133	1		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T202	8		T222	4		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T9	1		T100	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	14		T131	1		T170	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T140	9		T152	1		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T267	11		T229	7		T361	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17253	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T4	12		T58	14		T32	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	3		T142	8		T273	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	4		T94	2		T244	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T11	2		T12	11		T59	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T237	12		T171	4		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	8		T133	7		T30	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T199	13		T51	7		T169	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T149	12		T31	17		T169	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T171	10		T274	4		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T133	7		T132	14		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T122	1		T142	13		T298	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T203	11		T51	2		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T237	6		T228	1		T227	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T251	2		T91	2		T146	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T94	5		T281	5		T266	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T31	7		T136	6		T248	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T202	9		T222	1		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T9	6		T139	11		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T131	2		T170	16		T171	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T297	14		T196	1		T316	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T229	4		T362	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T182	3		T143	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T58	15		T32	10		T244	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T134	9		T152	1		T72	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T170	7		T153	2		T241	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T148	7		T305	8		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T318	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	7		T152	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	12		T56	6		T58	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T5	26		T6	5		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	14		T204	1		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	9		T100	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T18	13		T51	13		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T149	13		T31	17		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	6		T199	10		T171	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T133	1		T132	14		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T18	3		T135	1		T58	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T203	1		T51	12		T122	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T34	2		T53	13		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T146	8		T191	1		T265	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T134	6		T135	1		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T135	1		T136	16		T208	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T202	8		T32	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T9	1		T16	6		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	14		T131	1		T222	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T252	9		T363	5		T280	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T170	16		T265	6		T229	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T148	1		T305	8		T319	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T318	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T142	8		T91	10		T301	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T58	15		T32	10		T94	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T6	3		T11	2		T12	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	4		T169	9		T237	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	8		T133	7		T30	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T51	7		T169	2		T210	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T149	12		T31	17		T243	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T199	13		T171	10		T172	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T133	7		T132	14		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T142	13		T233	2		T259	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T203	11		T51	2		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T122	1		T237	6		T298	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T146	8		T265	20		T266	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T94	5		T228	1		T227	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T136	6		T251	2		T91	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T202	9		T167	12		T216	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T9	6		T31	7		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T131	2		T222	1		T171	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	5		T140	1		T142	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	5		T56	1		T94	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T5	3		T10	3		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T204	1		T237	13		T171	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	9		T100	1		T133	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	1		T18	1		T199	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T149	13		T31	18		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	1		T18	1		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T133	8		T132	15		T149	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T135	1		T122	2		T142	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T203	12		T51	3		T122	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T134	1		T135	1		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T251	3		T91	3		T146	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T32	1		T273	1		T94	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	1		T133	1		T31	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T202	10		T222	2		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T9	7		T100	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T131	3		T170	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T140	1		T152	1		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T267	1		T229	9		T361	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17405	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T4	1		T58	16		T32	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	3		T140	6		T91	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	11		T56	5		T94	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T5	23		T11	13		T13	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T171	11		T210	11		T143	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T9	8		T30	13		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	1		T18	12		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T149	12		T31	16		T172	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	5		T18	2		T58	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T132	13		T31	2		T56	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T66	5		T320	6		T276	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T51	11		T122	1		T154	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T134	5		T53	12		T228	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T91	8		T146	7		T157	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T320	12		T266	15		T277	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T16	5		T31	2		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T202	7		T222	3		T167	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T134	8		T136	1		T221	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	13		T170	5		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T140	8		T297	10		T321	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T267	10		T229	2		T362	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T292	1		T334	10		T74	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T4	11		T58	13		T32	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T134	1		T152	1		T72	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T170	18		T153	2		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T148	2		T305	9		T319	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T318	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T140	1		T152	1		T142	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	1		T56	1		T58	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T5	3		T6	5		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	6		T204	1		T169	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	9		T100	1		T133	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T18	1		T51	8		T169	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T149	13		T31	18		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T199	14		T171	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T133	8		T132	15		T149	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T18	1		T135	1		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T203	12		T51	3		T122	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T34	2		T53	1		T122	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T146	9		T191	1		T265	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T134	1		T135	1		T94	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T135	1		T136	7		T208	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T202	10		T32	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T9	7		T16	1		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T131	3		T222	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T134	8		T252	3		T280	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T170	5		T241	12		T267	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T148	6		T305	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T140	6		T91	12		T157	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	11		T56	5		T58	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T5	23		T6	3		T11	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	12		T171	11		T143	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T9	8		T30	13		T172	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T18	12		T51	12		T210	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T149	12		T31	16		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	5		T199	9		T171	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T132	13		T31	2		T56	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T18	2		T58	3		T66	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T51	11		T122	1		T154	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T53	12		T226	1		T274	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T146	7		T157	2		T266	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T134	5		T228	1		T266	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T136	15		T91	8		T323	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T202	7		T167	12		T216	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T16	5		T31	2		T140	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	13		T222	3		T171	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23