Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22481

1

T1

20

T2

20

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

3048

1

T3

20

T9

2

T100

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20271

1

T1

20

T2

20

T3

20

auto[1]

5258

1

T5

26

T6

8

T9

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	285	1			T199	24		T151	1		T202	17
values[0]	61	1			T170	23		T246	14		T326	24
values[1]	673	1			T4	12		T9	2		T100	2
values[2]	687	1			T3	6		T9	7		T133	1
values[3]	474	1			T131	3		T133	8		T134	6
values[4]	624	1			T3	14		T18	1		T31	7
values[5]	623	1			T9	17		T204	1		T139	13
values[6]	653	1			T6	8		T100	1		T133	8
values[7]	568	1			T31	34		T34	2		T142	9
values[8]	571	1			T11	16		T131	1		T134	9
values[9]	2947	1			T5	26		T9	16		T10	3
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	619	1			T4	12		T9	7		T100	1
values[1]	619	1			T3	6		T133	1		T203	12
values[2]	564	1			T3	14		T131	3		T133	8
values[3]	534	1			T9	17		T31	7		T139	12
values[4]	735	1			T100	1		T149	12		T204	1
values[5]	625	1			T6	8		T133	8		T31	34
values[6]	2467	1			T5	26		T10	3		T12	12
values[7]	620	1			T9	16		T11	16		T131	1
values[8]	908	1			T16	6		T132	28		T152	1
values[9]	183	1			T18	13		T199	24		T151	1
minimum	17655	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	12		T9	1		T18	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T100	1		T123	1		T56	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T133	1		T203	1		T136	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	6		T56	11		T171	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T131	1		T133	1		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	14		T210	12		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	9		T31	3		T51	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T139	1		T135	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T100	1		T149	1		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T204	1		T139	1		T214	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	5		T133	1		T31	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T199	10		T221	7		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T5	26		T10	3		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T169	1		T154	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	12		T11	14		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T149	13		T134	9		T243	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T16	6		T122	4		T162	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T132	14		T152	1		T222	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T18	13		T151	1		T202	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T199	10		T237	1		T307	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17279	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T9	2		T31	3		T219	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	6		T58	15		T94	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T123	6		T170	16		T167	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T203	11		T136	6		T51	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T171	14		T262	13		T264	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T131	2		T133	7		T136	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T210	4		T257	14		T274	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	8		T31	4		T51	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T139	11		T142	13		T91	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T149	11		T169	12		T265	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T139	12		T214	8		T251	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	3		T133	7		T31	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T199	13		T142	8		T233	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T12	11		T59	10		T193	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T169	9		T154	16		T145	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	4		T11	2		T237	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T149	12		T243	11		T172	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T122	1		T154	3		T94	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T132	14		T222	1		T32	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T202	9		T248	7		T216	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T199	14		T237	12		T307	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T9	1		T182	3		T171	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T31	7		T172	9		T148	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T151	1		T202	8		T216	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T199	10		T237	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T246	1		T326	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T170	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	12		T100	1		T18	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	2		T100	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T133	1		T203	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	6		T56	11		T171	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	1		T133	1		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T155	1		T244	1		T259	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T18	1		T31	3		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	14		T139	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	9		T50	1		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T204	1		T139	1		T214	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	5		T100	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T199	10		T221	7		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T31	17		T34	2		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T142	1		T154	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	14		T131	1		T30	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T134	9		T243	13		T140	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T5	26		T9	12		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T132	14		T149	13		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T202	9		T216	12		T272	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T199	14		T237	12		T142	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T246	13		T326	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T170	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T58	15		T171	12		T94	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T31	7		T123	6		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	6		T203	11		T51	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T171	14		T262	13		T228	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T131	2		T133	7		T136	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T259	8		T257	14		T333	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T31	4		T136	11		T51	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T139	11		T142	13		T210	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T9	8		T169	12		T233	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T139	12		T214	8		T251	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	3		T133	7		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T199	13		T266	16		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T31	17		T266	13		T284	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T142	8		T154	16		T145	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	2		T30	15		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T243	11		T169	9		T216	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T9	4		T12	11		T59	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T132	14		T149	12		T222	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T9	7		T18	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T100	1		T123	7		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T133	1		T203	12		T136	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T56	1		T171	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T131	3		T133	8		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	1		T210	5		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	9		T31	5		T51	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T139	12		T135	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T100	1		T149	12		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T204	1		T139	13		T214	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	5		T133	8		T31	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T199	14		T221	1		T142	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T5	3		T10	3		T12	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T169	10		T154	17		T145	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T9	5		T11	3		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T149	13		T134	1		T243	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T16	1		T122	4		T162	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T132	15		T152	1		T222	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T18	1		T151	1		T202	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T199	15		T237	13		T307	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17473	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T9	1		T31	8		T219	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	11		T18	2		T58	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T56	5		T170	5		T167	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T136	15		T51	12		T91	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T3	5		T56	10		T171	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T134	5		T140	6		T136	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T3	13		T210	11		T257	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	8		T31	2		T51	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T91	8		T241	12		T286	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T60	2		T320	6		T230	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T214	9		T146	7		T228	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	3		T31	16		T53	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T199	9		T221	6		T241	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T5	23		T13	10		T17	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T148	6		T279	8		T330	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	11		T11	13		T248	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T149	12		T134	8		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T16	5		T122	1		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T132	13		T222	3		T32	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T18	12		T202	7		T248	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T199	9		T307	7		T331	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T171	2		T244	7		T332	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T9	1		T31	2		T219	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T151	1		T202	10		T216	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T199	15		T237	13		T142	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T246	14		T326	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T170	18		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	1		T100	1		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	1		T100	1		T31	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T9	7		T133	1		T203	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	1		T56	1		T171	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T131	3		T133	8		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T155	1		T244	1		T259	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T18	1		T31	5		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	1		T139	12		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	9		T50	1		T169	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T204	1		T139	13		T214	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	5		T100	1		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T199	14		T221	1		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T31	18		T34	2		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T142	9		T154	17		T145	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	3		T131	1		T30	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T134	1		T243	12		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T5	3		T9	5		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T132	15		T149	13		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T202	7		T216	10		T157	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T199	9		T312	6		T278	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T326	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T170	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T4	11		T18	2		T58	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	1		T31	2		T219	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T51	12		T143	3		T91	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	5		T56	10		T171	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T134	5		T136	15		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T257	14		T333	12		T357	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T31	2		T140	6		T136	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	13		T210	11		T91	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	8		T320	6		T230	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T214	9		T146	7		T228	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	3		T53	12		T261	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T199	9		T221	6		T241	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T31	16		T266	2		T284	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T148	6		T279	19		T323	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	13		T30	13		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T134	8		T243	12		T140	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T5	23		T9	11		T13	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T132	13		T149	12		T222	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23