Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T149	13		T31	18		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T123	7		T169	3		T72	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T5	3		T10	3		T12	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	1		T34	2		T170	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T6	5		T9	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T100	1		T134	1		T251	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	7		T149	12		T172	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T199	14		T152	2		T171	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	1		T133	8		T122	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T100	1		T139	12		T222	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T131	3		T18	1		T136	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T100	1		T133	8		T199	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T133	1		T134	1		T139	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T204	1		T151	1		T203	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T9	9		T11	3		T132	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	1		T31	5		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T18	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T30	16		T135	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T153	1		T172	11		T248	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T205	1		T266	12		T272	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T219	1		T58	1		T90	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T149	12		T31	16		T154	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T257	22		T252	10		T269	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T5	23		T13	10		T16	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T170	5		T214	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	5		T6	3		T9	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T134	8		T157	9		T274	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T172	9		T248	11		T228	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T199	9		T171	11		T192	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T4	11		T167	12		T228	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T222	3		T56	5		T171	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T18	2		T136	15		T171	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T199	9		T221	6		T262	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T134	5		T143	3		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T51	11		T32	8		T91	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	8		T11	13		T132	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T31	2		T192	8		T244	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	13		T18	12		T140	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T30	13		T140	8		T94	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T172	10		T248	4		T188	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T266	10		T272	10		T282	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T31	2		T148	6		T283	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T219	12		T58	3		T157	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	554	1			T3	1		T6	8		T14	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T53	1		T142	14		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T206	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T149	13		T31	8		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T219	1		T58	1		T169	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T5	3		T6	5		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	1		T34	2		T123	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	5		T16	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T100	1		T134	1		T251	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T9	7		T149	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T199	14		T152	1		T208	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T122	2		T142	23		T172	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T100	1		T139	12		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T131	3		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T133	8		T169	13		T262	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T133	1		T132	15		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T100	1		T204	1		T199	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T11	3		T139	13		T202	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T131	1		T203	12		T51	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	9		T18	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T30	16		T31	5		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16917	1			T1	20		T2	20		T6	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T3	13		T279	11		T284	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T173	3		T266	10		T280	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T149	12		T31	2		T148	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T219	12		T58	3		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T5	23		T6	3		T13	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T170	5		T214	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	11		T16	5		T53	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T134	8		T274	4		T285	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	5		T51	12		T56	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T199	9		T157	9		T286	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T172	9		T228	5		T148	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T222	3		T56	5		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	11		T18	2		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T262	13		T60	2		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T132	13		T134	5		T171	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T199	9		T221	6		T32	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	13		T202	7		T136	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T51	11		T244	7		T286	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	8		T18	12		T140	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	13		T31	2		T140	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23