Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22659

1

T1

20

T2

20

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

2870

1

T9

19

T16

6

T100

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19869

1

T1

20

T2

20

T4

12

auto[1]

5660

1

T3

20

T5

26

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	492	1			T6	8		T14	5		T19	11
values[0]	65	1			T90	1		T269	18		T232	17
values[1]	642	1			T149	25		T31	10		T150	1
values[2]	2507	1			T5	26		T6	8		T9	2
values[3]	574	1			T9	16		T16	6		T100	1
values[4]	668	1			T3	6		T9	7		T100	1
values[5]	595	1			T4	12		T139	12		T152	1
values[6]	566	1			T131	3		T133	16		T18	3
values[7]	614	1			T100	1		T133	1		T132	28
values[8]	769	1			T11	16		T131	1		T139	13
values[9]	1120	1			T3	14		T9	17		T18	13
minimum	16917	1			T1	20		T2	20		T6	160

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	882	1			T149	25		T31	44		T150	1
values[1]	2501	1			T5	26		T9	2		T10	3
values[2]	621	1			T3	6		T6	8		T9	16
values[3]	596	1			T9	7		T149	12		T199	23
values[4]	603	1			T4	12		T100	1		T133	8
values[5]	592	1			T100	1		T131	3		T133	8
values[6]	703	1			T133	1		T132	28		T134	6
values[7]	612	1			T9	17		T11	16		T31	7
values[8]	828	1			T3	14		T131	1		T30	29
values[9]	216	1			T18	13		T135	2		T33	2
minimum	17375	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T31	3		T150	1		T58	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T149	13		T31	17		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T5	26		T10	3		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	2		T16	6		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	6		T6	5		T9	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T152	1		T32	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	1		T149	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T199	10		T192	2		T228	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	12		T100	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T139	1		T152	1		T56	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T131	1		T133	1		T18	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T100	1		T199	10		T221	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T132	14		T134	6		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T133	1		T204	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	14		T202	8		T136	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	9		T31	3		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	14		T140	7		T251	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T131	1		T30	14		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T18	13		T135	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T135	1		T33	1		T248	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17217	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T148	7		T287	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T31	7		T169	2		T154	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T149	12		T31	17		T123	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T12	11		T59	10		T193	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T58	15		T170	16		T65	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	3		T9	4		T51	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T251	13		T273	11		T274	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	6		T149	11		T122	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T199	13		T192	4		T228	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T133	7		T171	12		T167	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T139	11		T142	21		T94	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T131	2		T133	7		T136	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T199	14		T169	12		T262	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T132	14		T139	12		T143	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T203	11		T51	2		T32	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	2		T202	9		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T9	8		T31	4		T244	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T251	2		T192	6		T288	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T30	15		T122	1		T142	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T172	10		T266	11		T282	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T33	1		T248	7		T264	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T148	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	467	1			T6	8		T14	5		T19	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T191	1		T289	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T90	1		T269	18		T232	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T31	3		T150	1		T58	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T149	13		T219	13		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T5	26		T6	5		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	2		T31	17		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	12		T100	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T16	6		T58	14		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	6		T9	1		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T199	10		T152	1		T273	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	12		T222	4		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T139	1		T152	1		T56	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T131	1		T133	2		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T169	1		T94	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T132	14		T134	6		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T100	1		T133	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	14		T139	1		T202	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T131	1		T203	1		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T3	14		T18	13		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T9	9		T30	14		T31	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16770	1			T1	20		T2	20		T6	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T290	11		T85	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T289	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T232	6		T260	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T31	7		T169	2		T154	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T149	12		T148	1		T244	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	915	1			T6	3		T12	11		T59	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T31	17		T123	6		T170	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	4		T237	12		T214	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T58	15		T251	13		T281	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	6		T149	11		T51	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T199	13		T273	11		T228	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T222	1		T122	1		T171	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T139	11		T142	21		T146	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T131	2		T133	14		T136	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T169	12		T94	5		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T132	14		T237	6		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T199	14		T32	10		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T11	2		T139	12		T202	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T203	11		T51	2		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T251	2		T172	10		T192	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	8		T30	15		T31	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T31	8		T150	1		T58	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T149	13		T31	18		T123	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T5	3		T10	3		T12	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	1		T16	1		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T6	5		T9	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T152	1		T32	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	7		T149	12		T122	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T199	14		T192	5		T228	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	1		T100	1		T133	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T139	12		T152	1		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T131	3		T133	8		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T100	1		T199	15		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T132	15		T134	1		T139	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T133	1		T204	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	3		T202	10		T136	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	9		T31	5		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T3	1		T140	1		T251	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T131	1		T30	16		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T18	1		T135	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T135	1		T33	2		T248	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17364	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T148	2		T287	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T31	2		T58	3		T154	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T149	12		T31	16		T219	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T5	23		T13	10		T17	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T16	5		T58	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	5		T6	3		T9	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T267	10		T157	9		T274	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T171	11		T172	9		T248	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T199	9		T192	1		T228	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	11		T171	2		T167	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T56	5		T146	7		T241	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T18	2		T136	15		T222	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T199	9		T221	6		T262	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T132	13		T134	5		T143	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T51	11		T32	8		T91	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	13		T202	7		T136	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T9	8		T31	2		T140	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	13		T140	6		T192	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T30	13		T122	1		T94	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T18	12		T172	10		T266	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T248	4		T264	2		T279	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T148	6		T287	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	468	1			T6	8		T14	5		T19	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T191	1		T289	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T90	1		T269	1		T232	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T31	8		T150	1		T58	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T149	13		T219	1		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T5	3		T6	5		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T31	18		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	5		T100	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	1		T58	16		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T9	7		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T199	14		T152	1		T273	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T222	2		T122	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T139	12		T152	1		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T131	3		T133	16		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T169	13		T94	6		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T132	15		T134	1		T237	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T100	1		T133	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	3		T139	13		T202	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T131	1		T203	12		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T3	1		T18	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T9	9		T30	16		T31	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16917	1			T1	20		T2	20		T6	160
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T290	11		T85	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T269	17		T232	7		T287	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T31	2		T58	3		T257	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T149	12		T219	12		T148	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	943	1			T5	23		T6	3		T13	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	1		T31	16		T170	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	11		T134	8		T53	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T16	5		T58	13		T285	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	5		T51	12		T56	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T199	9		T228	1		T267	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T4	11		T222	3		T171	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T56	5		T146	7		T192	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T18	2		T136	15		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T156	12		T291	2		T292	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T132	13		T134	5		T171	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T199	9		T221	6		T32	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	13		T202	7		T136	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T51	11		T122	1		T293	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	13		T18	12		T140	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	8		T30	13		T31	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23