Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22562

1

T1

20

T2

20

T5

26

auto[ADC_CTRL_FILTER_COND_OUT]

2967

1

T3

20

T4

12

T9

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20158

1

T1

20

T2

20

T4

12

auto[1]

5371

1

T3

20

T5

26

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T207	27		-	-		-	-
values[0]	73	1			T131	3		T199	23		T294	1
values[1]	587	1			T11	16		T16	6		T100	1
values[2]	538	1			T100	1		T132	28		T149	12
values[3]	607	1			T3	14		T134	9		T150	1
values[4]	492	1			T9	16		T131	1		T134	6
values[5]	2599	1			T5	26		T9	9		T10	3
values[6]	655	1			T30	29		T199	24		T34	2
values[7]	602	1			T3	6		T100	1		T31	34
values[8]	536	1			T4	12		T9	17		T204	1
values[9]	1450	1			T6	8		T133	9		T18	16
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	704	1			T11	16		T16	6		T100	1
values[1]	689	1			T100	1		T132	28		T149	12
values[2]	559	1			T3	14		T131	1		T134	6
values[3]	2573	1			T5	26		T9	18		T10	3
values[4]	614	1			T9	7		T133	8		T18	1
values[5]	519	1			T3	6		T30	29		T31	34
values[6]	657	1			T4	12		T135	1		T151	1
values[7]	494	1			T100	1		T204	1		T139	13
values[8]	1220	1			T6	8		T9	17		T133	9
values[9]	134	1			T18	3		T140	7		T214	18
minimum	17366	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T16	6		T100	1		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	14		T149	13		T199	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T132	14		T149	1		T134	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T100	1		T152	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T131	1		T134	6		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	14		T140	9		T32	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T5	26		T9	12		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	2		T56	6		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	1		T31	3		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T133	1		T18	1		T31	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	14		T123	1		T56	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	6		T31	17		T199	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T135	1		T152	1		T219	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	12		T151	1		T58	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T139	1		T243	13		T222	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T100	1		T204	1		T203	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T6	5		T133	2		T18	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	9		T122	4		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T18	3		T140	7		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T214	10		T296	1		T297	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T230	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T131	2		T171	4		T261	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	2		T149	12		T199	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T132	14		T149	11		T139	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T298	6		T94	7		T228	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T142	13		T248	16		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	10		T192	4		T226	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T9	4		T12	11		T59	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T33	1		T91	17		T190	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	6		T31	4		T169	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	7		T31	7		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T30	15		T123	6		T65	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T31	17		T199	14		T51	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T142	8		T251	2		T249	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T58	15		T142	13		T143	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T139	12		T243	11		T222	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T203	11		T171	10		T154	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T6	3		T133	7		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	8		T122	1		T172	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T159	14		T81	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T214	8		T297	14		T299	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T207	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T131	1		T271	3		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T199	10		T294	1		T301	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	6		T100	1		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	14		T149	13		T136	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T132	14		T149	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T100	1		T94	11		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T134	9		T150	1		T51	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	14		T140	9		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	12		T131	1		T134	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T56	6		T32	9		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T5	26		T9	1		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	2		T133	1		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	14		T123	1		T56	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T199	10		T34	2		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T135	1		T152	1		T219	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	6		T100	1		T31	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T139	1		T243	13		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	12		T9	9		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	400	1			T6	5		T133	2		T18	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T122	4		T171	12		T214	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T207	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T131	2		T271	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T199	13		T301	6		T302	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T171	4		T261	8		T244	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	2		T149	12		T136	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T132	14		T149	11		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T94	7		T230	1		T303	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T51	7		T142	13		T228	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T298	6		T226	1		T271	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T9	4		T202	9		T248	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T32	10		T33	1		T190	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T9	6		T12	11		T59	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T133	7		T31	7		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T30	15		T123	6		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T199	14		T51	2		T237	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T142	8		T251	2		T192	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T31	17		T142	13		T143	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T139	12		T243	11		T265	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	8		T203	11		T58	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	411	1			T6	3		T133	7		T136	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T122	1		T171	10		T214	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T16	1		T100	1		T131	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	3		T149	13		T199	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T132	15		T149	12		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T100	1		T152	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T131	1		T134	1		T142	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	1		T140	1		T32	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T5	3		T9	5		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	1		T56	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	7		T31	5		T169	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T133	8		T18	1		T31	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T30	16		T123	7		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T3	1		T31	18		T199	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T135	1		T152	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	1		T151	1		T58	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T139	13		T243	12		T222	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T100	1		T204	1		T203	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	435	1			T6	5		T133	9		T18	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T9	9		T122	4		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T18	1		T140	1		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T214	9		T296	1		T297	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T230	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	5		T171	11		T261	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	13		T149	12		T199	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T132	13		T134	8		T221	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T94	10		T146	3		T228	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T134	5		T248	11		T228	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	13		T140	8		T32	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T5	23		T9	11		T13	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T9	1		T56	5		T91	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T31	2		T210	11		T61	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T31	2		T192	8		T288	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T30	13		T56	10		T65	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T3	5		T31	16		T199	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T219	12		T60	2		T156	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	11		T58	13		T143	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T243	12		T222	3		T252	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T171	11		T91	12		T264	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T6	3		T18	12		T136	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	8		T122	1		T172	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T18	2		T140	6		T81	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T214	9		T297	10		T299	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T230	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T207	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T131	3		T271	5		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T199	14		T294	1		T301	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	1		T100	1		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	3		T149	13		T136	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T132	15		T149	12		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T100	1		T94	8		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T134	1		T150	1		T51	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	1		T140	1		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T9	5		T131	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T56	1		T32	11		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T5	3		T9	7		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	1		T133	8		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T30	16		T123	7		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T199	15		T34	2		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T135	1		T152	1		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	1		T100	1		T31	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T139	13		T243	12		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	1		T9	9		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	499	1			T6	5		T133	9		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T122	4		T171	11		T214	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T207	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T271	2		T304	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T199	9		T301	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T16	5		T171	11		T261	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	13		T149	12		T136	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T132	13		T221	6		T170	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T94	10		T157	10		T263	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T134	8		T51	12		T228	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	13		T140	8		T146	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T9	11		T134	5		T202	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T56	5		T32	8		T190	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T5	23		T13	10		T17	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	1		T31	2		T91	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T30	13		T56	10		T65	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T199	9		T51	11		T146	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T219	12		T148	6		T156	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	5		T31	16		T143	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T243	12		T60	2		T173	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	11		T9	8		T58	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T6	3		T18	14		T140	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T122	1		T171	11		T214	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23