CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 25529 | 1 | T1 | 20 | T2 | 20 | T3 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 22482 | 1 | T1 | 20 | T2 | 20 | T5 | 26 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3047 | 1 | T3 | 20 | T4 | 12 | T9 | 18 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 20156 | 1 | T1 | 20 | T2 | 20 | T3 | 6 | ||||
auto[1] | 5373 | 1 | T3 | 14 | T4 | 12 | T5 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21653 | 1 | T1 | 20 | T2 | 20 | T3 | 20 | ||||
auto[1] | 3876 | 1 | T6 | 3 | T9 | 19 | T11 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 34 | 1 | T153 | 1 | T314 | 33 | - | - | ||||
values[0] | 79 | 1 | T315 | 1 | T148 | 8 | T242 | 6 | ||||
values[1] | 635 | 1 | T4 | 12 | T152 | 1 | T56 | 6 | ||||
values[2] | 2629 | 1 | T5 | 26 | T6 | 8 | T9 | 18 | ||||
values[3] | 464 | 1 | T9 | 17 | T100 | 1 | T18 | 13 | ||||
values[4] | 779 | 1 | T3 | 6 | T133 | 8 | T149 | 25 | ||||
values[5] | 655 | 1 | T133 | 8 | T18 | 3 | T132 | 28 | ||||
values[6] | 524 | 1 | T203 | 12 | T51 | 14 | T53 | 13 | ||||
values[7] | 664 | 1 | T134 | 6 | T135 | 1 | T34 | 2 | ||||
values[8] | 455 | 1 | T135 | 1 | T202 | 17 | T32 | 1 | ||||
values[9] | 1248 | 1 | T3 | 14 | T9 | 7 | T16 | 6 | ||||
minimum | 17363 | 1 | T1 | 20 | T2 | 20 | T6 | 168 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 903 | 1 | T4 | 12 | T6 | 8 | T9 | 16 | ||||
values[1] | 2541 | 1 | T5 | 26 | T10 | 3 | T11 | 16 | ||||
values[2] | 634 | 1 | T9 | 19 | T100 | 1 | T133 | 8 | ||||
values[3] | 682 | 1 | T3 | 6 | T18 | 3 | T149 | 25 | ||||
values[4] | 613 | 1 | T133 | 8 | T132 | 28 | T149 | 12 | ||||
values[5] | 505 | 1 | T134 | 6 | T135 | 1 | T34 | 2 | ||||
values[6] | 688 | 1 | T53 | 13 | T33 | 1 | T298 | 1 | ||||
values[7] | 459 | 1 | T16 | 6 | T133 | 1 | T31 | 10 | ||||
values[8] | 954 | 1 | T3 | 14 | T9 | 7 | T100 | 1 | ||||
values[9] | 175 | 1 | T140 | 9 | T152 | 1 | T90 | 1 | ||||
minimum | 17375 | 1 | T1 | 20 | T2 | 20 | T6 | 168 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22094 | 1 | T1 | 20 | T2 | 20 | T3 | 2 | ||||
auto[1] | 3435 | 1 | T3 | 18 | T4 | 11 | T5 | 23 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 6 | 42 | 87.50 | 6 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 | |
* | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | -- | -- | 2 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 180 | 1 | T6 | 5 | T18 | 1 | T140 | 7 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 291 | 1 | T4 | 12 | T9 | 12 | T56 | 6 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 1285 | 1 | T5 | 26 | T10 | 3 | T11 | 14 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 134 | 1 | T18 | 13 | T204 | 1 | T237 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T9 | 9 | T100 | 1 | T133 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 171 | 1 | T9 | 2 | T199 | 10 | T51 | 13 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 171 | 1 | T149 | 13 | T31 | 17 | T150 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 229 | 1 | T3 | 6 | T18 | 3 | T58 | 4 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 145 | 1 | T133 | 1 | T132 | 14 | T149 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 179 | 1 | T135 | 1 | T122 | 1 | T142 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 160 | 1 | T203 | 1 | T51 | 12 | T122 | 4 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 108 | 1 | T134 | 6 | T135 | 1 | T34 | 2 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 173 | 1 | T91 | 9 | T146 | 8 | T174 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 186 | 1 | T53 | 13 | T33 | 1 | T298 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 117 | 1 | T16 | 6 | T133 | 1 | T31 | 3 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 127 | 1 | T202 | 8 | T32 | 1 | T33 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 264 | 1 | T9 | 1 | T100 | 1 | T131 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 240 | 1 | T3 | 14 | T131 | 1 | T222 | 4 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 87 | 1 | T140 | 9 | T152 | 1 | T90 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 26 | 1 | T267 | 11 | T229 | 7 | T274 | 4 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17228 | 1 | T1 | 20 | T2 | 20 | T6 | 168 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 206 | 1 | T6 | 3 | T142 | 8 | T154 | 16 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 226 | 1 | T9 | 4 | T58 | 15 | T32 | 10 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 972 | 1 | T11 | 2 | T12 | 11 | T59 | 10 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 150 | 1 | T237 | 12 | T210 | 4 | T145 | 17 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 153 | 1 | T9 | 8 | T133 | 7 | T30 | 15 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 158 | 1 | T199 | 13 | T51 | 7 | T169 | 11 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 130 | 1 | T149 | 12 | T31 | 17 | T169 | 12 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T171 | 10 | T274 | 4 | T231 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 147 | 1 | T133 | 7 | T132 | 14 | T149 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 142 | 1 | T122 | 1 | T142 | 13 | T298 | 6 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 137 | 1 | T203 | 11 | T51 | 2 | T122 | 1 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 100 | 1 | T237 | 6 | T228 | 1 | T286 | 1 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 193 | 1 | T91 | 2 | T146 | 8 | T174 | 13 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 136 | 1 | T94 | 5 | T281 | 5 | T266 | 16 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 114 | 1 | T31 | 7 | T136 | 6 | T251 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 101 | 1 | T202 | 9 | T33 | 1 | T167 | 12 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 264 | 1 | T9 | 6 | T139 | 11 | T136 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 186 | 1 | T131 | 2 | T222 | 1 | T170 | 16 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 57 | 1 | T297 | 14 | T196 | 1 | T316 | 13 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 5 | 1 | T229 | 4 | T317 | 1 | - | - | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 147 | 1 | T9 | 1 | T182 | 3 | T143 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 3 | 45 | 93.75 | 3 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 14 | 1 | T314 | 14 | - | - | - | - | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T153 | 1 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 18 | 1 | T315 | 1 | T148 | 7 | T305 | 8 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 17 | 1 | T242 | 5 | T284 | 11 | T318 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 145 | 1 | T152 | 1 | T142 | 1 | T91 | 13 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T4 | 12 | T56 | 6 | T58 | 14 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 1305 | 1 | T5 | 26 | T6 | 5 | T10 | 3 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 170 | 1 | T9 | 14 | T204 | 1 | T169 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 104 | 1 | T9 | 9 | T100 | 1 | T182 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 147 | 1 | T18 | 13 | T51 | 13 | T169 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 189 | 1 | T133 | 1 | T149 | 13 | T30 | 14 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 229 | 1 | T3 | 6 | T199 | 10 | T171 | 12 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 160 | 1 | T133 | 1 | T132 | 14 | T149 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 215 | 1 | T18 | 3 | T135 | 1 | T58 | 4 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 135 | 1 | T203 | 1 | T51 | 12 | T154 | 7 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 122 | 1 | T53 | 13 | T122 | 1 | T237 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 197 | 1 | T122 | 4 | T146 | 8 | T191 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 155 | 1 | T134 | 6 | T135 | 1 | T34 | 2 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 95 | 1 | T135 | 1 | T208 | 3 | T251 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T202 | 8 | T32 | 1 | T33 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 384 | 1 | T9 | 1 | T16 | 6 | T100 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 291 | 1 | T3 | 14 | T131 | 1 | T222 | 4 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17216 | 1 | T1 | 20 | T2 | 20 | T6 | 168 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 19 | 1 | T314 | 19 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 19 | 1 | T148 | 1 | T305 | 8 | T319 | 10 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 25 | 1 | T242 | 1 | T284 | 18 | T318 | 6 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 144 | 1 | T142 | 8 | T91 | 10 | T301 | 6 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 154 | 1 | T58 | 15 | T32 | 10 | T94 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 968 | 1 | T6 | 3 | T11 | 2 | T12 | 11 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 186 | 1 | T9 | 4 | T169 | 9 | T237 | 12 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 112 | 1 | T9 | 8 | T172 | 7 | T262 | 13 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 101 | 1 | T51 | 7 | T169 | 2 | T210 | 4 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 179 | 1 | T133 | 7 | T149 | 12 | T30 | 15 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 182 | 1 | T199 | 13 | T171 | 10 | T172 | 9 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 141 | 1 | T133 | 7 | T132 | 14 | T149 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 139 | 1 | T142 | 13 | T233 | 2 | T259 | 8 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 142 | 1 | T203 | 11 | T51 | 2 | T154 | 3 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 125 | 1 | T122 | 1 | T237 | 6 | T298 | 6 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 201 | 1 | T122 | 1 | T146 | 8 | T227 | 1 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 111 | 1 | T94 | 5 | T228 | 1 | T286 | 1 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 83 | 1 | T251 | 2 | T91 | 2 | T190 | 5 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 125 | 1 | T202 | 9 | T167 | 12 | T216 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 365 | 1 | T9 | 6 | T31 | 7 | T139 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 208 | 1 | T131 | 2 | T222 | 1 | T170 | 16 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 147 | 1 | T9 | 1 | T182 | 3 | T143 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 6 | 42 | 87.50 | 6 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 | |
* | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | -- | -- | 2 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 263 | 1 | T6 | 5 | T18 | 1 | T140 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 284 | 1 | T4 | 1 | T9 | 5 | T56 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 1287 | 1 | T5 | 3 | T10 | 3 | T11 | 3 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T18 | 1 | T204 | 1 | T237 | 13 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 185 | 1 | T9 | 9 | T100 | 1 | T133 | 8 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T9 | 1 | T199 | 14 | T51 | 8 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 163 | 1 | T149 | 13 | T31 | 18 | T150 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 197 | 1 | T3 | 1 | T18 | 1 | T58 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 176 | 1 | T133 | 8 | T132 | 15 | T149 | 12 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 188 | 1 | T135 | 1 | T122 | 2 | T142 | 14 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 183 | 1 | T203 | 12 | T51 | 3 | T122 | 4 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 130 | 1 | T134 | 1 | T135 | 1 | T34 | 2 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 227 | 1 | T91 | 3 | T146 | 9 | T174 | 14 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 172 | 1 | T53 | 1 | T33 | 1 | T298 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 146 | 1 | T16 | 1 | T133 | 1 | T31 | 8 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 126 | 1 | T202 | 10 | T32 | 1 | T33 | 2 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 323 | 1 | T9 | 7 | T100 | 1 | T131 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 226 | 1 | T3 | 1 | T131 | 3 | T222 | 2 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 71 | 1 | T140 | 1 | T152 | 1 | T90 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 16 | 1 | T267 | 1 | T229 | 9 | T274 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17364 | 1 | T1 | 20 | T2 | 20 | T6 | 168 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 123 | 1 | T6 | 3 | T140 | 6 | T91 | 12 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 233 | 1 | T4 | 11 | T9 | 11 | T56 | 5 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 970 | 1 | T5 | 23 | T11 | 13 | T13 | 10 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 109 | 1 | T18 | 12 | T210 | 11 | T156 | 8 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 120 | 1 | T9 | 8 | T30 | 13 | T243 | 12 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 137 | 1 | T9 | 1 | T199 | 9 | T51 | 12 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 138 | 1 | T149 | 12 | T31 | 16 | T172 | 10 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 184 | 1 | T3 | 5 | T18 | 2 | T58 | 3 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 116 | 1 | T132 | 13 | T31 | 2 | T56 | 10 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 133 | 1 | T66 | 5 | T320 | 6 | T276 | 2 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 114 | 1 | T51 | 11 | T122 | 1 | T264 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 78 | 1 | T134 | 5 | T228 | 1 | T226 | 1 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 139 | 1 | T91 | 8 | T146 | 7 | T157 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 150 | 1 | T53 | 12 | T320 | 12 | T266 | 15 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 85 | 1 | T16 | 5 | T31 | 2 | T136 | 15 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 102 | 1 | T202 | 7 | T167 | 12 | T216 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 205 | 1 | T134 | 8 | T136 | 1 | T221 | 6 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 200 | 1 | T3 | 13 | T222 | 3 | T170 | 5 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 73 | 1 | T140 | 8 | T297 | 10 | T321 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 15 | 1 | T267 | 10 | T229 | 2 | T274 | 3 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 11 | 1 | T322 | 11 | - | - | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 20 | 1 | T314 | 20 | - | - | - | - | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T153 | 1 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 24 | 1 | T315 | 1 | T148 | 2 | T305 | 9 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 31 | 1 | T242 | 5 | T284 | 19 | T318 | 7 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 187 | 1 | T152 | 1 | T142 | 9 | T91 | 11 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T4 | 1 | T56 | 1 | T58 | 16 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 1288 | 1 | T5 | 3 | T6 | 5 | T10 | 3 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 217 | 1 | T9 | 6 | T204 | 1 | T169 | 10 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 136 | 1 | T9 | 9 | T100 | 1 | T182 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 128 | 1 | T18 | 1 | T51 | 8 | T169 | 3 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 217 | 1 | T133 | 8 | T149 | 13 | T30 | 16 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 227 | 1 | T3 | 1 | T199 | 14 | T171 | 11 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 171 | 1 | T133 | 8 | T132 | 15 | T149 | 12 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 182 | 1 | T18 | 1 | T135 | 1 | T58 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 182 | 1 | T203 | 12 | T51 | 3 | T154 | 4 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 161 | 1 | T53 | 1 | T122 | 2 | T237 | 7 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 244 | 1 | T122 | 4 | T146 | 9 | T191 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 145 | 1 | T134 | 1 | T135 | 1 | T34 | 2 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 112 | 1 | T135 | 1 | T208 | 3 | T251 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 153 | 1 | T202 | 10 | T32 | 1 | T33 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 444 | 1 | T9 | 7 | T16 | 1 | T100 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 266 | 1 | T3 | 1 | T131 | 3 | T222 | 2 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17363 | 1 | T1 | 20 | T2 | 20 | T6 | 168 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T314 | 13 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T148 | 6 | T305 | 7 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 11 | 1 | T242 | 1 | T284 | 10 | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 102 | 1 | T91 | 12 | T157 | 9 | T301 | 6 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 151 | 1 | T4 | 11 | T56 | 5 | T58 | 13 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 985 | 1 | T5 | 23 | T6 | 3 | T11 | 13 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 139 | 1 | T9 | 12 | T171 | 11 | T143 | 3 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 80 | 1 | T9 | 8 | T172 | 10 | T262 | 13 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 120 | 1 | T18 | 12 | T51 | 12 | T210 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T149 | 12 | T30 | 13 | T31 | 16 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 184 | 1 | T3 | 5 | T199 | 9 | T171 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 130 | 1 | T132 | 13 | T31 | 2 | T56 | 10 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 172 | 1 | T18 | 2 | T58 | 3 | T66 | 5 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 95 | 1 | T51 | 11 | T154 | 6 | T148 | 12 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 86 | 1 | T53 | 12 | T226 | 1 | T274 | 6 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 154 | 1 | T122 | 1 | T146 | 7 | T157 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 121 | 1 | T134 | 5 | T228 | 1 | T266 | 15 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 66 | 1 | T91 | 8 | T190 | 2 | T323 | 1 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 124 | 1 | T202 | 7 | T167 | 12 | T216 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 305 | 1 | T16 | 5 | T134 | 8 | T31 | 2 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 233 | 1 | T3 | 13 | T222 | 3 | T170 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 22094 | 1 | T1 | 20 | T2 | 20 | T3 | 2 | ||||
auto[1] | auto[0] | 3435 | 1 | T3 | 18 | T4 | 11 | T5 | 23 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |