Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22590

1

T1

20

T2

20

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

2939

1

T3

20

T9

2

T11

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

20

T2

20

T3

20

auto[1]

5269

1

T5

26

T6

8

T9

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T309	3		T324	33		T325	7
values[0]	115	1			T170	23		T148	29		T246	14
values[1]	549	1			T4	12		T9	2		T100	2
values[2]	747	1			T3	6		T9	7		T133	1
values[3]	498	1			T131	3		T133	8		T134	6
values[4]	613	1			T3	14		T18	1		T31	7
values[5]	581	1			T9	17		T204	1		T135	1
values[6]	643	1			T6	8		T100	1		T133	8
values[7]	595	1			T31	34		T199	23		T34	2
values[8]	569	1			T11	16		T131	1		T134	9
values[9]	3213	1			T5	26		T9	16		T10	3
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	964	1			T4	12		T9	2		T100	2
values[1]	533	1			T3	6		T9	7		T133	1
values[2]	547	1			T131	3		T133	8		T18	1
values[3]	540	1			T3	14		T9	17		T139	12
values[4]	743	1			T100	1		T149	12		T204	1
values[5]	625	1			T6	8		T133	8		T31	34
values[6]	2434	1			T5	26		T10	3		T12	12
values[7]	677	1			T9	16		T11	16		T131	1
values[8]	828	1			T16	6		T152	1		T222	5
values[9]	252	1			T18	13		T132	28		T199	24
minimum	17386	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T4	12		T100	1		T18	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	2		T100	1		T31	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	1		T133	1		T203	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	6		T51	13		T56	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T131	1		T133	1		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T135	1		T210	12		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	9		T51	12		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	14		T139	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T100	1		T149	1		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T204	1		T214	10		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	5		T133	1		T31	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T199	10		T221	7		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T5	26		T10	3		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T154	1		T145	1		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	12		T131	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	14		T149	13		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T16	6		T152	1		T122	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T222	4		T32	10		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T18	13		T151	1		T202	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T132	14		T199	10		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17227	1			T1	20		T2	20		T6	168
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T58	15		T171	12		T172	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T31	7		T123	6		T170	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	6		T203	11		T136	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T51	7		T171	4		T262	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T131	2		T133	7		T136	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T210	4		T257	14		T274	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	8		T51	2		T172	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T139	11		T142	13		T91	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T149	11		T31	4		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T214	8		T251	2		T298	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	3		T133	7		T31	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T199	13		T142	8		T279	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T12	11		T59	10		T193	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T154	16		T145	17		T148	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T9	4		T243	11		T237	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T11	2		T149	12		T30	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T122	1		T237	12		T154	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T222	1		T32	10		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T202	9		T248	7		T286	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T132	14		T199	14		T155	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	1		T182	3		T143	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T324	15		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T309	3		T325	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T246	1		T326	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T170	7		T148	13		T327	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	12		T100	1		T18	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	2		T100	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	1		T133	1		T203	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	6		T51	13		T171	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T131	1		T133	1		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T56	11		T142	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	1		T31	3		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	14		T139	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	9		T135	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T204	1		T214	10		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	5		T100	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T221	7		T191	1		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T31	17		T34	2		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T199	10		T142	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T131	1		T135	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	14		T134	9		T30	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1443	1			T5	26		T9	12		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T132	14		T149	13		T140	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T324	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T246	13		T326	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T170	16		T148	16		T328	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T171	12		T172	9		T94	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T31	7		T123	6		T329	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	6		T203	11		T58	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T51	7		T171	14		T167	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T131	2		T133	7		T136	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T142	13		T259	8		T257	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T31	4		T136	11		T51	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T139	11		T210	4		T91	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	8		T169	12		T233	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T214	8		T251	2		T298	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	3		T133	7		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T266	16		T159	10		T297	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T31	17		T169	9		T227	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T199	13		T142	8		T154	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T33	1		T273	11		T248	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	2		T30	15		T216	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T9	4		T12	11		T59	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T132	14		T149	12		T199	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T4	1		T100	1		T18	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	1		T100	1		T31	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	7		T133	1		T203	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T51	8		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T131	3		T133	8		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T135	1		T210	5		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	9		T51	3		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	1		T139	12		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T100	1		T149	12		T31	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T204	1		T214	9		T251	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	5		T133	8		T31	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T199	14		T221	1		T142	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T5	3		T10	3		T12	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T154	17		T145	18		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T9	5		T131	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	3		T149	13		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T16	1		T152	1		T122	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T222	2		T32	12		T122	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T18	1		T151	1		T202	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T132	15		T199	15		T155	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17376	1			T1	20		T2	20		T6	168
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	11		T18	2		T58	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	1		T31	2		T219	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T136	15		T257	8		T297	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T3	5		T51	12		T56	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T134	5		T140	6		T136	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T210	11		T257	14		T274	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	8		T51	11		T172	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	13		T91	8		T241	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T31	2		T60	2		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T214	9		T146	7		T228	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	3		T31	16		T53	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T199	9		T221	6		T241	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T5	23		T13	10		T17	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T148	6		T279	8		T330	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	11		T243	12		T248	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	13		T149	12		T134	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	5		T122	1		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T222	3		T32	8		T91	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T18	12		T202	7		T248	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T132	13		T199	9		T331	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T332	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T324	19		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T309	1		T325	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T246	14		T326	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T170	18		T148	17		T327	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	1		T100	1		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T9	1		T100	1		T31	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T9	7		T133	1		T203	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	1		T51	8		T171	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T131	3		T133	8		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T56	1		T142	14		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T18	1		T31	5		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	1		T139	12		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	9		T135	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T204	1		T214	9		T251	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	5		T100	1		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T221	1		T191	1		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T31	18		T34	2		T169	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T199	14		T142	9		T154	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T131	1		T135	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	3		T134	1		T30	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T5	3		T9	5		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T132	15		T149	13		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T324	14		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T309	2		T325	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T326	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T170	5		T148	12		T327	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	11		T18	2		T171	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	1		T31	2		T219	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T58	13		T143	3		T91	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	5		T51	12		T171	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T134	5		T136	15		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T56	10		T257	14		T333	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T31	2		T140	6		T136	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	13		T210	11		T91	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	8		T157	2		T320	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T214	9		T146	7		T228	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	3		T53	12		T261	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T221	6		T241	7		T266	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T31	16		T266	2		T334	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T199	9		T148	6		T279	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T248	11		T226	1		T252	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T11	13		T134	8		T30	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T5	23		T9	11		T13	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T132	13		T149	12		T140	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23