Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22287

1

T1

20

T2

20

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

3242

1

T3

20

T9

24

T131

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20342

1

T1

20

T2

20

T3

6

auto[1]

5187

1

T3

14

T4

12

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T222	5		T335	1		-	-
values[0]	103	1			T18	13		T219	13		T53	13
values[1]	492	1			T31	7		T135	1		T152	1
values[2]	705	1			T139	12		T135	1		T151	1
values[3]	631	1			T135	1		T243	24		T140	7
values[4]	812	1			T3	20		T9	23		T100	1
values[5]	491	1			T6	8		T16	6		T100	1
values[6]	505	1			T131	1		T149	12		T199	23
values[7]	691	1			T136	22		T32	1		T154	10
values[8]	2526	1			T5	26		T10	3		T12	12
values[9]	1204	1			T4	12		T9	19		T11	16
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	744	1			T18	13		T31	7		T135	1
values[1]	610	1			T139	12		T135	2		T151	1
values[2]	669	1			T100	1		T243	24		T140	7
values[3]	785	1			T3	20		T9	7		T131	3
values[4]	489	1			T9	16		T16	6		T100	1
values[5]	530	1			T6	8		T149	12		T152	1
values[6]	2650	1			T5	26		T10	3		T12	12
values[7]	676	1			T133	16		T18	3		T31	34
values[8]	777	1			T4	12		T9	2		T100	1
values[9]	227	1			T9	17		T11	16		T149	25
minimum	17372	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T18	13		T219	13		T53	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T31	3		T135	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T139	1		T135	2		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T51	13		T122	4		T208	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T100	1		T140	7		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T243	13		T169	1		T170	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T131	1		T31	3		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	20		T9	1		T132	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T9	12		T16	6		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T131	1		T134	6		T171	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	5		T149	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T162	2		T147	1		T336	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T5	26		T10	3		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T32	1		T154	7		T298	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T133	2		T34	2		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T18	3		T31	17		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	12		T9	2		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T18	1		T204	1		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T11	14		T222	4		T172	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T9	9		T149	13		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T337	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T32	10		T169	12		T171	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T31	4		T142	21		T94	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T139	11		T136	11		T122	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T51	7		T122	1		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T167	12		T259	15		T281	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T243	11		T169	2		T170	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T131	2		T31	7		T248	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T9	6		T132	14		T30	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	4		T199	13		T202	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T171	12		T33	1		T232	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	3		T149	11		T172	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T308	7		T338	11		T175	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T12	11		T59	10		T193	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T154	3		T298	6		T91	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T133	14		T169	9		T94	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T31	17		T237	12		T251	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T199	14		T58	15		T248	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T123	6		T146	8		T174	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T11	2		T222	1		T172	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T9	8		T149	12		T192	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T337	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T222	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T335	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T18	13		T219	13		T53	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T230	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T32	9		T169	1		T298	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T31	3		T135	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T139	1		T135	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T56	6		T122	4		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T135	1		T140	7		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T243	13		T51	13		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	12		T100	1		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	20		T9	1		T132	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T6	5		T16	6		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T134	6		T51	12		T237	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T149	1		T199	10		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T131	1		T33	1		T162	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T136	16		T145	1		T172	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T32	1		T154	7		T298	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T5	26		T10	3		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T53	1		T237	1		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T4	12		T9	2		T11	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T9	9		T18	4		T149	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T222	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T121	13		T339	9		T188	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T32	10		T169	12		T228	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T31	4		T142	8		T94	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T139	11		T136	11		T122	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T122	1		T142	13		T210	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T259	15		T257	9		T281	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T243	11		T51	7		T169	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	4		T31	7		T203	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	6		T132	14		T30	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	3		T131	2		T202	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T51	2		T237	6		T142	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T149	11		T199	13		T242	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T33	1		T264	12		T246	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T136	6		T145	17		T172	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T154	3		T298	6		T65	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	898	1			T12	11		T59	10		T133	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T237	12		T251	2		T91	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	2		T199	14		T58	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	8		T149	12		T31	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T18	1		T219	1		T53	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	5		T135	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T139	12		T135	2		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T51	8		T122	4		T208	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T100	1		T140	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T243	12		T169	3		T170	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T131	3		T31	8		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	2		T9	7		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	5		T16	1		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T131	1		T134	1		T171	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	5		T149	12		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T162	2		T147	1		T336	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T5	3		T10	3		T12	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T32	1		T154	4		T298	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T133	16		T34	2		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T18	1		T31	18		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T9	1		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T18	1		T204	1		T123	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T11	3		T222	2		T172	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T9	9		T149	13		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T337	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T18	12		T219	12		T53	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T31	2		T56	5		T192	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T136	1		T58	3		T143	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T51	12		T122	1		T210	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T140	6		T167	12		T66	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T243	12		T170	5		T171	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T31	2		T248	4		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	18		T132	13		T134	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T9	11		T16	5		T199	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T134	5		T171	2		T146	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	3		T172	10		T242	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T312	6		T338	9		T175	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T5	23		T13	10		T17	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T154	6		T91	14		T65	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T94	10		T228	1		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T18	2		T31	16		T216	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	11		T9	1		T199	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T56	10		T146	7		T257	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T11	13		T222	3		T172	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T9	8		T149	12		T277	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T222	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T335	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T18	1		T219	1		T53	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T230	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T32	11		T169	13		T298	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T31	5		T135	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T139	12		T135	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T56	1		T122	4		T142	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T135	1		T140	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T243	12		T51	8		T169	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T9	5		T100	1		T31	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	2		T9	7		T132	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	5		T16	1		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	1		T51	3		T237	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T149	12		T199	14		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T131	1		T33	2		T162	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T136	7		T145	18		T172	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T32	1		T154	4		T298	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T5	3		T10	3		T12	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T53	1		T237	13		T251	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T4	1		T9	1		T11	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T9	9		T18	2		T149	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T222	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T18	12		T219	12		T53	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T230	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T32	8		T216	11		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T31	2		T192	8		T228	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	1		T58	3		T171	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T56	5		T122	1		T210	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T140	6		T257	8		T226	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T243	12		T51	12		T170	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	11		T31	2		T248	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	18		T132	13		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T6	3		T16	5		T202	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T134	5		T51	11		T171	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T199	9		T241	12		T242	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T264	11		T312	6		T338	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	15		T172	10		T286	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T154	6		T65	11		T157	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T5	23		T13	10		T17	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T91	14		T216	10		T244	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	11		T9	1		T11	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T9	8		T18	2		T149	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23