Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25529

1

T1

20

T2

20

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20093

1

T1

20

T2

20

T3

6

auto[ADC_CTRL_FILTER_COND_OUT]

5436

1

T3

14

T5

26

T9

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20335

1

T1

20

T2

20

T3

14

auto[1]

5194

1

T3

6

T4

12

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21653

1

T1

20

T2

20

T3

20

auto[1]

3876

1

T6

3

T9

19

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T233	8		T321	12		T340	1
values[0]	57	1			T135	1		T60	5		T259	9
values[1]	550	1			T4	12		T16	6		T100	1
values[2]	684	1			T139	13		T243	24		T53	13
values[3]	823	1			T3	6		T9	16		T100	1
values[4]	726	1			T18	3		T134	9		T31	7
values[5]	560	1			T100	1		T123	7		T51	20
values[6]	499	1			T3	14		T6	8		T9	7
values[7]	576	1			T9	19		T11	16		T133	8
values[8]	524	1			T133	1		T18	13		T149	12
values[9]	3145	1			T5	26		T10	3		T12	12
minimum	17363	1			T1	20		T2	20		T6	168

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	740	1			T4	12		T16	6		T135	1
values[1]	2755	1			T5	26		T10	3		T12	12
values[2]	823	1			T3	6		T9	16		T100	1
values[3]	607	1			T18	3		T134	9		T31	7
values[4]	491	1			T6	8		T100	1		T136	22
values[5]	588	1			T3	14		T9	7		T53	1
values[6]	530	1			T9	2		T11	16		T133	8
values[7]	686	1			T9	17		T133	1		T149	12
values[8]	699	1			T131	3		T31	34		T139	12
values[9]	242	1			T131	1		T169	3		T306	1
minimum	17368	1			T1	20		T2	20		T6	168

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

3435

1

T3

18

T4

11

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	12		T243	13		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T16	6		T135	1		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T169	1		T170	7		T172	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1382	1			T5	26		T10	3		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	6		T133	1		T132	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T9	12		T100	1		T149	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T18	3		T31	3		T140	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T134	9		T123	1		T51	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	5		T91	9		T295	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T100	1		T136	16		T192	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T53	1		T273	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	14		T32	9		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	2		T11	14		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T50	1		T122	5		T171	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T134	6		T152	2		T208	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	9		T133	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T131	1		T151	1		T221	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T31	17		T139	1		T140	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T169	1		T306	1		T72	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T131	1		T146	8		T191	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17219	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T243	11		T143	3		T251	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T136	11		T51	2		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T169	12		T170	16		T172	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1094	1			T12	11		T59	10		T193	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T133	7		T132	14		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	4		T149	12		T30	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T31	4		T203	11		T214	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T123	6		T51	7		T172	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	3		T91	2		T266	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T136	6		T192	4		T148	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	6		T273	11		T248	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T32	10		T142	8		T154	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	2		T133	7		T31	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T122	2		T171	4		T190	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T284	18		T280	15		T341	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	8		T149	11		T199	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T131	2		T222	1		T171	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T31	17		T139	11		T202	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T169	2		T148	16		T288	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T146	8		T265	10		T233	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	1		T182	3		T143	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T321	12		T340	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T233	4		T186	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T259	1		T287	3		T272	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T135	1		T60	5		T342	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T4	12		T35	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T16	6		T100	1		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T243	13		T32	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T139	1		T53	13		T58	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	6		T133	1		T132	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	12		T100	1		T149	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T18	3		T31	3		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T134	9		T199	10		T56	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T214	10		T248	12		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T100	1		T123	1		T51	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	5		T9	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	14		T136	16		T32	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	2		T11	14		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	9		T50	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T18	13		T134	6		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T133	1		T149	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T131	1		T151	1		T221	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1448	1			T5	26		T10	3		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T233	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T259	8		T272	3		T343	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T251	13		T154	3		T145	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T136	11		T51	2		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T243	11		T169	12		T170	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T139	12		T210	4		T94	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T133	7		T132	14		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T9	4		T149	12		T30	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T31	4		T203	11		T91	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T199	13		T228	1		T286	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T214	8		T248	16		T266	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T123	6		T51	7		T172	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	3		T9	6		T273	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T136	6		T32	10		T142	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	2		T133	7		T31	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	8		T154	16		T91	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T232	6		T280	15		T282	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T149	11		T58	15		T169	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T131	2		T222	1		T169	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1145	1			T12	11		T59	10		T193	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T182	3		T143	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	1		T243	12		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T16	1		T135	1		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T169	13		T170	18		T172	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1414	1			T5	3		T10	3		T12	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	1		T133	8		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T9	5		T100	1		T149	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T18	1		T31	5		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T134	1		T123	7		T51	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	5		T91	3		T295	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T100	1		T136	7		T192	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	7		T53	1		T273	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	1		T32	11		T142	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	1		T11	3		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T50	1		T122	6		T171	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T134	1		T152	2		T208	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	9		T133	1		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T131	3		T151	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T31	18		T139	12		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T169	3		T306	1		T72	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T131	1		T146	9		T191	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17366	1			T1	20		T2	20		T6	168
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T4	11		T243	12		T143	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T16	5		T136	1		T51	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T170	5		T172	10		T264	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1062	1			T5	23		T13	10		T17	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	5		T132	13		T146	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	11		T149	12		T30	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T18	2		T31	2		T140	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	8		T51	12		T56	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	3		T91	8		T266	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T136	15		T192	1		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T248	4		T216	10		T320	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	13		T32	8		T91	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T9	1		T11	13		T18	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T122	1		T171	11		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T134	5		T285	10		T284	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	8		T199	9		T58	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T221	6		T222	3		T171	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T31	16		T140	8		T202	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T148	12		T288	13		T266	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T146	7		T198	9		T344	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T226	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T321	1		T340	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T233	8		T186	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T259	9		T287	1		T272	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T135	1		T60	3		T342	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T4	1		T35	1		T251	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T16	1		T100	1		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T243	12		T32	1		T169	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T139	13		T53	1		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	1		T133	8		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T9	5		T100	1		T149	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T18	1		T31	5		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T134	1		T199	14		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T214	9		T248	17		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T100	1		T123	7		T51	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	5		T9	7		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T3	1		T136	7		T32	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T11	3		T133	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	9		T50	1		T154	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T18	1		T134	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T133	1		T149	12		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T131	3		T151	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1505	1			T5	3		T10	3		T12	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T1	20		T2	20		T6	168
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T321	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T287	2		T272	5		T343	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T60	2		T342	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T4	11		T154	6		T226	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T16	5		T136	1		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T243	12		T170	5		T143	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T53	12		T58	3		T210	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	5		T132	13		T146	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	11		T149	12		T30	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T18	2		T31	2		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	8		T199	9		T56	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T214	9		T248	11		T266	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T51	12		T172	10		T192	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	3		T248	4		T91	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T3	13		T136	15		T32	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	1		T11	13		T31	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T9	8		T91	14		T94	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T18	12		T134	5		T323	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T58	13		T122	1		T171	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T221	6		T222	3		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1088	1			T5	23		T13	10		T17	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22094

1

T1

20

T2

20

T3

2

auto[1]

auto[0]

3435

1

T3

18

T4

11

T5

23