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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 99.01 95.74 100.00 100.00 98.24 98.64 91.52


Total test records in report: 914
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T797 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.191066942 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:47 PM PST 24 431275467 ps
T26 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2623046530 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:31 PM PST 24 1853286335 ps
T36 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3547299430 Feb 21 12:28:22 PM PST 24 Feb 21 12:28:25 PM PST 24 364584915 ps
T40 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3577723531 Feb 21 12:28:48 PM PST 24 Feb 21 12:28:50 PM PST 24 460793585 ps
T101 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2474919579 Feb 21 12:28:22 PM PST 24 Feb 21 12:28:25 PM PST 24 1237702029 ps
T29 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.476786772 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:31 PM PST 24 533858198 ps
T798 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3958849114 Feb 21 12:28:41 PM PST 24 Feb 21 12:28:44 PM PST 24 284292357 ps
T37 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3709937135 Feb 21 12:28:26 PM PST 24 Feb 21 12:28:33 PM PST 24 4242146121 ps
T120 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3194313823 Feb 21 12:28:24 PM PST 24 Feb 21 12:28:29 PM PST 24 911244387 ps
T799 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.991900817 Feb 21 12:28:38 PM PST 24 Feb 21 12:28:40 PM PST 24 486453706 ps
T800 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3820805511 Feb 21 12:28:31 PM PST 24 Feb 21 12:28:33 PM PST 24 527804903 ps
T801 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1371238500 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:57 PM PST 24 452488348 ps
T38 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3077488406 Feb 21 12:28:22 PM PST 24 Feb 21 12:28:34 PM PST 24 3981048140 ps
T41 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2342221391 Feb 21 12:28:27 PM PST 24 Feb 21 12:28:48 PM PST 24 7846301032 ps
T115 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.255801913 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:43 PM PST 24 335680742 ps
T27 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.515926972 Feb 21 12:28:47 PM PST 24 Feb 21 12:29:02 PM PST 24 3734283634 ps
T42 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1748161679 Feb 21 12:28:29 PM PST 24 Feb 21 12:28:32 PM PST 24 925653536 ps
T802 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3748114036 Feb 21 12:28:42 PM PST 24 Feb 21 12:28:45 PM PST 24 315020550 ps
T75 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.345462304 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:33 PM PST 24 4211395419 ps
T77 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2034465396 Feb 21 12:28:42 PM PST 24 Feb 21 12:28:45 PM PST 24 588177857 ps
T803 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2891979926 Feb 21 12:28:38 PM PST 24 Feb 21 12:28:41 PM PST 24 450828526 ps
T78 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.793530147 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:31 PM PST 24 499959556 ps
T28 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1485527761 Feb 21 12:28:27 PM PST 24 Feb 21 12:28:40 PM PST 24 4715606419 ps
T804 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.503242990 Feb 21 12:28:30 PM PST 24 Feb 21 12:28:32 PM PST 24 412176251 ps
T805 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3729271022 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:46 PM PST 24 414661623 ps
T102 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3355573363 Feb 21 12:28:30 PM PST 24 Feb 21 12:28:32 PM PST 24 426001332 ps
T79 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3352120564 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:43 PM PST 24 666831983 ps
T80 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.534084783 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:50 PM PST 24 900167631 ps
T806 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3007778305 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:43 PM PST 24 357191817 ps
T807 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1856269940 Feb 21 12:28:35 PM PST 24 Feb 21 12:28:37 PM PST 24 563888661 ps
T808 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.46808717 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:50 PM PST 24 358082856 ps
T809 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1606895386 Feb 21 12:28:18 PM PST 24 Feb 21 12:28:20 PM PST 24 485525432 ps
T810 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.519326592 Feb 21 12:28:42 PM PST 24 Feb 21 12:28:44 PM PST 24 296794128 ps
T116 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1013849197 Feb 21 12:28:37 PM PST 24 Feb 21 12:28:39 PM PST 24 325178770 ps
T103 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2181601886 Feb 21 12:28:32 PM PST 24 Feb 21 12:28:35 PM PST 24 699381340 ps
T104 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.673841645 Feb 21 12:29:29 PM PST 24 Feb 21 12:29:31 PM PST 24 445625631 ps
T117 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2557793188 Feb 21 12:28:37 PM PST 24 Feb 21 12:28:42 PM PST 24 2092275408 ps
T118 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2010925540 Feb 21 12:28:22 PM PST 24 Feb 21 12:28:27 PM PST 24 2575571392 ps
T127 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2992791194 Feb 21 12:28:27 PM PST 24 Feb 21 12:28:32 PM PST 24 4608206391 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.134114287 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:31 PM PST 24 508782805 ps
T811 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2932002042 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:49 PM PST 24 520127510 ps
T812 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.188718943 Feb 21 12:28:26 PM PST 24 Feb 21 12:28:29 PM PST 24 416272222 ps
T813 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3850237008 Feb 21 12:28:26 PM PST 24 Feb 21 12:28:29 PM PST 24 533752417 ps
T814 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2266239295 Feb 21 12:28:31 PM PST 24 Feb 21 12:28:34 PM PST 24 4532534302 ps
T815 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2097347886 Feb 21 12:28:41 PM PST 24 Feb 21 12:28:44 PM PST 24 299015135 ps
T105 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.226916483 Feb 21 12:28:35 PM PST 24 Feb 21 12:28:38 PM PST 24 523880971 ps
T816 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3644210033 Feb 21 12:28:36 PM PST 24 Feb 21 12:28:39 PM PST 24 443380571 ps
T126 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.868132705 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:43 PM PST 24 660734323 ps
T817 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2431264054 Feb 21 12:28:21 PM PST 24 Feb 21 12:28:24 PM PST 24 2425387291 ps
T818 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2370694495 Feb 21 12:28:35 PM PST 24 Feb 21 12:28:36 PM PST 24 387350620 ps
T106 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.838566490 Feb 21 12:28:16 PM PST 24 Feb 21 12:29:25 PM PST 24 18742765311 ps
T819 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2436464391 Feb 21 12:28:33 PM PST 24 Feb 21 12:28:36 PM PST 24 290630025 ps
T124 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2546630445 Feb 21 12:28:24 PM PST 24 Feb 21 12:28:28 PM PST 24 369112654 ps
T820 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2117807949 Feb 21 12:28:41 PM PST 24 Feb 21 12:28:44 PM PST 24 430395909 ps
T128 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3297655321 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:26 PM PST 24 8542938910 ps
T821 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1218201516 Feb 21 12:28:42 PM PST 24 Feb 21 12:28:44 PM PST 24 314324746 ps
T822 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3280843065 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:45 PM PST 24 384128076 ps
T823 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1825239955 Feb 21 12:28:16 PM PST 24 Feb 21 12:28:21 PM PST 24 4393269875 ps
T824 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2969793378 Feb 21 12:28:38 PM PST 24 Feb 21 12:28:40 PM PST 24 614309169 ps
T825 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2089429180 Feb 21 12:28:24 PM PST 24 Feb 21 12:28:28 PM PST 24 1133015309 ps
T826 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4215652855 Feb 21 12:28:24 PM PST 24 Feb 21 12:28:26 PM PST 24 489109168 ps
T827 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3397086372 Feb 21 12:28:18 PM PST 24 Feb 21 12:28:21 PM PST 24 424299003 ps
T107 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2038473939 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:31 PM PST 24 452362407 ps
T828 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1462226932 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:45 PM PST 24 4410575825 ps
T829 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.571608954 Feb 21 12:28:11 PM PST 24 Feb 21 12:28:25 PM PST 24 8631487092 ps
T830 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1546897411 Feb 21 12:28:30 PM PST 24 Feb 21 12:28:32 PM PST 24 297204932 ps
T831 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1628436092 Feb 21 12:28:26 PM PST 24 Feb 21 12:28:28 PM PST 24 558047007 ps
T125 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2207565069 Feb 21 12:28:29 PM PST 24 Feb 21 12:28:32 PM PST 24 480642108 ps
T366 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4188966142 Feb 21 12:28:41 PM PST 24 Feb 21 12:28:55 PM PST 24 4367724421 ps
T832 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4294027472 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:47 PM PST 24 527150416 ps
T108 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.238670973 Feb 21 12:28:35 PM PST 24 Feb 21 12:28:37 PM PST 24 539620586 ps
T833 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1392951812 Feb 21 12:28:39 PM PST 24 Feb 21 12:28:42 PM PST 24 441165589 ps
T109 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.955302128 Feb 21 12:28:39 PM PST 24 Feb 21 12:28:44 PM PST 24 775871131 ps
T130 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2105609953 Feb 21 12:28:27 PM PST 24 Feb 21 12:28:30 PM PST 24 593499792 ps
T834 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.862781423 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:43 PM PST 24 503379140 ps
T835 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3228537614 Feb 21 12:28:20 PM PST 24 Feb 21 12:28:32 PM PST 24 4287140858 ps
T836 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1122460876 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:50 PM PST 24 535257396 ps
T110 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3120565113 Feb 21 12:28:39 PM PST 24 Feb 21 12:28:43 PM PST 24 823209557 ps
T837 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1193873382 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:49 PM PST 24 514639105 ps
T838 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1556490853 Feb 21 12:28:38 PM PST 24 Feb 21 12:28:40 PM PST 24 386760271 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.65186997 Feb 21 12:28:20 PM PST 24 Feb 21 12:29:00 PM PST 24 31369134432 ps
T129 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4210523230 Feb 21 12:29:46 PM PST 24 Feb 21 12:29:49 PM PST 24 900701216 ps
T839 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4001126477 Feb 21 12:28:41 PM PST 24 Feb 21 12:28:44 PM PST 24 372971063 ps
T840 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3015004302 Feb 21 12:28:49 PM PST 24 Feb 21 12:28:50 PM PST 24 459064785 ps
T841 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4244320621 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:46 PM PST 24 504563429 ps
T842 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1878502846 Feb 21 12:28:32 PM PST 24 Feb 21 12:28:36 PM PST 24 485779622 ps
T843 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.181014041 Feb 21 12:28:32 PM PST 24 Feb 21 12:28:34 PM PST 24 404984861 ps
T844 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1801795019 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:49 PM PST 24 506378034 ps
T845 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.990832157 Feb 21 12:29:29 PM PST 24 Feb 21 12:29:31 PM PST 24 829297797 ps
T846 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.303957094 Feb 21 12:28:22 PM PST 24 Feb 21 12:28:24 PM PST 24 314806679 ps
T114 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3434725460 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:43 PM PST 24 413697047 ps
T847 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1238950301 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:44 PM PST 24 2738568213 ps
T848 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2928856878 Feb 21 12:28:33 PM PST 24 Feb 21 12:28:36 PM PST 24 447045460 ps
T849 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1482001704 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:58 PM PST 24 4127019907 ps
T850 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2213332069 Feb 21 12:28:27 PM PST 24 Feb 21 12:28:30 PM PST 24 401354668 ps
T851 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4093332436 Feb 21 12:28:24 PM PST 24 Feb 21 12:28:26 PM PST 24 422935447 ps
T852 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2643913343 Feb 21 12:28:43 PM PST 24 Feb 21 12:28:54 PM PST 24 7681012227 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3028396229 Feb 21 12:28:39 PM PST 24 Feb 21 12:30:23 PM PST 24 23760288811 ps
T853 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2416493975 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:49 PM PST 24 316606242 ps
T854 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2494166743 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:47 PM PST 24 365456492 ps
T855 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3491981798 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:50 PM PST 24 8018315743 ps
T856 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3975825017 Feb 21 12:28:36 PM PST 24 Feb 21 12:28:37 PM PST 24 535903298 ps
T857 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1572430335 Feb 21 12:28:33 PM PST 24 Feb 21 12:28:36 PM PST 24 1775958416 ps
T858 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1456691011 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:51 PM PST 24 576298685 ps
T859 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1627029541 Feb 21 12:28:30 PM PST 24 Feb 21 12:28:34 PM PST 24 4171992604 ps
T860 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3067012256 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:30 PM PST 24 470717653 ps
T861 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.487393670 Feb 21 12:28:23 PM PST 24 Feb 21 12:28:26 PM PST 24 1955612693 ps
T862 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4284993654 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:40 PM PST 24 8339260918 ps
T863 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2347788587 Feb 21 12:28:31 PM PST 24 Feb 21 12:28:36 PM PST 24 2656216746 ps
T864 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.126975908 Feb 21 12:28:22 PM PST 24 Feb 21 12:28:26 PM PST 24 429585867 ps
T865 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2081919046 Feb 21 12:28:42 PM PST 24 Feb 21 12:28:55 PM PST 24 4816631309 ps
T866 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3673600809 Feb 21 12:28:48 PM PST 24 Feb 21 12:28:50 PM PST 24 421373558 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3260345668 Feb 21 12:28:21 PM PST 24 Feb 21 12:28:27 PM PST 24 1483374454 ps
T867 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1498994258 Feb 21 12:28:38 PM PST 24 Feb 21 12:28:41 PM PST 24 4787587369 ps
T868 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2969942852 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:31 PM PST 24 1382119328 ps
T869 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.500829429 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:50 PM PST 24 402641781 ps
T870 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3842503690 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:45 PM PST 24 2304758739 ps
T871 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2210906080 Feb 21 12:28:48 PM PST 24 Feb 21 12:28:50 PM PST 24 435336416 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1495732917 Feb 21 12:28:15 PM PST 24 Feb 21 12:28:19 PM PST 24 405384613 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3274344138 Feb 21 12:29:46 PM PST 24 Feb 21 12:29:48 PM PST 24 507957558 ps
T874 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2085772719 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:03 PM PST 24 310569815 ps
T875 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1444169875 Feb 21 12:28:35 PM PST 24 Feb 21 12:28:38 PM PST 24 766951924 ps
T876 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3916621113 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:42 PM PST 24 442567789 ps
T877 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.548698232 Feb 21 12:28:36 PM PST 24 Feb 21 12:28:37 PM PST 24 487341556 ps
T878 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3572608159 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:31 PM PST 24 460949412 ps
T879 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.444693363 Feb 21 12:28:40 PM PST 24 Feb 21 12:29:03 PM PST 24 8728423166 ps
T880 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2735364479 Feb 21 12:28:25 PM PST 24 Feb 21 12:28:30 PM PST 24 386469735 ps
T881 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1744924572 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:43 PM PST 24 5269982515 ps
T882 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.525351101 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:04 PM PST 24 402083797 ps
T883 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3643215893 Feb 21 12:28:36 PM PST 24 Feb 21 12:28:38 PM PST 24 382667427 ps
T884 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1577304040 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:45 PM PST 24 548099999 ps
T885 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.516907777 Feb 21 12:28:29 PM PST 24 Feb 21 12:28:31 PM PST 24 569337980 ps
T886 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3726819315 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:45 PM PST 24 432356078 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1674799406 Feb 21 12:28:22 PM PST 24 Feb 21 12:28:42 PM PST 24 4745676034 ps
T888 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2774961668 Feb 21 12:28:31 PM PST 24 Feb 21 12:28:33 PM PST 24 370119271 ps
T889 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3590704133 Feb 21 12:28:41 PM PST 24 Feb 21 12:28:44 PM PST 24 400685663 ps
T890 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2096835909 Feb 21 12:28:42 PM PST 24 Feb 21 12:28:45 PM PST 24 527591519 ps
T891 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2472987451 Feb 21 12:28:39 PM PST 24 Feb 21 12:28:41 PM PST 24 391710809 ps
T892 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3965955194 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:53 PM PST 24 8318763503 ps
T893 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2437491318 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:49 PM PST 24 533537555 ps
T894 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3107415388 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:46 PM PST 24 481240316 ps
T895 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.823752386 Feb 21 12:28:44 PM PST 24 Feb 21 12:28:45 PM PST 24 386786351 ps
T896 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4276263263 Feb 21 12:28:33 PM PST 24 Feb 21 12:28:36 PM PST 24 443328937 ps
T367 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1886644864 Feb 21 12:28:27 PM PST 24 Feb 21 12:28:47 PM PST 24 7805000816 ps
T897 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.71286756 Feb 21 12:28:28 PM PST 24 Feb 21 12:28:30 PM PST 24 369152475 ps
T898 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2920874124 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:55 PM PST 24 354436789 ps
T899 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3180119974 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:54 PM PST 24 3800318750 ps
T900 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.821535497 Feb 21 12:28:41 PM PST 24 Feb 21 12:28:47 PM PST 24 2960296893 ps
T364 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2294257028 Feb 21 12:28:41 PM PST 24 Feb 21 12:28:47 PM PST 24 4247457933 ps
T901 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.81567801 Feb 21 12:28:33 PM PST 24 Feb 21 12:28:36 PM PST 24 422841783 ps
T365 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2416891571 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:07 PM PST 24 4824716474 ps
T902 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.106595 Feb 21 12:28:24 PM PST 24 Feb 21 12:28:31 PM PST 24 3852566741 ps
T903 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.353242953 Feb 21 12:28:35 PM PST 24 Feb 21 12:28:37 PM PST 24 457988070 ps
T904 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2213579778 Feb 21 12:28:31 PM PST 24 Feb 21 12:28:33 PM PST 24 383802075 ps
T905 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3996169112 Feb 21 12:28:33 PM PST 24 Feb 21 12:28:40 PM PST 24 4192861715 ps
T906 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3454326229 Feb 21 12:28:36 PM PST 24 Feb 21 12:28:39 PM PST 24 509717305 ps
T907 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1966184137 Feb 21 12:29:46 PM PST 24 Feb 21 12:29:50 PM PST 24 910972444 ps
T908 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2604531487 Feb 21 12:28:33 PM PST 24 Feb 21 12:28:37 PM PST 24 769930746 ps
T909 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3747621251 Feb 21 12:28:40 PM PST 24 Feb 21 12:28:43 PM PST 24 422775513 ps
T910 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.641955260 Feb 21 12:28:36 PM PST 24 Feb 21 12:28:38 PM PST 24 375155291 ps
T911 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4336562 Feb 21 12:28:30 PM PST 24 Feb 21 12:29:34 PM PST 24 26962669971 ps
T912 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.632110774 Feb 21 12:28:49 PM PST 24 Feb 21 12:28:51 PM PST 24 356263804 ps
T913 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.396483048 Feb 21 12:28:35 PM PST 24 Feb 21 12:28:36 PM PST 24 377113900 ps
T914 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4246469808 Feb 21 12:28:26 PM PST 24 Feb 21 12:28:28 PM PST 24 372482411 ps

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3880583758
Short name T6
Test name
Test status
Simulation time 176647050748 ps
CPU time 282.62 seconds
Started Feb 21 12:47:01 PM PST 24
Finished Feb 21 12:51:45 PM PST 24
Peak memory 210044 kb
Host smart-ec8a1c68-b928-46cc-98a0-efbb6ca31f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880583758 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3880583758
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4221605275
Short name T9
Test name
Test status
Simulation time 664566423090 ps
CPU time 173.72 seconds
Started Feb 21 12:48:17 PM PST 24
Finished Feb 21 12:51:11 PM PST 24
Peak memory 201440 kb
Host smart-461426de-0b0c-43e0-9fc0-83af2664afd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221605275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4221605275
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1296918456
Short name T170
Test name
Test status
Simulation time 298617430262 ps
CPU time 257.22 seconds
Started Feb 21 12:47:39 PM PST 24
Finished Feb 21 12:51:57 PM PST 24
Peak memory 210152 kb
Host smart-1331de83-4f3b-4163-9e37-a749e100e4f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296918456 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1296918456
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1183051800
Short name T31
Test name
Test status
Simulation time 506256661908 ps
CPU time 254.44 seconds
Started Feb 21 12:50:01 PM PST 24
Finished Feb 21 12:54:15 PM PST 24
Peak memory 201420 kb
Host smart-c1515ab8-2458-49c9-af40-1a5fc2dedbfb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183051800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1183051800
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3947021699
Short name T134
Test name
Test status
Simulation time 331516474847 ps
CPU time 322.95 seconds
Started Feb 21 12:47:45 PM PST 24
Finished Feb 21 12:53:09 PM PST 24
Peak memory 201484 kb
Host smart-13b7a40e-6ef2-4bb4-8c08-ff4e041f2472
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947021699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3947021699
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3004348420
Short name T171
Test name
Test status
Simulation time 497749360660 ps
CPU time 292.56 seconds
Started Feb 21 12:48:50 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 201568 kb
Host smart-1fc7683e-0679-466c-97ee-f9a520c8aec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004348420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3004348420
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.20699148
Short name T91
Test name
Test status
Simulation time 490883862735 ps
CPU time 282.2 seconds
Started Feb 21 12:47:30 PM PST 24
Finished Feb 21 12:52:13 PM PST 24
Peak memory 201508 kb
Host smart-24122bcb-5b23-4238-8e2d-256b7d69e60b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20699148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gatin
g.20699148
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.100808892
Short name T232
Test name
Test status
Simulation time 91872572795 ps
CPU time 195.4 seconds
Started Feb 21 12:48:37 PM PST 24
Finished Feb 21 12:51:53 PM PST 24
Peak memory 210112 kb
Host smart-9e37a349-0b4d-4cef-8d45-a80a1e930681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100808892 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.100808892
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4250375774
Short name T172
Test name
Test status
Simulation time 500968464026 ps
CPU time 299.17 seconds
Started Feb 21 12:46:59 PM PST 24
Finished Feb 21 12:51:59 PM PST 24
Peak memory 201492 kb
Host smart-c1aaba9e-4674-4d9e-8f93-60195e6af148
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250375774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4250375774
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1171423064
Short name T142
Test name
Test status
Simulation time 492447078101 ps
CPU time 304.96 seconds
Started Feb 21 12:47:51 PM PST 24
Finished Feb 21 12:52:57 PM PST 24
Peak memory 201456 kb
Host smart-e930a4ce-7d15-4130-b3d0-3c5f0b1c2559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171423064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1171423064
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2342221391
Short name T41
Test name
Test status
Simulation time 7846301032 ps
CPU time 20.21 seconds
Started Feb 21 12:28:27 PM PST 24
Finished Feb 21 12:28:48 PM PST 24
Peak memory 201112 kb
Host smart-2333efde-ca3b-4e97-9f31-20c90206e811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342221391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2342221391
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.536131821
Short name T146
Test name
Test status
Simulation time 321109324159 ps
CPU time 150.31 seconds
Started Feb 21 12:48:11 PM PST 24
Finished Feb 21 12:50:42 PM PST 24
Peak memory 201528 kb
Host smart-59f76c4d-9976-467b-83ad-404d185313ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536131821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.536131821
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1526843458
Short name T154
Test name
Test status
Simulation time 807848310915 ps
CPU time 959.51 seconds
Started Feb 21 12:47:27 PM PST 24
Finished Feb 21 01:03:27 PM PST 24
Peak memory 209908 kb
Host smart-3af31265-83a6-43c3-ac7b-87e4a20e1bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526843458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1526843458
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1787964907
Short name T199
Test name
Test status
Simulation time 323271773410 ps
CPU time 66.61 seconds
Started Feb 21 12:46:59 PM PST 24
Finished Feb 21 12:48:06 PM PST 24
Peak memory 201568 kb
Host smart-eb4e59a3-8f9d-4ab8-ad9f-478f85ddfab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787964907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1787964907
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3451912860
Short name T13
Test name
Test status
Simulation time 160158764328 ps
CPU time 344.01 seconds
Started Feb 21 12:49:43 PM PST 24
Finished Feb 21 12:55:27 PM PST 24
Peak memory 201500 kb
Host smart-d98dfc11-635e-4ce3-98ed-81eb4ea802c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451912860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3451912860
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2276922661
Short name T46
Test name
Test status
Simulation time 4416148806 ps
CPU time 9.35 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:47:28 PM PST 24
Peak memory 216472 kb
Host smart-869f2c07-85e9-451f-a658-d2802fc7e640
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276922661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2276922661
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1481324539
Short name T148
Test name
Test status
Simulation time 329796949020 ps
CPU time 376.54 seconds
Started Feb 21 12:48:26 PM PST 24
Finished Feb 21 12:54:43 PM PST 24
Peak memory 201408 kb
Host smart-b337ee3b-a36f-4261-8ce3-7e2aba6c6240
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481324539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1481324539
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.399133285
Short name T60
Test name
Test status
Simulation time 139331693935 ps
CPU time 262.81 seconds
Started Feb 21 12:47:57 PM PST 24
Finished Feb 21 12:52:20 PM PST 24
Peak memory 210112 kb
Host smart-c015ac69-a176-4296-962a-8949b3220f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399133285 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.399133285
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.476786772
Short name T29
Test name
Test status
Simulation time 533858198 ps
CPU time 2.08 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:31 PM PST 24
Peak memory 199500 kb
Host smart-700005f6-9e4d-45c0-b665-a3e2e61e3eb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476786772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.476786772
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2398574994
Short name T244
Test name
Test status
Simulation time 500684184460 ps
CPU time 80.49 seconds
Started Feb 21 12:47:26 PM PST 24
Finished Feb 21 12:48:47 PM PST 24
Peak memory 201396 kb
Host smart-80651dc9-b24f-4b74-b514-3fffaea67ac8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398574994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2398574994
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.301224245
Short name T226
Test name
Test status
Simulation time 38756187543 ps
CPU time 85.02 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:48:44 PM PST 24
Peak memory 209820 kb
Host smart-99b3596b-101b-4864-af22-020cdc9b91ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301224245 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.301224245
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.257418916
Short name T297
Test name
Test status
Simulation time 495250589461 ps
CPU time 569 seconds
Started Feb 21 12:48:36 PM PST 24
Finished Feb 21 12:58:05 PM PST 24
Peak memory 201412 kb
Host smart-dec298c8-8b90-4c55-a5d8-6cdb9e6f9dc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257418916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.257418916
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2207565069
Short name T125
Test name
Test status
Simulation time 480642108 ps
CPU time 2.63 seconds
Started Feb 21 12:28:29 PM PST 24
Finished Feb 21 12:28:32 PM PST 24
Peak memory 217372 kb
Host smart-ea15a6a4-7a0e-4077-a34c-417acdfac30d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207565069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2207565069
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2573825768
Short name T139
Test name
Test status
Simulation time 328164842548 ps
CPU time 52.93 seconds
Started Feb 21 12:47:53 PM PST 24
Finished Feb 21 12:48:46 PM PST 24
Peak memory 201504 kb
Host smart-4082b60f-5f56-436d-9c7e-18df957bf638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573825768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2573825768
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4071887699
Short name T248
Test name
Test status
Simulation time 341447941197 ps
CPU time 281.48 seconds
Started Feb 21 12:49:02 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 201492 kb
Host smart-0cf0f828-549a-4906-9309-febfb889c98e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071887699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4071887699
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1264845487
Short name T277
Test name
Test status
Simulation time 319666286676 ps
CPU time 364.11 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:53:50 PM PST 24
Peak memory 201576 kb
Host smart-bb46abb6-5752-4957-8c21-d99fb13347a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264845487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1264845487
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.827698561
Short name T94
Test name
Test status
Simulation time 516104648023 ps
CPU time 318.09 seconds
Started Feb 21 12:47:50 PM PST 24
Finished Feb 21 12:53:09 PM PST 24
Peak memory 201572 kb
Host smart-a4471824-9d25-4b09-9c0b-79c12167d741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827698561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.827698561
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2015510587
Short name T257
Test name
Test status
Simulation time 330768582996 ps
CPU time 684.31 seconds
Started Feb 21 12:47:31 PM PST 24
Finished Feb 21 12:58:56 PM PST 24
Peak memory 201584 kb
Host smart-5e4ea19a-a7ca-4ebc-bbc8-53ba16a270e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015510587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2015510587
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.898918460
Short name T272
Test name
Test status
Simulation time 500855520005 ps
CPU time 1044.05 seconds
Started Feb 21 12:47:22 PM PST 24
Finished Feb 21 01:04:47 PM PST 24
Peak memory 201584 kb
Host smart-caa2bb97-7292-4a1d-86b1-45f99c44d016
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898918460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.898918460
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.69634546
Short name T255
Test name
Test status
Simulation time 161522827647 ps
CPU time 359.62 seconds
Started Feb 21 12:47:11 PM PST 24
Finished Feb 21 12:53:11 PM PST 24
Peak memory 201504 kb
Host smart-a21060af-3447-4d7d-be84-3b306fd48044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69634546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.69634546
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3825560362
Short name T123
Test name
Test status
Simulation time 405087808867 ps
CPU time 923.55 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 01:03:12 PM PST 24
Peak memory 210024 kb
Host smart-b9072fa1-6071-4a81-b920-9f3f7b207cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825560362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3825560362
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.551213815
Short name T140
Test name
Test status
Simulation time 336376199304 ps
CPU time 205.63 seconds
Started Feb 21 12:47:40 PM PST 24
Finished Feb 21 12:51:07 PM PST 24
Peak memory 201556 kb
Host smart-5415f7e7-4437-4244-8e16-48d8bfd58c12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551213815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.551213815
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.14072035
Short name T44
Test name
Test status
Simulation time 432085710 ps
CPU time 1.62 seconds
Started Feb 21 12:47:29 PM PST 24
Finished Feb 21 12:47:32 PM PST 24
Peak memory 201124 kb
Host smart-19c27724-4149-4aba-8d77-de923d6a7ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14072035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.14072035
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2394331267
Short name T229
Test name
Test status
Simulation time 49678385910 ps
CPU time 99.07 seconds
Started Feb 21 12:47:28 PM PST 24
Finished Feb 21 12:49:07 PM PST 24
Peak memory 209796 kb
Host smart-0617bdff-2122-4e79-9439-29a6446c17ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394331267 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2394331267
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2685714097
Short name T131
Test name
Test status
Simulation time 323785042468 ps
CPU time 709.5 seconds
Started Feb 21 12:47:01 PM PST 24
Finished Feb 21 12:58:51 PM PST 24
Peak memory 201496 kb
Host smart-e565e3f1-7842-45fa-b1d5-358124c62286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685714097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2685714097
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1975444508
Short name T32
Test name
Test status
Simulation time 323724899376 ps
CPU time 321.63 seconds
Started Feb 21 12:49:29 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 201548 kb
Host smart-22d09bcc-0d62-4a6d-9dd0-a370c0aad58d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975444508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1975444508
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3275369735
Short name T230
Test name
Test status
Simulation time 352181465604 ps
CPU time 94.41 seconds
Started Feb 21 12:49:57 PM PST 24
Finished Feb 21 12:51:32 PM PST 24
Peak memory 210136 kb
Host smart-72f51106-bb86-49d1-8bfa-8d690065f0a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275369735 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3275369735
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2866445623
Short name T284
Test name
Test status
Simulation time 490676036571 ps
CPU time 974.36 seconds
Started Feb 21 12:48:59 PM PST 24
Finished Feb 21 01:05:13 PM PST 24
Peak memory 201484 kb
Host smart-db82483f-10d4-4047-a7fe-b4b3330d2e08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866445623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2866445623
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3925651301
Short name T59
Test name
Test status
Simulation time 166581788812 ps
CPU time 333.79 seconds
Started Feb 21 12:47:43 PM PST 24
Finished Feb 21 12:53:17 PM PST 24
Peak memory 201492 kb
Host smart-81f0fbb4-d189-41c5-a50f-58d6af1e5d0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925651301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3925651301
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.232348631
Short name T121
Test name
Test status
Simulation time 499738176811 ps
CPU time 206.47 seconds
Started Feb 21 12:48:43 PM PST 24
Finished Feb 21 12:52:10 PM PST 24
Peak memory 201472 kb
Host smart-6988656e-76d3-43bf-927d-ab0d4bdd7e91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232348631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.232348631
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.838566490
Short name T106
Test name
Test status
Simulation time 18742765311 ps
CPU time 66.13 seconds
Started Feb 21 12:28:16 PM PST 24
Finished Feb 21 12:29:25 PM PST 24
Peak memory 199924 kb
Host smart-2ff36cae-86c0-427a-b23b-acbc2f1ce539
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838566490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.838566490
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.793530147
Short name T78
Test name
Test status
Simulation time 499959556 ps
CPU time 2.16 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:31 PM PST 24
Peak memory 201068 kb
Host smart-58dc667a-8e04-49fc-9847-38125fb552b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793530147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.793530147
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.993415193
Short name T135
Test name
Test status
Simulation time 491390373513 ps
CPU time 1076.32 seconds
Started Feb 21 12:47:36 PM PST 24
Finished Feb 21 01:05:33 PM PST 24
Peak memory 201464 kb
Host smart-f02b4357-ece4-4dbe-8b13-6a7f4505be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993415193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.993415193
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2323026898
Short name T326
Test name
Test status
Simulation time 498603356588 ps
CPU time 1183.54 seconds
Started Feb 21 12:49:25 PM PST 24
Finished Feb 21 01:09:09 PM PST 24
Peak memory 201584 kb
Host smart-0946995d-2de8-40ea-8425-801d5768ebcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323026898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2323026898
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3467284347
Short name T308
Test name
Test status
Simulation time 469591625888 ps
CPU time 602.54 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:57:36 PM PST 24
Peak memory 201892 kb
Host smart-4fd47fda-1f73-47fe-baaa-ce820aa99687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467284347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3467284347
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2112787615
Short name T259
Test name
Test status
Simulation time 327052237079 ps
CPU time 742.95 seconds
Started Feb 21 12:47:23 PM PST 24
Finished Feb 21 12:59:47 PM PST 24
Peak memory 201584 kb
Host smart-6f446d7d-e66e-4de7-8d56-020248a884ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112787615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2112787615
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.4293014040
Short name T309
Test name
Test status
Simulation time 340931391564 ps
CPU time 717.7 seconds
Started Feb 21 12:49:31 PM PST 24
Finished Feb 21 01:01:29 PM PST 24
Peak memory 201480 kb
Host smart-ec6b9c2c-30aa-4aec-af0a-15be0b9ca62d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293014040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.4293014040
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2847739636
Short name T314
Test name
Test status
Simulation time 333947250554 ps
CPU time 230.8 seconds
Started Feb 21 12:50:45 PM PST 24
Finished Feb 21 12:54:37 PM PST 24
Peak memory 201516 kb
Host smart-52e5ef6a-b0c0-431e-9e1e-965fdbfcd774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847739636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2847739636
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1450140067
Short name T222
Test name
Test status
Simulation time 166763887740 ps
CPU time 348.36 seconds
Started Feb 21 12:46:59 PM PST 24
Finished Feb 21 12:52:48 PM PST 24
Peak memory 201540 kb
Host smart-9da4f3ce-c96e-45b5-8bcc-d59db5cdfe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450140067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1450140067
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.259184176
Short name T254
Test name
Test status
Simulation time 501654406096 ps
CPU time 855.55 seconds
Started Feb 21 12:48:55 PM PST 24
Finished Feb 21 01:03:11 PM PST 24
Peak memory 201468 kb
Host smart-db510b2a-5de0-431a-bd22-3929559a239c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259184176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.259184176
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2829218329
Short name T321
Test name
Test status
Simulation time 492199575517 ps
CPU time 868.43 seconds
Started Feb 21 12:49:15 PM PST 24
Finished Feb 21 01:03:44 PM PST 24
Peak memory 201512 kb
Host smart-af7a37dd-a653-422c-9a16-b8a3d775f38b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829218329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2829218329
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2156768152
Short name T281
Test name
Test status
Simulation time 487341869199 ps
CPU time 1152.06 seconds
Started Feb 21 12:49:31 PM PST 24
Finished Feb 21 01:08:43 PM PST 24
Peak memory 201548 kb
Host smart-a9a213e0-e6d1-488c-aeff-421e8ed6dbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156768152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2156768152
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.499011795
Short name T207
Test name
Test status
Simulation time 496433581837 ps
CPU time 595.35 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:57:43 PM PST 24
Peak memory 201604 kb
Host smart-080dae3f-cbda-4eb0-b7bc-6442ec924b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499011795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.499011795
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.809623729
Short name T241
Test name
Test status
Simulation time 336905642994 ps
CPU time 744.96 seconds
Started Feb 21 12:47:58 PM PST 24
Finished Feb 21 01:00:24 PM PST 24
Peak memory 201612 kb
Host smart-ec12bc46-5039-47ec-8566-4d92992ec7b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809623729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.809623729
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1950877811
Short name T305
Test name
Test status
Simulation time 162469822022 ps
CPU time 91.06 seconds
Started Feb 21 12:49:30 PM PST 24
Finished Feb 21 12:51:01 PM PST 24
Peak memory 201576 kb
Host smart-9d15c374-86d8-4961-9610-38ea30a693e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950877811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1950877811
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1541063519
Short name T85
Test name
Test status
Simulation time 493232827771 ps
CPU time 1166.97 seconds
Started Feb 21 12:47:40 PM PST 24
Finished Feb 21 01:07:08 PM PST 24
Peak memory 201552 kb
Host smart-6f55c6ca-9474-4947-89c0-7ea612d47cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541063519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1541063519
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.162163917
Short name T324
Test name
Test status
Simulation time 333660740517 ps
CPU time 390.63 seconds
Started Feb 21 12:47:54 PM PST 24
Finished Feb 21 12:54:25 PM PST 24
Peak memory 201544 kb
Host smart-8798ffa9-aa1c-41c0-a143-40ed58d37381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162163917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.162163917
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2229870029
Short name T304
Test name
Test status
Simulation time 163258618015 ps
CPU time 174.12 seconds
Started Feb 21 12:48:11 PM PST 24
Finished Feb 21 12:51:06 PM PST 24
Peak memory 201484 kb
Host smart-ad1e89ba-8b90-46d9-ae18-c51093cc0009
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229870029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2229870029
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1351314082
Short name T359
Test name
Test status
Simulation time 105036438356 ps
CPU time 194.11 seconds
Started Feb 21 12:50:46 PM PST 24
Finished Feb 21 12:54:01 PM PST 24
Peak memory 210224 kb
Host smart-131d54ab-9537-4d19-aaa0-dd1b9addb078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351314082 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1351314082
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1011605593
Short name T227
Test name
Test status
Simulation time 324112619160 ps
CPU time 717.26 seconds
Started Feb 21 12:48:19 PM PST 24
Finished Feb 21 01:00:17 PM PST 24
Peak memory 210176 kb
Host smart-2bf8bf2c-df7e-4bf3-abeb-36dd6f14fbc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011605593 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1011605593
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2442074396
Short name T299
Test name
Test status
Simulation time 378350690739 ps
CPU time 769.4 seconds
Started Feb 21 12:48:43 PM PST 24
Finished Feb 21 01:01:33 PM PST 24
Peak memory 201516 kb
Host smart-cd2f7d5c-5196-446e-8d8f-ce43dd3adf70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442074396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2442074396
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4246653883
Short name T233
Test name
Test status
Simulation time 108272276225 ps
CPU time 150.16 seconds
Started Feb 21 12:48:35 PM PST 24
Finished Feb 21 12:51:05 PM PST 24
Peak memory 217352 kb
Host smart-32d0c5c9-4bca-4df9-9b29-47e0e4dee7d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246653883 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4246653883
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2383117044
Short name T206
Test name
Test status
Simulation time 313065162286 ps
CPU time 692.04 seconds
Started Feb 21 12:49:39 PM PST 24
Finished Feb 21 01:01:12 PM PST 24
Peak memory 201572 kb
Host smart-4e121e58-f0ad-41c8-8963-20eb199f11e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383117044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2383117044
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1755877996
Short name T337
Test name
Test status
Simulation time 495761112113 ps
CPU time 720.11 seconds
Started Feb 21 12:50:02 PM PST 24
Finished Feb 21 01:02:02 PM PST 24
Peak memory 201572 kb
Host smart-cc90884e-57da-4da6-acc4-bd0c3e93e1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755877996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1755877996
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1791785225
Short name T318
Test name
Test status
Simulation time 163659339276 ps
CPU time 102.39 seconds
Started Feb 21 12:50:43 PM PST 24
Finished Feb 21 12:52:27 PM PST 24
Peak memory 201504 kb
Host smart-ad4beba8-cab7-486a-8b71-04716ef0995f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791785225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1791785225
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3343865895
Short name T289
Test name
Test status
Simulation time 175620557790 ps
CPU time 44.18 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:48:02 PM PST 24
Peak memory 201616 kb
Host smart-0e229026-2122-45ff-ab80-f699f1219c1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343865895 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3343865895
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3297655321
Short name T128
Test name
Test status
Simulation time 8542938910 ps
CPU time 23.22 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:26 PM PST 24
Peak memory 201124 kb
Host smart-326ea218-af1b-490a-9364-25a9ebc8ee60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297655321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3297655321
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.842228165
Short name T153
Test name
Test status
Simulation time 493070898393 ps
CPU time 542.15 seconds
Started Feb 21 12:47:22 PM PST 24
Finished Feb 21 12:56:25 PM PST 24
Peak memory 201464 kb
Host smart-dae6dada-4b63-4d4e-b566-258992ea6324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842228165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.842228165
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2981745839
Short name T372
Test name
Test status
Simulation time 310182812675 ps
CPU time 576.45 seconds
Started Feb 21 12:47:34 PM PST 24
Finished Feb 21 12:57:11 PM PST 24
Peak memory 212560 kb
Host smart-8bbb4d00-08a5-40e4-941b-0d150416cb7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981745839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2981745839
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1965931965
Short name T196
Test name
Test status
Simulation time 491665960142 ps
CPU time 180.14 seconds
Started Feb 21 12:48:15 PM PST 24
Finished Feb 21 12:51:15 PM PST 24
Peak memory 201580 kb
Host smart-0d76f4c8-1a70-4aea-b6f0-3ecd826ba027
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965931965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1965931965
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.4282435595
Short name T81
Test name
Test status
Simulation time 491676513973 ps
CPU time 434.61 seconds
Started Feb 21 12:48:26 PM PST 24
Finished Feb 21 12:55:41 PM PST 24
Peak memory 201620 kb
Host smart-6fd87730-e09e-4c88-908c-854a81fc2a75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282435595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.4282435595
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1201467090
Short name T273
Test name
Test status
Simulation time 327767660272 ps
CPU time 740.72 seconds
Started Feb 21 12:48:59 PM PST 24
Finished Feb 21 01:01:20 PM PST 24
Peak memory 201544 kb
Host smart-4ad54b46-9cd9-43e6-8220-4327363d34c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201467090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1201467090
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.532247767
Short name T382
Test name
Test status
Simulation time 90426033864 ps
CPU time 292.56 seconds
Started Feb 21 12:49:25 PM PST 24
Finished Feb 21 12:54:18 PM PST 24
Peak memory 201792 kb
Host smart-6bfacbff-9d25-46b1-b7cd-457f398e3385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532247767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.532247767
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1648480
Short name T292
Test name
Test status
Simulation time 507550294243 ps
CPU time 1235.7 seconds
Started Feb 21 12:50:25 PM PST 24
Finished Feb 21 01:11:01 PM PST 24
Peak memory 201504 kb
Host smart-31942005-7751-4b14-b90a-88692cec62d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wa
keup.1648480
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1707718940
Short name T335
Test name
Test status
Simulation time 161416799793 ps
CPU time 97.77 seconds
Started Feb 21 12:47:09 PM PST 24
Finished Feb 21 12:48:47 PM PST 24
Peak memory 201372 kb
Host smart-9c719fbc-d4bd-4622-8024-f61cf8751492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707718940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1707718940
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2735364479
Short name T880
Test name
Test status
Simulation time 386469735 ps
CPU time 3.13 seconds
Started Feb 21 12:28:25 PM PST 24
Finished Feb 21 12:28:30 PM PST 24
Peak memory 216944 kb
Host smart-c7051540-fda5-459a-bd23-d5f0f57fc0da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735364479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2735364479
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2294257028
Short name T364
Test name
Test status
Simulation time 4247457933 ps
CPU time 3.94 seconds
Started Feb 21 12:28:41 PM PST 24
Finished Feb 21 12:28:47 PM PST 24
Peak memory 201140 kb
Host smart-8de37d10-7970-4482-bdc2-3e79bc557fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294257028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2294257028
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2297779958
Short name T283
Test name
Test status
Simulation time 503448248593 ps
CPU time 1135.73 seconds
Started Feb 21 12:47:03 PM PST 24
Finished Feb 21 01:05:59 PM PST 24
Peak memory 201496 kb
Host smart-0d4d3052-ddec-4fb6-a619-588e88a81d86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297779958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2297779958
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2170820312
Short name T376
Test name
Test status
Simulation time 117539635501 ps
CPU time 410.08 seconds
Started Feb 21 12:47:06 PM PST 24
Finished Feb 21 12:53:56 PM PST 24
Peak memory 201732 kb
Host smart-70612308-7f84-4b76-8a98-0f19cb2330c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170820312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2170820312
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.179590047
Short name T378
Test name
Test status
Simulation time 142218926516 ps
CPU time 523.86 seconds
Started Feb 21 12:47:14 PM PST 24
Finished Feb 21 12:55:58 PM PST 24
Peak memory 201716 kb
Host smart-17401e4f-14a3-4ce6-820a-018ae532e830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179590047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.179590047
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3131665612
Short name T332
Test name
Test status
Simulation time 495950029978 ps
CPU time 1150.53 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 01:06:44 PM PST 24
Peak memory 201464 kb
Host smart-39f113cf-7ebb-4858-9ad2-d5b9aedf4d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131665612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3131665612
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1671903103
Short name T192
Test name
Test status
Simulation time 491234468419 ps
CPU time 1065.87 seconds
Started Feb 21 12:47:43 PM PST 24
Finished Feb 21 01:05:29 PM PST 24
Peak memory 201476 kb
Host smart-9d08166e-7254-4191-9ec0-0a7ff75e362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671903103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1671903103
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1409020738
Short name T19
Test name
Test status
Simulation time 100458595767 ps
CPU time 401 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:54:28 PM PST 24
Peak memory 201852 kb
Host smart-d1c150d5-13cc-4aad-a5a6-055ebf78cadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409020738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1409020738
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3271932447
Short name T346
Test name
Test status
Simulation time 331824709865 ps
CPU time 680.52 seconds
Started Feb 21 12:48:48 PM PST 24
Finished Feb 21 01:00:09 PM PST 24
Peak memory 201448 kb
Host smart-4ee51238-8266-4c87-8fda-4f211e1c38b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271932447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3271932447
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2508349461
Short name T322
Test name
Test status
Simulation time 157795857442 ps
CPU time 370.68 seconds
Started Feb 21 12:49:05 PM PST 24
Finished Feb 21 12:55:17 PM PST 24
Peak memory 201516 kb
Host smart-330d9445-6c20-46b2-a3ce-336a35cca824
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508349461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2508349461
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.890957508
Short name T381
Test name
Test status
Simulation time 145990979839 ps
CPU time 358.81 seconds
Started Feb 21 12:49:09 PM PST 24
Finished Feb 21 12:55:08 PM PST 24
Peak memory 217740 kb
Host smart-92f64bee-60c3-439b-b948-4ad5f1f0d50f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890957508 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.890957508
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2334089247
Short name T247
Test name
Test status
Simulation time 658266660726 ps
CPU time 796.49 seconds
Started Feb 21 12:47:15 PM PST 24
Finished Feb 21 01:00:32 PM PST 24
Peak memory 201508 kb
Host smart-5edf664f-739f-4ea5-a110-7454575273a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334089247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2334089247
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1597365881
Short name T371
Test name
Test status
Simulation time 88663365427 ps
CPU time 268.57 seconds
Started Feb 21 12:49:46 PM PST 24
Finished Feb 21 12:54:15 PM PST 24
Peak memory 210136 kb
Host smart-169dc920-1bba-4de1-bda4-578f066c2e82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597365881 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1597365881
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3867931297
Short name T374
Test name
Test status
Simulation time 116840441506 ps
CPU time 571.2 seconds
Started Feb 21 12:50:33 PM PST 24
Finished Feb 21 01:00:05 PM PST 24
Peak memory 201804 kb
Host smart-e32e9a2f-a0cc-40ef-af4a-b8844612222c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867931297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3867931297
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1233042551
Short name T373
Test name
Test status
Simulation time 133653965390 ps
CPU time 490.82 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:55:30 PM PST 24
Peak memory 201700 kb
Host smart-1ab61552-812b-491e-be58-c211a0f8f70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233042551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1233042551
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.487393670
Short name T861
Test name
Test status
Simulation time 1955612693 ps
CPU time 1.67 seconds
Started Feb 21 12:28:23 PM PST 24
Finished Feb 21 12:28:26 PM PST 24
Peak memory 200956 kb
Host smart-06c28e08-b3f5-4a4a-a7a8-1f83c31f56df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487393670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.487393670
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.65186997
Short name T111
Test name
Test status
Simulation time 31369134432 ps
CPU time 38.69 seconds
Started Feb 21 12:28:20 PM PST 24
Finished Feb 21 12:29:00 PM PST 24
Peak memory 201180 kb
Host smart-a8dccf61-1cf9-4227-bcf9-6ebeeabcf855
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65186997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_ba
sh.65186997
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2969942852
Short name T868
Test name
Test status
Simulation time 1382119328 ps
CPU time 1.55 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:31 PM PST 24
Peak memory 199636 kb
Host smart-6ae53e3e-3b4c-4453-8bac-1469ecb31959
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969942852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2969942852
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.126975908
Short name T864
Test name
Test status
Simulation time 429585867 ps
CPU time 2.09 seconds
Started Feb 21 12:28:22 PM PST 24
Finished Feb 21 12:28:26 PM PST 24
Peak memory 200848 kb
Host smart-ee573899-ab31-4a3d-8eb7-19401bb4262b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126975908 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.126975908
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.673841645
Short name T104
Test name
Test status
Simulation time 445625631 ps
CPU time 1.72 seconds
Started Feb 21 12:29:29 PM PST 24
Finished Feb 21 12:29:31 PM PST 24
Peak memory 200244 kb
Host smart-1c50fb40-d679-4e6a-9201-48b303ddc528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673841645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.673841645
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1495732917
Short name T872
Test name
Test status
Simulation time 405384613 ps
CPU time 0.9 seconds
Started Feb 21 12:28:15 PM PST 24
Finished Feb 21 12:28:19 PM PST 24
Peak memory 201004 kb
Host smart-11bbf557-5938-4a58-80e2-30f06b4f477f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495732917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1495732917
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2010925540
Short name T118
Test name
Test status
Simulation time 2575571392 ps
CPU time 3.74 seconds
Started Feb 21 12:28:22 PM PST 24
Finished Feb 21 12:28:27 PM PST 24
Peak memory 200848 kb
Host smart-0f6384a8-6511-4917-85e3-c461e6c3da97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010925540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2010925540
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3228537614
Short name T835
Test name
Test status
Simulation time 4287140858 ps
CPU time 10.69 seconds
Started Feb 21 12:28:20 PM PST 24
Finished Feb 21 12:28:32 PM PST 24
Peak memory 201124 kb
Host smart-cc61014f-cc63-4faa-b6e6-dbf9d2fcbdcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228537614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3228537614
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1966184137
Short name T907
Test name
Test status
Simulation time 910972444 ps
CPU time 3.39 seconds
Started Feb 21 12:29:46 PM PST 24
Finished Feb 21 12:29:50 PM PST 24
Peak memory 200952 kb
Host smart-47750a99-888c-48a9-b7f1-7aa95186a1d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966184137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1966184137
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2474919579
Short name T101
Test name
Test status
Simulation time 1237702029 ps
CPU time 1.2 seconds
Started Feb 21 12:28:22 PM PST 24
Finished Feb 21 12:28:25 PM PST 24
Peak memory 200816 kb
Host smart-9964cc70-c02c-4d6b-a52d-3674fc899840
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474919579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2474919579
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1606895386
Short name T809
Test name
Test status
Simulation time 485525432 ps
CPU time 1.4 seconds
Started Feb 21 12:28:18 PM PST 24
Finished Feb 21 12:28:20 PM PST 24
Peak memory 200868 kb
Host smart-4aabc719-b659-4b0d-8073-b81934ef22a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606895386 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1606895386
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3274344138
Short name T873
Test name
Test status
Simulation time 507957558 ps
CPU time 1.84 seconds
Started Feb 21 12:29:46 PM PST 24
Finished Feb 21 12:29:48 PM PST 24
Peak memory 200672 kb
Host smart-93b81674-59c2-4dfd-97f7-116113f4a7ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274344138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3274344138
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1674799406
Short name T887
Test name
Test status
Simulation time 4745676034 ps
CPU time 18.76 seconds
Started Feb 21 12:28:22 PM PST 24
Finished Feb 21 12:28:42 PM PST 24
Peak memory 201148 kb
Host smart-0907aeb1-649c-412d-b1b4-548ba6acef2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674799406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1674799406
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.990832157
Short name T845
Test name
Test status
Simulation time 829297797 ps
CPU time 2.27 seconds
Started Feb 21 12:29:29 PM PST 24
Finished Feb 21 12:29:31 PM PST 24
Peak memory 199916 kb
Host smart-b05ee581-4d0c-483e-baba-f0d8733cd87a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990832157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.990832157
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3077488406
Short name T38
Test name
Test status
Simulation time 3981048140 ps
CPU time 10.84 seconds
Started Feb 21 12:28:22 PM PST 24
Finished Feb 21 12:28:34 PM PST 24
Peak memory 201136 kb
Host smart-a0d50224-a08c-411b-8f83-d3bf04e2e790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077488406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3077488406
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.81567801
Short name T901
Test name
Test status
Simulation time 422841783 ps
CPU time 1.83 seconds
Started Feb 21 12:28:33 PM PST 24
Finished Feb 21 12:28:36 PM PST 24
Peak memory 200876 kb
Host smart-8450dbd2-d0f2-4c0f-bf8c-ab356e32b6b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81567801 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.81567801
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.226916483
Short name T105
Test name
Test status
Simulation time 523880971 ps
CPU time 2.28 seconds
Started Feb 21 12:28:35 PM PST 24
Finished Feb 21 12:28:38 PM PST 24
Peak memory 200808 kb
Host smart-d05cf528-8f33-4440-a0be-06bb881281ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226916483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.226916483
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.303957094
Short name T846
Test name
Test status
Simulation time 314806679 ps
CPU time 0.85 seconds
Started Feb 21 12:28:22 PM PST 24
Finished Feb 21 12:28:24 PM PST 24
Peak memory 200804 kb
Host smart-951155db-1348-4362-902d-4a006c3796fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303957094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.303957094
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1627029541
Short name T859
Test name
Test status
Simulation time 4171992604 ps
CPU time 3.02 seconds
Started Feb 21 12:28:30 PM PST 24
Finished Feb 21 12:28:34 PM PST 24
Peak memory 201484 kb
Host smart-79ffcac9-c4be-4026-9a7b-4e32345f6d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627029541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1627029541
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.516907777
Short name T885
Test name
Test status
Simulation time 569337980 ps
CPU time 1.68 seconds
Started Feb 21 12:28:29 PM PST 24
Finished Feb 21 12:28:31 PM PST 24
Peak memory 201044 kb
Host smart-58f7019d-ddc8-4bef-916f-397f585f8058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516907777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.516907777
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.345462304
Short name T75
Test name
Test status
Simulation time 4211395419 ps
CPU time 4.22 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:33 PM PST 24
Peak memory 201020 kb
Host smart-18e708a5-d50a-46dd-939b-e237c35aaf5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345462304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.345462304
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2213332069
Short name T850
Test name
Test status
Simulation time 401354668 ps
CPU time 1.27 seconds
Started Feb 21 12:28:27 PM PST 24
Finished Feb 21 12:28:30 PM PST 24
Peak memory 200872 kb
Host smart-ceb83206-7744-46c3-b20a-1095518762ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213332069 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2213332069
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.255801913
Short name T115
Test name
Test status
Simulation time 335680742 ps
CPU time 1.42 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:43 PM PST 24
Peak memory 200784 kb
Host smart-2be7a567-ef8f-4e97-9212-51f358ca22d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255801913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.255801913
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1392951812
Short name T833
Test name
Test status
Simulation time 441165589 ps
CPU time 1.66 seconds
Started Feb 21 12:28:39 PM PST 24
Finished Feb 21 12:28:42 PM PST 24
Peak memory 200328 kb
Host smart-528b49b7-512f-4d88-b1e7-860ac13b8fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392951812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1392951812
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2431264054
Short name T817
Test name
Test status
Simulation time 2425387291 ps
CPU time 2.01 seconds
Started Feb 21 12:28:21 PM PST 24
Finished Feb 21 12:28:24 PM PST 24
Peak memory 200848 kb
Host smart-56bad154-f347-4b38-b1f8-29b41681d888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431264054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2431264054
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1878502846
Short name T842
Test name
Test status
Simulation time 485779622 ps
CPU time 2.78 seconds
Started Feb 21 12:28:32 PM PST 24
Finished Feb 21 12:28:36 PM PST 24
Peak memory 200984 kb
Host smart-ac155147-bd14-46b4-bbcd-4a8abf4be70c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878502846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1878502846
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4294027472
Short name T832
Test name
Test status
Simulation time 527150416 ps
CPU time 2.18 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:47 PM PST 24
Peak memory 200856 kb
Host smart-9dd24304-182b-4ded-a988-b5b8eaace6b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294027472 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4294027472
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4001126477
Short name T839
Test name
Test status
Simulation time 372971063 ps
CPU time 0.9 seconds
Started Feb 21 12:28:41 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 200772 kb
Host smart-c9d73046-0e2c-44a0-ab8a-fe53f88e8fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001126477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4001126477
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.71286756
Short name T897
Test name
Test status
Simulation time 369152475 ps
CPU time 0.92 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:30 PM PST 24
Peak memory 200764 kb
Host smart-2b291e40-9633-4255-a999-8b1699ef2c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71286756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.71286756
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3996169112
Short name T905
Test name
Test status
Simulation time 4192861715 ps
CPU time 5.87 seconds
Started Feb 21 12:28:33 PM PST 24
Finished Feb 21 12:28:40 PM PST 24
Peak memory 201064 kb
Host smart-db79fc06-b3a2-4ee8-8f01-dfef5df95036
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996169112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3996169112
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1577304040
Short name T884
Test name
Test status
Simulation time 548099999 ps
CPU time 3.19 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 201032 kb
Host smart-2dc456de-b3c6-4f3b-bbd8-f49720452e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577304040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1577304040
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2266239295
Short name T814
Test name
Test status
Simulation time 4532534302 ps
CPU time 2.61 seconds
Started Feb 21 12:28:31 PM PST 24
Finished Feb 21 12:28:34 PM PST 24
Peak memory 201168 kb
Host smart-7c7ee12b-04bb-483f-a82b-ba9fa7265c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266239295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2266239295
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4276263263
Short name T896
Test name
Test status
Simulation time 443328937 ps
CPU time 1.07 seconds
Started Feb 21 12:28:33 PM PST 24
Finished Feb 21 12:28:36 PM PST 24
Peak memory 200840 kb
Host smart-09e3d667-9457-4ba0-b70d-af4eed222d3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276263263 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4276263263
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.396483048
Short name T913
Test name
Test status
Simulation time 377113900 ps
CPU time 1.04 seconds
Started Feb 21 12:28:35 PM PST 24
Finished Feb 21 12:28:36 PM PST 24
Peak memory 201140 kb
Host smart-f7732c11-97f5-434d-8024-c88eaa5f8034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396483048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.396483048
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3820805511
Short name T800
Test name
Test status
Simulation time 527804903 ps
CPU time 1.08 seconds
Started Feb 21 12:28:31 PM PST 24
Finished Feb 21 12:28:33 PM PST 24
Peak memory 200984 kb
Host smart-8fe16bbd-9c3b-4306-88a6-9f00592c1c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820805511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3820805511
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1238950301
Short name T847
Test name
Test status
Simulation time 2738568213 ps
CPU time 1.37 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 200784 kb
Host smart-aba24625-63c8-4d56-99d9-db208be0ee8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238950301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1238950301
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3965955194
Short name T892
Test name
Test status
Simulation time 8318763503 ps
CPU time 5.58 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:53 PM PST 24
Peak memory 201060 kb
Host smart-01418217-46ff-434a-9b1e-5b06096addac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965955194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3965955194
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.548698232
Short name T877
Test name
Test status
Simulation time 487341556 ps
CPU time 1.28 seconds
Started Feb 21 12:28:36 PM PST 24
Finished Feb 21 12:28:37 PM PST 24
Peak memory 200884 kb
Host smart-71b4be87-a6ce-43dc-aa7c-05b8ec98c33e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548698232 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.548698232
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1801795019
Short name T844
Test name
Test status
Simulation time 506378034 ps
CPU time 1.12 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:49 PM PST 24
Peak memory 200752 kb
Host smart-2c3896a6-ce31-4c67-8006-3d6ffa0e9cd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801795019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1801795019
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2097347886
Short name T815
Test name
Test status
Simulation time 299015135 ps
CPU time 1.27 seconds
Started Feb 21 12:28:41 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 200620 kb
Host smart-0402fc33-1b91-4cef-827b-6cfecde9f6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097347886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2097347886
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1482001704
Short name T849
Test name
Test status
Simulation time 4127019907 ps
CPU time 13.49 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:58 PM PST 24
Peak memory 201208 kb
Host smart-30459eb5-7bb2-4caa-b79a-51c7dc968ede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482001704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1482001704
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2494166743
Short name T854
Test name
Test status
Simulation time 365456492 ps
CPU time 2.53 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:47 PM PST 24
Peak memory 209288 kb
Host smart-af97cb71-2204-42f0-92ce-094a1f233d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494166743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2494166743
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2643913343
Short name T852
Test name
Test status
Simulation time 7681012227 ps
CPU time 10.59 seconds
Started Feb 21 12:28:43 PM PST 24
Finished Feb 21 12:28:54 PM PST 24
Peak memory 201120 kb
Host smart-5732872b-39d0-489c-8f0b-3594c93c446e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643913343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2643913343
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3590704133
Short name T889
Test name
Test status
Simulation time 400685663 ps
CPU time 1.39 seconds
Started Feb 21 12:28:41 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 200832 kb
Host smart-b39d9b76-8a82-459b-a48d-2e24b9e56583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590704133 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3590704133
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2969793378
Short name T824
Test name
Test status
Simulation time 614309169 ps
CPU time 0.9 seconds
Started Feb 21 12:28:38 PM PST 24
Finished Feb 21 12:28:40 PM PST 24
Peak memory 200720 kb
Host smart-c612b81e-b8ed-497a-b408-7d2de543f8db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969793378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2969793378
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2416493975
Short name T853
Test name
Test status
Simulation time 316606242 ps
CPU time 1.42 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:49 PM PST 24
Peak memory 200740 kb
Host smart-0a4015d6-8197-4990-95e0-f221466085ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416493975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2416493975
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2081919046
Short name T865
Test name
Test status
Simulation time 4816631309 ps
CPU time 11.82 seconds
Started Feb 21 12:28:42 PM PST 24
Finished Feb 21 12:28:55 PM PST 24
Peak memory 201148 kb
Host smart-b2718aa9-1f1a-46c1-a88e-05858ff9f68a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081919046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2081919046
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1456691011
Short name T858
Test name
Test status
Simulation time 576298685 ps
CPU time 2.84 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:51 PM PST 24
Peak memory 201076 kb
Host smart-f7403fe7-14b9-48a7-b239-d4d018c57dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456691011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1456691011
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4188966142
Short name T366
Test name
Test status
Simulation time 4367724421 ps
CPU time 11.86 seconds
Started Feb 21 12:28:41 PM PST 24
Finished Feb 21 12:28:55 PM PST 24
Peak memory 201200 kb
Host smart-ef7773dc-0ecd-4fb1-b2af-f2d4913e56c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188966142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4188966142
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2034465396
Short name T77
Test name
Test status
Simulation time 588177857 ps
CPU time 1.13 seconds
Started Feb 21 12:28:42 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 200856 kb
Host smart-1632fd64-4607-40d2-8316-3b62a04bb3ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034465396 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2034465396
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1013849197
Short name T116
Test name
Test status
Simulation time 325178770 ps
CPU time 1.49 seconds
Started Feb 21 12:28:37 PM PST 24
Finished Feb 21 12:28:39 PM PST 24
Peak memory 200788 kb
Host smart-de33074c-a45d-45ab-ae33-8baff58a8444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013849197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1013849197
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1556490853
Short name T838
Test name
Test status
Simulation time 386760271 ps
CPU time 1.52 seconds
Started Feb 21 12:28:38 PM PST 24
Finished Feb 21 12:28:40 PM PST 24
Peak memory 200552 kb
Host smart-dc1a5b86-415a-41be-a6bb-dc17c87cfd1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556490853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1556490853
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.821535497
Short name T900
Test name
Test status
Simulation time 2960296893 ps
CPU time 3.82 seconds
Started Feb 21 12:28:41 PM PST 24
Finished Feb 21 12:28:47 PM PST 24
Peak memory 201020 kb
Host smart-e95e8d99-9f4c-4ed1-b7d4-d11bee30d7c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821535497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.821535497
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3107415388
Short name T894
Test name
Test status
Simulation time 481240316 ps
CPU time 1.47 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:46 PM PST 24
Peak memory 201172 kb
Host smart-63bb572f-3ac4-4a31-8f32-775145bfa5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107415388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3107415388
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2437491318
Short name T893
Test name
Test status
Simulation time 533537555 ps
CPU time 1.39 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:49 PM PST 24
Peak memory 200812 kb
Host smart-c3bf3239-5d9d-48a3-a519-65552e482b8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437491318 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2437491318
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2472987451
Short name T891
Test name
Test status
Simulation time 391710809 ps
CPU time 1.07 seconds
Started Feb 21 12:28:39 PM PST 24
Finished Feb 21 12:28:41 PM PST 24
Peak memory 200748 kb
Host smart-2c0cb9a9-cdca-492e-9126-7fb8d7a1e5aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472987451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2472987451
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.823752386
Short name T895
Test name
Test status
Simulation time 386786351 ps
CPU time 0.88 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 200628 kb
Host smart-4e010cd3-2f02-46bf-b1d7-33c2adc39185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823752386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.823752386
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3180119974
Short name T899
Test name
Test status
Simulation time 3800318750 ps
CPU time 11.91 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:54 PM PST 24
Peak memory 201116 kb
Host smart-a9844a5c-3cbe-433f-891d-fb7f1cab7210
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180119974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3180119974
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.534084783
Short name T80
Test name
Test status
Simulation time 900167631 ps
CPU time 2.02 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 201084 kb
Host smart-7cd3fc48-4a88-478a-94c7-5a44a47d2b53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534084783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.534084783
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1856269940
Short name T807
Test name
Test status
Simulation time 563888661 ps
CPU time 2.09 seconds
Started Feb 21 12:28:35 PM PST 24
Finished Feb 21 12:28:37 PM PST 24
Peak memory 200880 kb
Host smart-13ca91e6-f599-4235-a096-79cec39a256c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856269940 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1856269940
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3975825017
Short name T856
Test name
Test status
Simulation time 535903298 ps
CPU time 1.03 seconds
Started Feb 21 12:28:36 PM PST 24
Finished Feb 21 12:28:37 PM PST 24
Peak memory 200832 kb
Host smart-653e0406-baf4-4a4c-bc16-2af243bfd583
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975825017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3975825017
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3958849114
Short name T798
Test name
Test status
Simulation time 284292357 ps
CPU time 1.3 seconds
Started Feb 21 12:28:41 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 200796 kb
Host smart-0546eed6-35d3-4226-a632-300105206b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958849114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3958849114
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.515926972
Short name T27
Test name
Test status
Simulation time 3734283634 ps
CPU time 14.83 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:29:02 PM PST 24
Peak memory 201084 kb
Host smart-59df0cda-9c21-486f-9519-be7faf380f50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515926972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.515926972
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3454326229
Short name T906
Test name
Test status
Simulation time 509717305 ps
CPU time 2.09 seconds
Started Feb 21 12:28:36 PM PST 24
Finished Feb 21 12:28:39 PM PST 24
Peak memory 201080 kb
Host smart-355e2b1d-ad85-4dce-88b6-c4aa76e62538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454326229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3454326229
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2416891571
Short name T365
Test name
Test status
Simulation time 4824716474 ps
CPU time 4.42 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:07 PM PST 24
Peak memory 201208 kb
Host smart-13421e64-457d-412f-9de4-555075d10185
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416891571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2416891571
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3577723531
Short name T40
Test name
Test status
Simulation time 460793585 ps
CPU time 1.39 seconds
Started Feb 21 12:28:48 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 200844 kb
Host smart-8298c4fa-35c4-4535-b664-a9924afc3b13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577723531 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3577723531
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.238670973
Short name T108
Test name
Test status
Simulation time 539620586 ps
CPU time 1.4 seconds
Started Feb 21 12:28:35 PM PST 24
Finished Feb 21 12:28:37 PM PST 24
Peak memory 200836 kb
Host smart-157e0a99-0918-4253-b673-dd9d051ba27f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238670973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.238670973
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.500829429
Short name T869
Test name
Test status
Simulation time 402641781 ps
CPU time 1.67 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 200772 kb
Host smart-a90298eb-8714-4f9c-ae3b-ea27a027f805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500829429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.500829429
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2557793188
Short name T117
Test name
Test status
Simulation time 2092275408 ps
CPU time 5.26 seconds
Started Feb 21 12:28:37 PM PST 24
Finished Feb 21 12:28:42 PM PST 24
Peak memory 200788 kb
Host smart-13a36f53-984b-4325-be95-ce8e9c19dcb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557793188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2557793188
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1748161679
Short name T42
Test name
Test status
Simulation time 925653536 ps
CPU time 2.02 seconds
Started Feb 21 12:28:29 PM PST 24
Finished Feb 21 12:28:32 PM PST 24
Peak memory 201024 kb
Host smart-27a5f6cc-444e-4f3a-8e53-59a7e95b11bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748161679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1748161679
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1498994258
Short name T867
Test name
Test status
Simulation time 4787587369 ps
CPU time 2.43 seconds
Started Feb 21 12:28:38 PM PST 24
Finished Feb 21 12:28:41 PM PST 24
Peak memory 201176 kb
Host smart-d3819553-1678-439a-9cce-dbcd9c3d7b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498994258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1498994258
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2181601886
Short name T103
Test name
Test status
Simulation time 699381340 ps
CPU time 2.27 seconds
Started Feb 21 12:28:32 PM PST 24
Finished Feb 21 12:28:35 PM PST 24
Peak memory 200992 kb
Host smart-fd976bbc-f14c-4ef9-87ab-2b6b9e8a4f36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181601886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2181601886
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3260345668
Short name T113
Test name
Test status
Simulation time 1483374454 ps
CPU time 4.83 seconds
Started Feb 21 12:28:21 PM PST 24
Finished Feb 21 12:28:27 PM PST 24
Peak memory 201056 kb
Host smart-e8f79faa-e29f-4327-bb2b-794323062cb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260345668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3260345668
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2089429180
Short name T825
Test name
Test status
Simulation time 1133015309 ps
CPU time 2.47 seconds
Started Feb 21 12:28:24 PM PST 24
Finished Feb 21 12:28:28 PM PST 24
Peak memory 201140 kb
Host smart-7349b48d-a672-4d90-9617-c954ea90aa7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089429180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2089429180
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2213579778
Short name T904
Test name
Test status
Simulation time 383802075 ps
CPU time 1.25 seconds
Started Feb 21 12:28:31 PM PST 24
Finished Feb 21 12:28:33 PM PST 24
Peak memory 200872 kb
Host smart-072c1475-b58c-485a-a690-e0681ac19725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213579778 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2213579778
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3355573363
Short name T102
Test name
Test status
Simulation time 426001332 ps
CPU time 0.98 seconds
Started Feb 21 12:28:30 PM PST 24
Finished Feb 21 12:28:32 PM PST 24
Peak memory 201172 kb
Host smart-15ae176b-00f1-4b29-afdc-b10b74aa1072
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355573363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3355573363
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3397086372
Short name T827
Test name
Test status
Simulation time 424299003 ps
CPU time 1.71 seconds
Started Feb 21 12:28:18 PM PST 24
Finished Feb 21 12:28:21 PM PST 24
Peak memory 200612 kb
Host smart-46a29ffa-f7c6-4c85-9231-be761418e6ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397086372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3397086372
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1825239955
Short name T823
Test name
Test status
Simulation time 4393269875 ps
CPU time 3.19 seconds
Started Feb 21 12:28:16 PM PST 24
Finished Feb 21 12:28:21 PM PST 24
Peak memory 200948 kb
Host smart-c83002ab-a0ff-4844-b8dd-cd48ce0ae0a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825239955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1825239955
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4210523230
Short name T129
Test name
Test status
Simulation time 900701216 ps
CPU time 2.91 seconds
Started Feb 21 12:29:46 PM PST 24
Finished Feb 21 12:29:49 PM PST 24
Peak memory 201000 kb
Host smart-62634d51-64c3-4d54-9d8e-6f20ee4777a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210523230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4210523230
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.571608954
Short name T829
Test name
Test status
Simulation time 8631487092 ps
CPU time 13.22 seconds
Started Feb 21 12:28:11 PM PST 24
Finished Feb 21 12:28:25 PM PST 24
Peak memory 201528 kb
Host smart-9aba1836-732a-42c9-9d94-419f210e7f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571608954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.571608954
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3673600809
Short name T866
Test name
Test status
Simulation time 421373558 ps
CPU time 1.2 seconds
Started Feb 21 12:28:48 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 200580 kb
Host smart-9d34a468-1081-44ad-b7b6-ec6da9d690d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673600809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3673600809
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1193873382
Short name T837
Test name
Test status
Simulation time 514639105 ps
CPU time 1.06 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:49 PM PST 24
Peak memory 200584 kb
Host smart-83f66c39-27ec-4aee-8250-04166832729f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193873382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1193873382
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2210906080
Short name T871
Test name
Test status
Simulation time 435336416 ps
CPU time 1.16 seconds
Started Feb 21 12:28:48 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 200692 kb
Host smart-4baf2823-e98f-49c9-9957-68ca163f56ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210906080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2210906080
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.519326592
Short name T810
Test name
Test status
Simulation time 296794128 ps
CPU time 0.81 seconds
Started Feb 21 12:28:42 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 200784 kb
Host smart-6ec99aa9-117c-4d75-b678-8a2676bcb5c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519326592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.519326592
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.46808717
Short name T808
Test name
Test status
Simulation time 358082856 ps
CPU time 1.5 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 200596 kb
Host smart-c8ea5291-1f46-4739-9428-1b5d5fad1988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46808717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.46808717
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3015004302
Short name T840
Test name
Test status
Simulation time 459064785 ps
CPU time 0.78 seconds
Started Feb 21 12:28:49 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 201164 kb
Host smart-3d5b433d-d697-44b7-b376-21f29cd2c6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015004302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3015004302
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.525351101
Short name T882
Test name
Test status
Simulation time 402083797 ps
CPU time 0.9 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 200628 kb
Host smart-62eea580-17e3-4c0a-8698-7a13e7a0efcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525351101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.525351101
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3729271022
Short name T805
Test name
Test status
Simulation time 414661623 ps
CPU time 1.16 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:46 PM PST 24
Peak memory 200740 kb
Host smart-ff3c783f-acf1-4191-87af-3bf85c09d42e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729271022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3729271022
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2932002042
Short name T811
Test name
Test status
Simulation time 520127510 ps
CPU time 0.86 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:49 PM PST 24
Peak memory 200772 kb
Host smart-e3ac675b-1fa0-4c25-ad61-9909e57f2d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932002042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2932002042
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4244320621
Short name T841
Test name
Test status
Simulation time 504563429 ps
CPU time 1.77 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:46 PM PST 24
Peak memory 200744 kb
Host smart-a5f73eb1-4c03-4a36-a831-535152e907a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244320621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4244320621
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3194313823
Short name T120
Test name
Test status
Simulation time 911244387 ps
CPU time 4.06 seconds
Started Feb 21 12:28:24 PM PST 24
Finished Feb 21 12:28:29 PM PST 24
Peak memory 201092 kb
Host smart-6d2d7811-da0b-4171-b861-83a777abf7cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194313823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3194313823
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3028396229
Short name T112
Test name
Test status
Simulation time 23760288811 ps
CPU time 101.84 seconds
Started Feb 21 12:28:39 PM PST 24
Finished Feb 21 12:30:23 PM PST 24
Peak memory 200988 kb
Host smart-b0a6480a-7050-4fda-9ed9-658f55525e12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028396229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3028396229
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.955302128
Short name T109
Test name
Test status
Simulation time 775871131 ps
CPU time 2.48 seconds
Started Feb 21 12:28:39 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 200580 kb
Host smart-38397976-562a-4550-a8a8-8417bf420096
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955302128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.955302128
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3067012256
Short name T860
Test name
Test status
Simulation time 470717653 ps
CPU time 1.14 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:30 PM PST 24
Peak memory 210532 kb
Host smart-771afa08-4c79-4009-af7d-5d9cd224a5be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067012256 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3067012256
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1628436092
Short name T831
Test name
Test status
Simulation time 558047007 ps
CPU time 1.16 seconds
Started Feb 21 12:28:26 PM PST 24
Finished Feb 21 12:28:28 PM PST 24
Peak memory 201140 kb
Host smart-c558a091-3ebd-48bf-b70c-24977d450458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628436092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1628436092
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.503242990
Short name T804
Test name
Test status
Simulation time 412176251 ps
CPU time 1.18 seconds
Started Feb 21 12:28:30 PM PST 24
Finished Feb 21 12:28:32 PM PST 24
Peak memory 200640 kb
Host smart-d76ff616-2fbb-434e-a335-2732a462a660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503242990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.503242990
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2347788587
Short name T863
Test name
Test status
Simulation time 2656216746 ps
CPU time 4.21 seconds
Started Feb 21 12:28:31 PM PST 24
Finished Feb 21 12:28:36 PM PST 24
Peak memory 200872 kb
Host smart-fe513f33-a47f-45c2-8fc4-5eff10c60ea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347788587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2347788587
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2096835909
Short name T890
Test name
Test status
Simulation time 527591519 ps
CPU time 1.88 seconds
Started Feb 21 12:28:42 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 201108 kb
Host smart-c1ce2d83-ec3b-4dcd-9762-51fa68ba4f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096835909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2096835909
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2992791194
Short name T127
Test name
Test status
Simulation time 4608206391 ps
CPU time 4.01 seconds
Started Feb 21 12:28:27 PM PST 24
Finished Feb 21 12:28:32 PM PST 24
Peak memory 201176 kb
Host smart-ba117183-3af0-454c-ae59-bdb7e7e859e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992791194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2992791194
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.991900817
Short name T799
Test name
Test status
Simulation time 486453706 ps
CPU time 1.8 seconds
Started Feb 21 12:28:38 PM PST 24
Finished Feb 21 12:28:40 PM PST 24
Peak memory 200584 kb
Host smart-71298ead-560d-4807-9af4-7326d55c6f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991900817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.991900817
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3916621113
Short name T876
Test name
Test status
Simulation time 442567789 ps
CPU time 0.72 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:42 PM PST 24
Peak memory 200736 kb
Host smart-f2084f4e-9d76-4435-8478-a3f1e2680689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916621113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3916621113
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3007778305
Short name T806
Test name
Test status
Simulation time 357191817 ps
CPU time 1.56 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:43 PM PST 24
Peak memory 200544 kb
Host smart-5c109a09-ef17-47f0-9c5d-ce4916b54532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007778305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3007778305
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.641955260
Short name T910
Test name
Test status
Simulation time 375155291 ps
CPU time 0.96 seconds
Started Feb 21 12:28:36 PM PST 24
Finished Feb 21 12:28:38 PM PST 24
Peak memory 199624 kb
Host smart-eceadcb6-d48d-41e9-b9c4-27366b97b551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641955260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.641955260
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.53418483
Short name T796
Test name
Test status
Simulation time 506290597 ps
CPU time 1.7 seconds
Started Feb 21 12:28:37 PM PST 24
Finished Feb 21 12:28:39 PM PST 24
Peak memory 200660 kb
Host smart-a3e1b121-3488-4df8-b929-d0f03fd313b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53418483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.53418483
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1122460876
Short name T836
Test name
Test status
Simulation time 535257396 ps
CPU time 1.95 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 200724 kb
Host smart-2d5e4708-5565-4161-b909-0a6434197393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122460876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1122460876
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2117807949
Short name T820
Test name
Test status
Simulation time 430395909 ps
CPU time 0.74 seconds
Started Feb 21 12:28:41 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 200772 kb
Host smart-cc9a68f1-e6f5-4ef5-ad67-4b77251a99f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117807949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2117807949
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3280843065
Short name T822
Test name
Test status
Simulation time 384128076 ps
CPU time 0.79 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 200628 kb
Host smart-13ca5d5b-6cc5-48bd-b2b8-31f1df7a0ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280843065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3280843065
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3726819315
Short name T886
Test name
Test status
Simulation time 432356078 ps
CPU time 0.74 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 200632 kb
Host smart-a95a868f-adc8-4547-877f-bcf2db60bd84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726819315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3726819315
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3643215893
Short name T883
Test name
Test status
Simulation time 382667427 ps
CPU time 0.86 seconds
Started Feb 21 12:28:36 PM PST 24
Finished Feb 21 12:28:38 PM PST 24
Peak memory 200616 kb
Host smart-3a4ca94c-cc97-4533-98f9-5ac0344feaa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643215893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3643215893
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3120565113
Short name T110
Test name
Test status
Simulation time 823209557 ps
CPU time 2.27 seconds
Started Feb 21 12:28:39 PM PST 24
Finished Feb 21 12:28:43 PM PST 24
Peak memory 200868 kb
Host smart-343b3880-bddc-4426-ae68-633200032e8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120565113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3120565113
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4336562
Short name T911
Test name
Test status
Simulation time 26962669971 ps
CPU time 63.2 seconds
Started Feb 21 12:28:30 PM PST 24
Finished Feb 21 12:29:34 PM PST 24
Peak memory 201184 kb
Host smart-9af49d90-759b-44b7-aa65-0b43a7a8638a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4336562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bas
h.4336562
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1444169875
Short name T875
Test name
Test status
Simulation time 766951924 ps
CPU time 2.58 seconds
Started Feb 21 12:28:35 PM PST 24
Finished Feb 21 12:28:38 PM PST 24
Peak memory 200828 kb
Host smart-75d3594a-af5f-4978-ac13-9af9f6cdcbab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444169875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1444169875
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.868132705
Short name T126
Test name
Test status
Simulation time 660734323 ps
CPU time 1.28 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:43 PM PST 24
Peak memory 201128 kb
Host smart-3fce25b5-218c-46d0-a94b-3ff5f65e1c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868132705 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.868132705
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.134114287
Short name T119
Test name
Test status
Simulation time 508782805 ps
CPU time 2.12 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:31 PM PST 24
Peak memory 200796 kb
Host smart-1ac615d5-4551-4b55-9f81-9442d6a6234d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134114287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.134114287
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2774961668
Short name T888
Test name
Test status
Simulation time 370119271 ps
CPU time 0.86 seconds
Started Feb 21 12:28:31 PM PST 24
Finished Feb 21 12:28:33 PM PST 24
Peak memory 200632 kb
Host smart-df14e150-732a-488f-92ca-8e855f12c4e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774961668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2774961668
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1462226932
Short name T828
Test name
Test status
Simulation time 4410575825 ps
CPU time 3.65 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 201052 kb
Host smart-e4fc793e-9aa6-4269-8275-d2c393a9f59f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462226932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1462226932
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3709937135
Short name T37
Test name
Test status
Simulation time 4242146121 ps
CPU time 6.2 seconds
Started Feb 21 12:28:26 PM PST 24
Finished Feb 21 12:28:33 PM PST 24
Peak memory 201160 kb
Host smart-c53d4665-8d39-4d97-9fae-b63ab8f89803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709937135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3709937135
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3644210033
Short name T816
Test name
Test status
Simulation time 443380571 ps
CPU time 1.62 seconds
Started Feb 21 12:28:36 PM PST 24
Finished Feb 21 12:28:39 PM PST 24
Peak memory 200768 kb
Host smart-bf86a8ae-5fb7-46ef-8985-45dedf5b977f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644210033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3644210033
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2085772719
Short name T874
Test name
Test status
Simulation time 310569815 ps
CPU time 0.88 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:03 PM PST 24
Peak memory 200788 kb
Host smart-2b103f53-0d47-4c26-8aae-ba3aacb3fbaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085772719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2085772719
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.862781423
Short name T834
Test name
Test status
Simulation time 503379140 ps
CPU time 1.07 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:43 PM PST 24
Peak memory 200556 kb
Host smart-18f6f5f0-efaa-493c-8887-da4b54f33013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862781423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.862781423
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.632110774
Short name T912
Test name
Test status
Simulation time 356263804 ps
CPU time 0.9 seconds
Started Feb 21 12:28:49 PM PST 24
Finished Feb 21 12:28:51 PM PST 24
Peak memory 200700 kb
Host smart-776feaad-db84-487f-b887-fb18dfa14543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632110774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.632110774
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2920874124
Short name T898
Test name
Test status
Simulation time 354436789 ps
CPU time 0.82 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:55 PM PST 24
Peak memory 200636 kb
Host smart-2aaa9327-77d6-4d48-a7b5-c5625477df22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920874124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2920874124
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1371238500
Short name T801
Test name
Test status
Simulation time 452488348 ps
CPU time 1.66 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:57 PM PST 24
Peak memory 200772 kb
Host smart-0bfb4ede-3880-41e5-93e3-c4cc81c6bedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371238500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1371238500
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.191066942
Short name T797
Test name
Test status
Simulation time 431275467 ps
CPU time 1.58 seconds
Started Feb 21 12:28:44 PM PST 24
Finished Feb 21 12:28:47 PM PST 24
Peak memory 200788 kb
Host smart-07388b8e-7444-4f3e-946e-d6c73d2a8a36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191066942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.191066942
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2891979926
Short name T803
Test name
Test status
Simulation time 450828526 ps
CPU time 1.79 seconds
Started Feb 21 12:28:38 PM PST 24
Finished Feb 21 12:28:41 PM PST 24
Peak memory 200776 kb
Host smart-d18c9738-0615-4855-a36b-1eb83013c237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891979926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2891979926
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3748114036
Short name T802
Test name
Test status
Simulation time 315020550 ps
CPU time 1.36 seconds
Started Feb 21 12:28:42 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 200728 kb
Host smart-01fa6c24-12dd-4e03-8d75-cd2e7f6e4cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748114036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3748114036
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1218201516
Short name T821
Test name
Test status
Simulation time 314324746 ps
CPU time 0.77 seconds
Started Feb 21 12:28:42 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 200636 kb
Host smart-ab0d5636-78c8-4a6c-90f6-5e74fe130055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218201516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1218201516
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4215652855
Short name T826
Test name
Test status
Simulation time 489109168 ps
CPU time 1.06 seconds
Started Feb 21 12:28:24 PM PST 24
Finished Feb 21 12:28:26 PM PST 24
Peak memory 200924 kb
Host smart-b0d49168-f2d8-4b3e-807c-1216798df877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215652855 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.4215652855
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3850237008
Short name T813
Test name
Test status
Simulation time 533752417 ps
CPU time 2.14 seconds
Started Feb 21 12:28:26 PM PST 24
Finished Feb 21 12:28:29 PM PST 24
Peak memory 200808 kb
Host smart-5f5977e5-fb9a-4ca8-986c-fb8694caf524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850237008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3850237008
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2436464391
Short name T819
Test name
Test status
Simulation time 290630025 ps
CPU time 1.26 seconds
Started Feb 21 12:28:33 PM PST 24
Finished Feb 21 12:28:36 PM PST 24
Peak memory 200792 kb
Host smart-d16121d5-26fd-460f-828a-0cb6a0e5a5e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436464391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2436464391
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1485527761
Short name T28
Test name
Test status
Simulation time 4715606419 ps
CPU time 11.21 seconds
Started Feb 21 12:28:27 PM PST 24
Finished Feb 21 12:28:40 PM PST 24
Peak memory 201112 kb
Host smart-b5675ae6-ac5d-41c7-a2a8-111a6f7a35c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485527761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1485527761
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.353242953
Short name T903
Test name
Test status
Simulation time 457988070 ps
CPU time 1.88 seconds
Started Feb 21 12:28:35 PM PST 24
Finished Feb 21 12:28:37 PM PST 24
Peak memory 201120 kb
Host smart-de1ab553-7b79-482f-bf24-182ef5fdc357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353242953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.353242953
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.444693363
Short name T879
Test name
Test status
Simulation time 8728423166 ps
CPU time 21.1 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:29:03 PM PST 24
Peak memory 201012 kb
Host smart-4d0b6ea3-0287-4e4e-a14e-c93364184803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444693363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.444693363
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4093332436
Short name T851
Test name
Test status
Simulation time 422935447 ps
CPU time 0.91 seconds
Started Feb 21 12:28:24 PM PST 24
Finished Feb 21 12:28:26 PM PST 24
Peak memory 200872 kb
Host smart-b4b3000a-0eb1-4c5a-affd-cf4a52d11608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093332436 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.4093332436
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3572608159
Short name T878
Test name
Test status
Simulation time 460949412 ps
CPU time 1.78 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:31 PM PST 24
Peak memory 200796 kb
Host smart-a923c10f-a28f-4eec-933f-cb9917ae40cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572608159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3572608159
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2370694495
Short name T818
Test name
Test status
Simulation time 387350620 ps
CPU time 1.09 seconds
Started Feb 21 12:28:35 PM PST 24
Finished Feb 21 12:28:36 PM PST 24
Peak memory 200776 kb
Host smart-c6194269-e427-47b5-941c-be6276391600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370694495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2370694495
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2623046530
Short name T26
Test name
Test status
Simulation time 1853286335 ps
CPU time 1.78 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:31 PM PST 24
Peak memory 200796 kb
Host smart-2b660eef-72bd-483b-90da-f8f29e6c0b00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623046530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2623046530
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2105609953
Short name T130
Test name
Test status
Simulation time 593499792 ps
CPU time 2.01 seconds
Started Feb 21 12:28:27 PM PST 24
Finished Feb 21 12:28:30 PM PST 24
Peak memory 201032 kb
Host smart-e09e0349-5144-41de-8195-ad188d70e920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105609953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2105609953
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4284993654
Short name T862
Test name
Test status
Simulation time 8339260918 ps
CPU time 11.32 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:40 PM PST 24
Peak memory 201100 kb
Host smart-c32aac0a-19e0-4032-a8b7-67b36e005231
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284993654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4284993654
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3747621251
Short name T909
Test name
Test status
Simulation time 422775513 ps
CPU time 1.66 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:43 PM PST 24
Peak memory 200768 kb
Host smart-177c734f-4af6-4439-ae7e-74aebfc9270f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747621251 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3747621251
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2038473939
Short name T107
Test name
Test status
Simulation time 452362407 ps
CPU time 1.44 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:31 PM PST 24
Peak memory 200752 kb
Host smart-3d6ede3d-9575-480f-bd55-e16e483d7b0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038473939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2038473939
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4246469808
Short name T914
Test name
Test status
Simulation time 372482411 ps
CPU time 0.85 seconds
Started Feb 21 12:28:26 PM PST 24
Finished Feb 21 12:28:28 PM PST 24
Peak memory 200640 kb
Host smart-1e4e287f-acb5-419d-bb2b-f898402e54f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246469808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.4246469808
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3842503690
Short name T870
Test name
Test status
Simulation time 2304758739 ps
CPU time 3.65 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 200844 kb
Host smart-1a5a226d-d406-4a3e-a31b-72d52d5a3a48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842503690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3842503690
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2604531487
Short name T908
Test name
Test status
Simulation time 769930746 ps
CPU time 2.09 seconds
Started Feb 21 12:28:33 PM PST 24
Finished Feb 21 12:28:37 PM PST 24
Peak memory 201148 kb
Host smart-1500fea3-2c9e-48ee-bb7d-6e03c8989187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604531487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2604531487
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1886644864
Short name T367
Test name
Test status
Simulation time 7805000816 ps
CPU time 19.81 seconds
Started Feb 21 12:28:27 PM PST 24
Finished Feb 21 12:28:47 PM PST 24
Peak memory 201100 kb
Host smart-6065a86f-c47f-4b9a-aa10-1100eda55373
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886644864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1886644864
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.181014041
Short name T843
Test name
Test status
Simulation time 404984861 ps
CPU time 1.41 seconds
Started Feb 21 12:28:32 PM PST 24
Finished Feb 21 12:28:34 PM PST 24
Peak memory 200800 kb
Host smart-0e356977-5e28-4309-b5cf-0f7404134989
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181014041 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.181014041
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3434725460
Short name T114
Test name
Test status
Simulation time 413697047 ps
CPU time 0.93 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:43 PM PST 24
Peak memory 200708 kb
Host smart-1c6fa629-0550-4677-b7c7-fbc4a73de758
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434725460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3434725460
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.188718943
Short name T812
Test name
Test status
Simulation time 416272222 ps
CPU time 1.51 seconds
Started Feb 21 12:28:26 PM PST 24
Finished Feb 21 12:28:29 PM PST 24
Peak memory 200788 kb
Host smart-7c06664b-2268-46ac-9a7e-4b6e79205cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188718943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.188718943
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1744924572
Short name T881
Test name
Test status
Simulation time 5269982515 ps
CPU time 2.04 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:43 PM PST 24
Peak memory 201132 kb
Host smart-ba328de1-e9f2-4b35-a54a-930952902f8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744924572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1744924572
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2546630445
Short name T124
Test name
Test status
Simulation time 369112654 ps
CPU time 2.81 seconds
Started Feb 21 12:28:24 PM PST 24
Finished Feb 21 12:28:28 PM PST 24
Peak memory 201144 kb
Host smart-3e4003c2-b182-4ae8-8055-3a4b1c6a225d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546630445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2546630445
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.106595
Short name T902
Test name
Test status
Simulation time 3852566741 ps
CPU time 6.21 seconds
Started Feb 21 12:28:24 PM PST 24
Finished Feb 21 12:28:31 PM PST 24
Peak memory 201124 kb
Host smart-b1739076-a09c-4444-8600-433878bc3054
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_e
rr.106595
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3352120564
Short name T79
Test name
Test status
Simulation time 666831983 ps
CPU time 1.24 seconds
Started Feb 21 12:28:40 PM PST 24
Finished Feb 21 12:28:43 PM PST 24
Peak memory 209280 kb
Host smart-916f7975-1208-4862-b815-42809c355967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352120564 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3352120564
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2928856878
Short name T848
Test name
Test status
Simulation time 447045460 ps
CPU time 1.78 seconds
Started Feb 21 12:28:33 PM PST 24
Finished Feb 21 12:28:36 PM PST 24
Peak memory 200764 kb
Host smart-c6eb66f6-c669-474e-a554-5ab31e733b93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928856878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2928856878
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1546897411
Short name T830
Test name
Test status
Simulation time 297204932 ps
CPU time 1.03 seconds
Started Feb 21 12:28:30 PM PST 24
Finished Feb 21 12:28:32 PM PST 24
Peak memory 200800 kb
Host smart-f0dd51d2-d2c9-44f1-85f7-ab87cbcabe6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546897411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1546897411
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1572430335
Short name T857
Test name
Test status
Simulation time 1775958416 ps
CPU time 1.95 seconds
Started Feb 21 12:28:33 PM PST 24
Finished Feb 21 12:28:36 PM PST 24
Peak memory 200840 kb
Host smart-b15ad413-06fb-4ed0-ad02-ccdaf9848a9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572430335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1572430335
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3547299430
Short name T36
Test name
Test status
Simulation time 364584915 ps
CPU time 2.68 seconds
Started Feb 21 12:28:22 PM PST 24
Finished Feb 21 12:28:25 PM PST 24
Peak memory 201100 kb
Host smart-0edd9484-ffa5-4223-816c-5ca0190c30b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547299430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3547299430
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3491981798
Short name T855
Test name
Test status
Simulation time 8018315743 ps
CPU time 20.62 seconds
Started Feb 21 12:28:28 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 201100 kb
Host smart-cda08ebf-74c6-4ed2-a681-1f07854a4754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491981798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3491981798
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3964100447
Short name T427
Test name
Test status
Simulation time 440895110 ps
CPU time 0.84 seconds
Started Feb 21 12:47:10 PM PST 24
Finished Feb 21 12:47:11 PM PST 24
Peak memory 201252 kb
Host smart-545af486-ed11-4adb-832e-c42627a40008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964100447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3964100447
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.383596764
Short name T546
Test name
Test status
Simulation time 499561037734 ps
CPU time 624.39 seconds
Started Feb 21 12:47:09 PM PST 24
Finished Feb 21 12:57:34 PM PST 24
Peak memory 201440 kb
Host smart-ab602e6d-9c2c-4a19-a1e3-5e3586b9e847
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=383596764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.383596764
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2454597642
Short name T72
Test name
Test status
Simulation time 488201946149 ps
CPU time 271.69 seconds
Started Feb 21 12:47:01 PM PST 24
Finished Feb 21 12:51:34 PM PST 24
Peak memory 201812 kb
Host smart-ffc4f1b2-bcb6-4709-a3d6-05c99901ffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454597642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2454597642
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1586938719
Short name T569
Test name
Test status
Simulation time 331745449278 ps
CPU time 185.07 seconds
Started Feb 21 12:47:06 PM PST 24
Finished Feb 21 12:50:11 PM PST 24
Peak memory 201412 kb
Host smart-52fa786a-2abf-4a57-bb5b-9cca6607e978
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586938719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1586938719
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1136881440
Short name T325
Test name
Test status
Simulation time 509921977970 ps
CPU time 1110.74 seconds
Started Feb 21 12:47:06 PM PST 24
Finished Feb 21 01:05:37 PM PST 24
Peak memory 201412 kb
Host smart-1c400073-26aa-45b6-99dc-64c0d2024ede
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136881440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1136881440
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.573963413
Short name T609
Test name
Test status
Simulation time 330376986537 ps
CPU time 220.5 seconds
Started Feb 21 12:47:03 PM PST 24
Finished Feb 21 12:50:44 PM PST 24
Peak memory 201508 kb
Host smart-4a9a2535-a59f-4d14-a057-c84bd1ac0728
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573963413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.573963413
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3908185857
Short name T624
Test name
Test status
Simulation time 22322671752 ps
CPU time 6.71 seconds
Started Feb 21 12:47:16 PM PST 24
Finished Feb 21 12:47:23 PM PST 24
Peak memory 201216 kb
Host smart-c4d3e9ba-06b2-42b5-a55a-597ce77430a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908185857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3908185857
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1473757296
Short name T638
Test name
Test status
Simulation time 4448605342 ps
CPU time 2.68 seconds
Started Feb 21 12:47:12 PM PST 24
Finished Feb 21 12:47:15 PM PST 24
Peak memory 201296 kb
Host smart-a7b3b87c-abc5-4493-a245-49571673b964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473757296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1473757296
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1866312496
Short name T47
Test name
Test status
Simulation time 3918918163 ps
CPU time 4.14 seconds
Started Feb 21 12:47:00 PM PST 24
Finished Feb 21 12:47:05 PM PST 24
Peak memory 216460 kb
Host smart-aed2cf67-c73c-41e9-bccd-c60019178481
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866312496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1866312496
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3712016573
Short name T467
Test name
Test status
Simulation time 5627591309 ps
CPU time 11.99 seconds
Started Feb 21 12:47:02 PM PST 24
Finished Feb 21 12:47:14 PM PST 24
Peak memory 201292 kb
Host smart-e08c9577-8539-4944-be1b-6b1b33dd55e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712016573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3712016573
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2315629296
Short name T293
Test name
Test status
Simulation time 168986759067 ps
CPU time 348.22 seconds
Started Feb 21 12:47:04 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 201504 kb
Host smart-9fc2b8f4-63c8-4973-b5d8-e8f6dd311c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315629296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2315629296
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2633093191
Short name T424
Test name
Test status
Simulation time 468991598 ps
CPU time 0.87 seconds
Started Feb 21 12:47:11 PM PST 24
Finished Feb 21 12:47:13 PM PST 24
Peak memory 201164 kb
Host smart-5fecefc9-3e13-44eb-889c-ec668aced31b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633093191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2633093191
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.27810116
Short name T363
Test name
Test status
Simulation time 330872365275 ps
CPU time 380.84 seconds
Started Feb 21 12:47:01 PM PST 24
Finished Feb 21 12:53:23 PM PST 24
Peak memory 201476 kb
Host smart-e51fd87f-6eb4-4036-865e-ef32cd37b5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27810116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.27810116
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3227436440
Short name T445
Test name
Test status
Simulation time 165995619439 ps
CPU time 366.04 seconds
Started Feb 21 12:47:01 PM PST 24
Finished Feb 21 12:53:08 PM PST 24
Peak memory 201724 kb
Host smart-f0a5acd2-d8ed-4382-948a-2655c391e362
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227436440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3227436440
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3346420724
Short name T245
Test name
Test status
Simulation time 164079861002 ps
CPU time 365.01 seconds
Started Feb 21 12:47:07 PM PST 24
Finished Feb 21 12:53:13 PM PST 24
Peak memory 201444 kb
Host smart-0d8e75c3-f114-40b5-b216-fd07b2ff92e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346420724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3346420724
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2192229865
Short name T687
Test name
Test status
Simulation time 489024868825 ps
CPU time 103.45 seconds
Started Feb 21 12:47:04 PM PST 24
Finished Feb 21 12:48:48 PM PST 24
Peak memory 201480 kb
Host smart-62333e11-b01b-4112-b4a6-ca77de76f898
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192229865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2192229865
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2458266776
Short name T285
Test name
Test status
Simulation time 161764542107 ps
CPU time 178.42 seconds
Started Feb 21 12:47:06 PM PST 24
Finished Feb 21 12:50:05 PM PST 24
Peak memory 201484 kb
Host smart-62a4fa50-7b5f-4bb7-8319-38175eca1153
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458266776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2458266776
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.866850770
Short name T505
Test name
Test status
Simulation time 499850069873 ps
CPU time 1147.93 seconds
Started Feb 21 12:47:05 PM PST 24
Finished Feb 21 01:06:13 PM PST 24
Peak memory 201484 kb
Host smart-18d4ecb3-0738-4f07-9ecd-2283202732ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866850770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.866850770
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3476694060
Short name T704
Test name
Test status
Simulation time 44264914801 ps
CPU time 51.09 seconds
Started Feb 21 12:47:02 PM PST 24
Finished Feb 21 12:47:54 PM PST 24
Peak memory 201304 kb
Host smart-3373ae60-c62e-43da-a7bc-598cdc44f4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476694060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3476694060
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1078034773
Short name T234
Test name
Test status
Simulation time 5703737149 ps
CPU time 1.84 seconds
Started Feb 21 12:47:06 PM PST 24
Finished Feb 21 12:47:08 PM PST 24
Peak memory 201292 kb
Host smart-622a7e75-f617-440d-9e3a-ef9ade7523b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078034773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1078034773
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2518392608
Short name T49
Test name
Test status
Simulation time 4323900519 ps
CPU time 10.99 seconds
Started Feb 21 12:47:10 PM PST 24
Finished Feb 21 12:47:26 PM PST 24
Peak memory 216448 kb
Host smart-fcf859f8-94a5-4e4e-965e-67d277116ed7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518392608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2518392608
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.4116388359
Short name T543
Test name
Test status
Simulation time 5975827314 ps
CPU time 14.47 seconds
Started Feb 21 12:47:02 PM PST 24
Finished Feb 21 12:47:17 PM PST 24
Peak memory 201268 kb
Host smart-64d07035-7572-4466-a0df-10a38648c8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116388359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.4116388359
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2030017291
Short name T303
Test name
Test status
Simulation time 487737558816 ps
CPU time 312.13 seconds
Started Feb 21 12:47:03 PM PST 24
Finished Feb 21 12:52:16 PM PST 24
Peak memory 201440 kb
Host smart-4bbf7801-d107-40d3-bb79-59d2553ec9bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030017291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2030017291
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.520824327
Short name T639
Test name
Test status
Simulation time 17664531037 ps
CPU time 68.9 seconds
Started Feb 21 12:47:09 PM PST 24
Finished Feb 21 12:48:19 PM PST 24
Peak memory 210032 kb
Host smart-9be4d9c0-ed4f-495e-90dc-eac28c92b0d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520824327 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.520824327
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.591564348
Short name T149
Test name
Test status
Simulation time 331673167730 ps
CPU time 361.3 seconds
Started Feb 21 12:47:34 PM PST 24
Finished Feb 21 12:53:37 PM PST 24
Peak memory 201524 kb
Host smart-0a8a20d4-8724-44c6-976a-7fde806b671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591564348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.591564348
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3327224793
Short name T133
Test name
Test status
Simulation time 498611106907 ps
CPU time 520.59 seconds
Started Feb 21 12:47:23 PM PST 24
Finished Feb 21 12:56:05 PM PST 24
Peak memory 201584 kb
Host smart-13912ab2-e866-4321-aa4f-4246cccef581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327224793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3327224793
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2777138066
Short name T535
Test name
Test status
Simulation time 163045665655 ps
CPU time 107.24 seconds
Started Feb 21 12:47:29 PM PST 24
Finished Feb 21 12:49:17 PM PST 24
Peak memory 201420 kb
Host smart-c37d6b38-819e-4197-b804-124d7e2c79ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777138066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2777138066
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1378934820
Short name T180
Test name
Test status
Simulation time 165558307619 ps
CPU time 405.68 seconds
Started Feb 21 12:47:26 PM PST 24
Finished Feb 21 12:54:13 PM PST 24
Peak memory 201540 kb
Host smart-debbc361-9c9b-4a9e-897f-0a283879a4a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378934820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1378934820
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4003851896
Short name T270
Test name
Test status
Simulation time 166920218275 ps
CPU time 84.31 seconds
Started Feb 21 12:47:29 PM PST 24
Finished Feb 21 12:48:54 PM PST 24
Peak memory 201596 kb
Host smart-96c2c0c6-b63c-4513-91cc-eed9c355f391
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003851896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4003851896
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.4067137285
Short name T137
Test name
Test status
Simulation time 167851343042 ps
CPU time 60.27 seconds
Started Feb 21 12:47:25 PM PST 24
Finished Feb 21 12:48:27 PM PST 24
Peak memory 201480 kb
Host smart-bf2f366c-ea70-4e6d-90cd-e6ee85d0d5b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067137285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.4067137285
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1741702476
Short name T400
Test name
Test status
Simulation time 88809051167 ps
CPU time 444.54 seconds
Started Feb 21 12:47:26 PM PST 24
Finished Feb 21 12:54:52 PM PST 24
Peak memory 201820 kb
Host smart-110063ed-0861-4b82-8a9d-ceffd1d847c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741702476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1741702476
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3964367019
Short name T692
Test name
Test status
Simulation time 43418057421 ps
CPU time 50.84 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:48:24 PM PST 24
Peak memory 201280 kb
Host smart-5d76f3c4-33bf-4ab3-9f15-99949b202c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964367019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3964367019
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3660210727
Short name T68
Test name
Test status
Simulation time 4820314312 ps
CPU time 12.78 seconds
Started Feb 21 12:47:28 PM PST 24
Finished Feb 21 12:47:41 PM PST 24
Peak memory 201256 kb
Host smart-f4acc250-4eb0-45dc-9271-6987d024c26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660210727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3660210727
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2362621971
Short name T781
Test name
Test status
Simulation time 5519945655 ps
CPU time 8.94 seconds
Started Feb 21 12:47:21 PM PST 24
Finished Feb 21 12:47:30 PM PST 24
Peak memory 201324 kb
Host smart-33ebe88b-e336-4798-9e05-4583227146e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362621971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2362621971
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3820242718
Short name T340
Test name
Test status
Simulation time 208709717708 ps
CPU time 64.06 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:48:38 PM PST 24
Peak memory 201496 kb
Host smart-339d7c70-9f3e-4f25-b5a8-41f62c8e4f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820242718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3820242718
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.206386233
Short name T242
Test name
Test status
Simulation time 70120340110 ps
CPU time 172.63 seconds
Started Feb 21 12:47:30 PM PST 24
Finished Feb 21 12:50:23 PM PST 24
Peak memory 217504 kb
Host smart-51eb3fe8-6e84-41af-b746-6ceda92d6fcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206386233 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.206386233
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1820255204
Short name T753
Test name
Test status
Simulation time 332192337 ps
CPU time 0.85 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:47:34 PM PST 24
Peak memory 201152 kb
Host smart-b4b8a7e2-7db5-45ef-8618-cae9391ed3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820255204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1820255204
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2920939584
Short name T271
Test name
Test status
Simulation time 325109365155 ps
CPU time 471.33 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:55:29 PM PST 24
Peak memory 201500 kb
Host smart-d8438906-cf17-4d50-b728-445e9fb981ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920939584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2920939584
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2775008965
Short name T329
Test name
Test status
Simulation time 168183370804 ps
CPU time 99.35 seconds
Started Feb 21 12:47:36 PM PST 24
Finished Feb 21 12:49:16 PM PST 24
Peak memory 201548 kb
Host smart-aacfd81a-0001-4865-9a17-003b6a3f4fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775008965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2775008965
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1348860653
Short name T484
Test name
Test status
Simulation time 488689886475 ps
CPU time 538.74 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:56:32 PM PST 24
Peak memory 201528 kb
Host smart-fd09b5ac-dc35-47bd-8133-83a7e496fdc9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348860653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1348860653
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2571332950
Short name T64
Test name
Test status
Simulation time 324956225074 ps
CPU time 200.78 seconds
Started Feb 21 12:47:27 PM PST 24
Finished Feb 21 12:50:48 PM PST 24
Peak memory 201436 kb
Host smart-96f9496e-2dfe-4c5b-8daa-105f40f0175d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571332950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2571332950
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.607433877
Short name T209
Test name
Test status
Simulation time 165554546849 ps
CPU time 84.95 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:48:58 PM PST 24
Peak memory 201492 kb
Host smart-a25c9f14-7833-421d-92f6-14b6538e2227
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=607433877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.607433877
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3146515737
Short name T16
Test name
Test status
Simulation time 168862940008 ps
CPU time 24.97 seconds
Started Feb 21 12:47:41 PM PST 24
Finished Feb 21 12:48:06 PM PST 24
Peak memory 201572 kb
Host smart-02c2010e-9ebe-46d5-802e-13f1852c479e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146515737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3146515737
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.191981121
Short name T496
Test name
Test status
Simulation time 167629755367 ps
CPU time 58.29 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:48:50 PM PST 24
Peak memory 201480 kb
Host smart-965722e9-c9c3-461b-9eea-cede13c84d94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191981121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.191981121
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2456802661
Short name T69
Test name
Test status
Simulation time 93862853089 ps
CPU time 472.39 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:55:26 PM PST 24
Peak memory 201796 kb
Host smart-b7a1ce89-1e9f-4f2c-a309-41517e74d833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456802661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2456802661
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.4283629956
Short name T403
Test name
Test status
Simulation time 40798604376 ps
CPU time 46.69 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:48:24 PM PST 24
Peak memory 201292 kb
Host smart-d8eb9a1e-f8df-4237-bee4-7258d8767e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283629956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.4283629956
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2984880869
Short name T593
Test name
Test status
Simulation time 4197724415 ps
CPU time 10.63 seconds
Started Feb 21 12:47:45 PM PST 24
Finished Feb 21 12:47:57 PM PST 24
Peak memory 201244 kb
Host smart-b2c65eaf-31bc-4dfd-b559-e4240ac473d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984880869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2984880869
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3961972983
Short name T487
Test name
Test status
Simulation time 5855469484 ps
CPU time 4.2 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:47:38 PM PST 24
Peak memory 201256 kb
Host smart-be795c5f-832f-4a7a-842a-1f120adc5cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961972983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3961972983
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3651548260
Short name T619
Test name
Test status
Simulation time 750885562096 ps
CPU time 676.75 seconds
Started Feb 21 12:47:41 PM PST 24
Finished Feb 21 12:58:59 PM PST 24
Peak memory 201720 kb
Host smart-1d29c88b-f275-452b-a865-b6e988a21743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651548260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3651548260
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1439282256
Short name T39
Test name
Test status
Simulation time 356405288522 ps
CPU time 292.85 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:52:26 PM PST 24
Peak memory 210224 kb
Host smart-73679939-d5d3-4ce2-b7c8-95eb81cdadd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439282256 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1439282256
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1997923512
Short name T460
Test name
Test status
Simulation time 355162117 ps
CPU time 1.34 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:47:39 PM PST 24
Peak memory 201220 kb
Host smart-ee41b9a3-4770-41c7-9dda-977742a6810d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997923512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1997923512
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2292874390
Short name T357
Test name
Test status
Simulation time 500329418137 ps
CPU time 168.25 seconds
Started Feb 21 12:47:39 PM PST 24
Finished Feb 21 12:50:28 PM PST 24
Peak memory 201604 kb
Host smart-00f10ac8-d858-4775-a72b-c9a5e95d32d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292874390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2292874390
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1592348711
Short name T649
Test name
Test status
Simulation time 327128712238 ps
CPU time 494 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:56:01 PM PST 24
Peak memory 201524 kb
Host smart-4b9884ff-509b-4f83-bd0b-470bd09bdef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592348711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1592348711
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4012441331
Short name T752
Test name
Test status
Simulation time 158619031662 ps
CPU time 171.19 seconds
Started Feb 21 12:47:30 PM PST 24
Finished Feb 21 12:50:22 PM PST 24
Peak memory 201532 kb
Host smart-ed1cbfc1-d3c5-4565-9ce1-1e6baf5c2104
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012441331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.4012441331
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2665115272
Short name T534
Test name
Test status
Simulation time 493311555497 ps
CPU time 1075.82 seconds
Started Feb 21 12:47:36 PM PST 24
Finished Feb 21 01:05:33 PM PST 24
Peak memory 201472 kb
Host smart-000c5910-d20c-4850-8e25-3245f76a1cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665115272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2665115272
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.4141877101
Short name T211
Test name
Test status
Simulation time 338359960352 ps
CPU time 202.1 seconds
Started Feb 21 12:47:43 PM PST 24
Finished Feb 21 12:51:06 PM PST 24
Peak memory 201376 kb
Host smart-8e5cc25e-947d-447d-9d3a-2b70856ed3bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141877101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.4141877101
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1442463841
Short name T703
Test name
Test status
Simulation time 490162582224 ps
CPU time 1095.37 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 01:05:48 PM PST 24
Peak memory 201544 kb
Host smart-322c554c-ed5a-45ec-888a-c667b4fa0dc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442463841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1442463841
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1595805060
Short name T138
Test name
Test status
Simulation time 329741272836 ps
CPU time 166.62 seconds
Started Feb 21 12:47:31 PM PST 24
Finished Feb 21 12:50:19 PM PST 24
Peak memory 201560 kb
Host smart-1319e0e8-77e0-4ab7-89d1-10e524067b68
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595805060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1595805060
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2264515921
Short name T368
Test name
Test status
Simulation time 102994889173 ps
CPU time 510.33 seconds
Started Feb 21 12:47:34 PM PST 24
Finished Feb 21 12:56:06 PM PST 24
Peak memory 201880 kb
Host smart-09eac79a-01b4-430d-a586-17cfd26eec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264515921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2264515921
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2261030194
Short name T549
Test name
Test status
Simulation time 36019446777 ps
CPU time 40.58 seconds
Started Feb 21 12:47:33 PM PST 24
Finished Feb 21 12:48:15 PM PST 24
Peak memory 201300 kb
Host smart-e9421d40-5787-4861-81d1-e32251d84c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261030194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2261030194
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1304447341
Short name T737
Test name
Test status
Simulation time 3625571788 ps
CPU time 2.77 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:47:35 PM PST 24
Peak memory 201312 kb
Host smart-71d459ae-e8bf-4460-9e32-8143c7e1a0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304447341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1304447341
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3519384255
Short name T442
Test name
Test status
Simulation time 5718167616 ps
CPU time 7.16 seconds
Started Feb 21 12:47:31 PM PST 24
Finished Feb 21 12:47:39 PM PST 24
Peak memory 201316 kb
Host smart-596d41f9-5995-44d0-9da4-504c5a3731da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519384255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3519384255
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2370367058
Short name T323
Test name
Test status
Simulation time 215522678012 ps
CPU time 117.79 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:49:31 PM PST 24
Peak memory 211008 kb
Host smart-3f7ef344-5f94-48d5-bb58-452b559b289f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370367058 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2370367058
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2186773270
Short name T715
Test name
Test status
Simulation time 458178448 ps
CPU time 0.88 seconds
Started Feb 21 12:47:39 PM PST 24
Finished Feb 21 12:47:40 PM PST 24
Peak memory 201220 kb
Host smart-a5a9abbc-048d-447e-9de5-9055b066cb4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186773270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2186773270
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2454170508
Short name T286
Test name
Test status
Simulation time 486808524062 ps
CPU time 683.13 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:59:00 PM PST 24
Peak memory 201404 kb
Host smart-97b9659b-96a2-448e-b047-570e4fa7d2f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454170508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2454170508
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.480519797
Short name T65
Test name
Test status
Simulation time 166463711248 ps
CPU time 356.17 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 201464 kb
Host smart-f2d393b4-1b0a-4e02-93fc-de2c79652127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480519797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.480519797
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2033486043
Short name T502
Test name
Test status
Simulation time 328339356671 ps
CPU time 181.48 seconds
Started Feb 21 12:47:35 PM PST 24
Finished Feb 21 12:50:37 PM PST 24
Peak memory 201564 kb
Host smart-3f2848a4-f8a2-429b-b918-ab3ee3baecdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033486043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2033486043
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1654083488
Short name T144
Test name
Test status
Simulation time 161936040857 ps
CPU time 356.13 seconds
Started Feb 21 12:47:36 PM PST 24
Finished Feb 21 12:53:32 PM PST 24
Peak memory 201504 kb
Host smart-485188ae-bbad-4fbe-85c2-c64e7644d4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654083488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1654083488
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.948683836
Short name T462
Test name
Test status
Simulation time 161436473878 ps
CPU time 98.85 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:49:16 PM PST 24
Peak memory 201488 kb
Host smart-d2775d64-b129-4c57-9daa-eca4b48732cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=948683836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.948683836
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2003259856
Short name T157
Test name
Test status
Simulation time 493021813077 ps
CPU time 527.59 seconds
Started Feb 21 12:47:34 PM PST 24
Finished Feb 21 12:56:22 PM PST 24
Peak memory 201428 kb
Host smart-82decebf-fdfb-4019-b03b-3560f4e7bbe7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003259856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2003259856
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2317271434
Short name T775
Test name
Test status
Simulation time 168977832422 ps
CPU time 29.49 seconds
Started Feb 21 12:47:24 PM PST 24
Finished Feb 21 12:47:54 PM PST 24
Peak memory 201572 kb
Host smart-3d15d9cc-3b14-40a0-b240-0f8f0a020214
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317271434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2317271434
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2837468101
Short name T380
Test name
Test status
Simulation time 68957607472 ps
CPU time 229.24 seconds
Started Feb 21 12:47:40 PM PST 24
Finished Feb 21 12:51:30 PM PST 24
Peak memory 201788 kb
Host smart-87e4f20c-d668-41a0-adf8-93eee938f40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837468101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2837468101
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3433133404
Short name T500
Test name
Test status
Simulation time 39993467348 ps
CPU time 12.07 seconds
Started Feb 21 12:47:31 PM PST 24
Finished Feb 21 12:47:45 PM PST 24
Peak memory 201280 kb
Host smart-01ab1fa0-e946-45bc-bf2c-de2a622153e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433133404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3433133404
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4176751008
Short name T725
Test name
Test status
Simulation time 4383382586 ps
CPU time 3.17 seconds
Started Feb 21 12:47:35 PM PST 24
Finished Feb 21 12:47:39 PM PST 24
Peak memory 201324 kb
Host smart-64e8266b-5a9f-46b0-982e-99ddbc69401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176751008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4176751008
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3060550727
Short name T602
Test name
Test status
Simulation time 6141779032 ps
CPU time 2.49 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:47:35 PM PST 24
Peak memory 201260 kb
Host smart-9cedb4c5-532d-4233-a650-60c90154808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060550727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3060550727
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1150223447
Short name T751
Test name
Test status
Simulation time 268069271833 ps
CPU time 60.06 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:48:37 PM PST 24
Peak memory 201624 kb
Host smart-32be766c-451f-40ef-b8c7-4553d5df395f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150223447 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1150223447
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4274574546
Short name T673
Test name
Test status
Simulation time 462586162 ps
CPU time 0.88 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:47:53 PM PST 24
Peak memory 201232 kb
Host smart-5d68b4f2-a1ee-49a3-86bf-255fbed5a4e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274574546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4274574546
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.80368645
Short name T786
Test name
Test status
Simulation time 166006926134 ps
CPU time 7.46 seconds
Started Feb 21 12:47:45 PM PST 24
Finished Feb 21 12:47:58 PM PST 24
Peak memory 201436 kb
Host smart-01ff3f68-0b7b-46e7-a908-3bbd496db7c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80368645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gatin
g.80368645
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1214631836
Short name T263
Test name
Test status
Simulation time 493912206766 ps
CPU time 236.85 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:51:49 PM PST 24
Peak memory 201552 kb
Host smart-6019cecf-6978-403d-b74f-875b43689170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214631836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1214631836
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.439417315
Short name T251
Test name
Test status
Simulation time 333352254649 ps
CPU time 699.1 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:59:16 PM PST 24
Peak memory 201560 kb
Host smart-b6da1769-2572-4936-80f9-f85d0db4bbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439417315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.439417315
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2182624245
Short name T600
Test name
Test status
Simulation time 162778564101 ps
CPU time 33.56 seconds
Started Feb 21 12:47:38 PM PST 24
Finished Feb 21 12:48:12 PM PST 24
Peak memory 201724 kb
Host smart-822658d2-0d58-43d8-b7d7-8c7ad511c23f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182624245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2182624245
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3240947719
Short name T217
Test name
Test status
Simulation time 487762541804 ps
CPU time 273.07 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:52:10 PM PST 24
Peak memory 201500 kb
Host smart-f39d9797-32ba-4b4c-839d-95faf8b6c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240947719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3240947719
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2345515454
Short name T699
Test name
Test status
Simulation time 328436446885 ps
CPU time 705.87 seconds
Started Feb 21 12:47:45 PM PST 24
Finished Feb 21 12:59:31 PM PST 24
Peak memory 201424 kb
Host smart-0f2e8294-6ae7-4907-9b5a-47fc7d44f084
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345515454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2345515454
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2860015912
Short name T268
Test name
Test status
Simulation time 323518634864 ps
CPU time 209.64 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:51:04 PM PST 24
Peak memory 201592 kb
Host smart-00b8b171-efa4-4a42-9b94-d6f732eaf9dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860015912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2860015912
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2001884056
Short name T650
Test name
Test status
Simulation time 324201678558 ps
CPU time 183.34 seconds
Started Feb 21 12:47:40 PM PST 24
Finished Feb 21 12:50:45 PM PST 24
Peak memory 201496 kb
Host smart-284c9810-e48f-4178-ab7e-ead9c615dc67
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001884056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2001884056
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.337974100
Short name T23
Test name
Test status
Simulation time 85946520646 ps
CPU time 339.19 seconds
Started Feb 21 12:47:30 PM PST 24
Finished Feb 21 12:53:13 PM PST 24
Peak memory 201792 kb
Host smart-521c23b8-9337-4934-b7f6-19bfa4cbb49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337974100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.337974100
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3319422806
Short name T586
Test name
Test status
Simulation time 24995986349 ps
CPU time 56.8 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:48:49 PM PST 24
Peak memory 201288 kb
Host smart-f3e8898e-1fd3-4e12-b489-3b0a4cace563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319422806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3319422806
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1299440740
Short name T660
Test name
Test status
Simulation time 5189889958 ps
CPU time 2.44 seconds
Started Feb 21 12:47:36 PM PST 24
Finished Feb 21 12:47:40 PM PST 24
Peak memory 201324 kb
Host smart-414bf8b6-4c55-42d7-b608-d6ef07814a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299440740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1299440740
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.960177122
Short name T610
Test name
Test status
Simulation time 5660891446 ps
CPU time 3.82 seconds
Started Feb 21 12:47:45 PM PST 24
Finished Feb 21 12:47:50 PM PST 24
Peak memory 201192 kb
Host smart-316caec0-a85a-48a0-b868-e8ce850f3960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960177122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.960177122
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.4105038063
Short name T579
Test name
Test status
Simulation time 410033714 ps
CPU time 1.44 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:47:48 PM PST 24
Peak memory 201236 kb
Host smart-3e09cb5b-f426-477f-b0f8-0ccd2222d10d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105038063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.4105038063
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3048485116
Short name T343
Test name
Test status
Simulation time 165768952492 ps
CPU time 84.71 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:49:11 PM PST 24
Peak memory 201812 kb
Host smart-45b0dccc-bbd8-4405-92f5-7e22c35dbbb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048485116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3048485116
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.823228906
Short name T250
Test name
Test status
Simulation time 330372006199 ps
CPU time 722.23 seconds
Started Feb 21 12:47:35 PM PST 24
Finished Feb 21 12:59:38 PM PST 24
Peak memory 201520 kb
Host smart-c53746f1-cdf8-4670-811b-39dec15d41fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823228906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.823228906
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2043514979
Short name T556
Test name
Test status
Simulation time 497438148385 ps
CPU time 1062.53 seconds
Started Feb 21 12:47:51 PM PST 24
Finished Feb 21 01:05:34 PM PST 24
Peak memory 201564 kb
Host smart-327274f3-873a-49a1-8cbf-97f7afd21c4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043514979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2043514979
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2197021830
Short name T598
Test name
Test status
Simulation time 327711396257 ps
CPU time 756.37 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 01:00:29 PM PST 24
Peak memory 201500 kb
Host smart-b61f1e36-7123-45ef-bca5-56cc62b66246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197021830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2197021830
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2436428764
Short name T764
Test name
Test status
Simulation time 161757121247 ps
CPU time 368.17 seconds
Started Feb 21 12:47:41 PM PST 24
Finished Feb 21 12:53:50 PM PST 24
Peak memory 201464 kb
Host smart-89723815-fa68-4180-bedd-dcca74ccc648
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436428764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2436428764
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1086579310
Short name T709
Test name
Test status
Simulation time 164865479745 ps
CPU time 64.51 seconds
Started Feb 21 12:47:42 PM PST 24
Finished Feb 21 12:48:47 PM PST 24
Peak memory 201476 kb
Host smart-9b6ff7bd-4004-4224-9051-e5d994722fee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086579310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1086579310
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1784784022
Short name T383
Test name
Test status
Simulation time 99515733057 ps
CPU time 551.88 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:57:05 PM PST 24
Peak memory 201824 kb
Host smart-e48d5b55-d828-4f55-ad05-8d6d311bc559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784784022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1784784022
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.344929527
Short name T179
Test name
Test status
Simulation time 22063953282 ps
CPU time 52.05 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:48:39 PM PST 24
Peak memory 201292 kb
Host smart-dc747d87-8646-47c2-a5d6-9874b34c1d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344929527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.344929527
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1214530562
Short name T95
Test name
Test status
Simulation time 4310171383 ps
CPU time 9.38 seconds
Started Feb 21 12:47:47 PM PST 24
Finished Feb 21 12:47:57 PM PST 24
Peak memory 201304 kb
Host smart-c2002efd-f413-448b-be6b-dd3f78c62c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214530562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1214530562
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1881209756
Short name T423
Test name
Test status
Simulation time 5952594574 ps
CPU time 16.39 seconds
Started Feb 21 12:47:40 PM PST 24
Finished Feb 21 12:47:57 PM PST 24
Peak memory 201204 kb
Host smart-bb7a731a-7631-4eab-8793-4ff303710284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881209756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1881209756
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1434114348
Short name T249
Test name
Test status
Simulation time 352575539766 ps
CPU time 763.95 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 01:00:30 PM PST 24
Peak memory 201496 kb
Host smart-21f108cc-f125-4ed1-ba8a-24a5bec65a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434114348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1434114348
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3929512328
Short name T98
Test name
Test status
Simulation time 75771856307 ps
CPU time 325.17 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:53:18 PM PST 24
Peak memory 210088 kb
Host smart-3008dfb9-ca8b-4ecc-9e83-482b8ea05097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929512328 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3929512328
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3126118436
Short name T451
Test name
Test status
Simulation time 393083626 ps
CPU time 1.1 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:47:48 PM PST 24
Peak memory 201496 kb
Host smart-7ae18e38-20a0-45b1-802a-a1f443c12a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126118436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3126118436
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1132930467
Short name T274
Test name
Test status
Simulation time 494313399014 ps
CPU time 255.25 seconds
Started Feb 21 12:47:45 PM PST 24
Finished Feb 21 12:52:01 PM PST 24
Peak memory 201752 kb
Host smart-fee9c2c0-306d-4143-837f-052eada059b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132930467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1132930467
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1401720899
Short name T175
Test name
Test status
Simulation time 500870822808 ps
CPU time 597.32 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:57:44 PM PST 24
Peak memory 201544 kb
Host smart-3d3f43cf-3cd0-44b6-b4a7-3dc2b0a4f1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401720899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1401720899
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3123103012
Short name T328
Test name
Test status
Simulation time 340586391104 ps
CPU time 781.59 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 01:00:50 PM PST 24
Peak memory 201504 kb
Host smart-476dc4ce-8014-499c-8f01-6adf43d33db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123103012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3123103012
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.66152408
Short name T495
Test name
Test status
Simulation time 155005379486 ps
CPU time 43.63 seconds
Started Feb 21 12:47:38 PM PST 24
Finished Feb 21 12:48:22 PM PST 24
Peak memory 201548 kb
Host smart-a8c0d6a2-44eb-4b0f-a638-0abbebc778e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=66152408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt
_fixed.66152408
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.4114402243
Short name T176
Test name
Test status
Simulation time 493114258403 ps
CPU time 65.55 seconds
Started Feb 21 12:47:39 PM PST 24
Finished Feb 21 12:48:46 PM PST 24
Peak memory 201604 kb
Host smart-bb09d699-1407-46e3-9366-901acd142af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114402243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4114402243
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2341865207
Short name T533
Test name
Test status
Simulation time 489969980969 ps
CPU time 1021.63 seconds
Started Feb 21 12:47:44 PM PST 24
Finished Feb 21 01:04:46 PM PST 24
Peak memory 201748 kb
Host smart-5309e176-ae7b-4cc9-920e-931bf75b3218
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341865207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2341865207
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2259078853
Short name T219
Test name
Test status
Simulation time 171597165955 ps
CPU time 392.44 seconds
Started Feb 21 12:47:47 PM PST 24
Finished Feb 21 12:54:21 PM PST 24
Peak memory 201548 kb
Host smart-2ca8b9b8-e0a1-44d5-879b-844d7c9f98a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259078853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2259078853
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.773313134
Short name T514
Test name
Test status
Simulation time 493985789364 ps
CPU time 287.54 seconds
Started Feb 21 12:47:42 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 201492 kb
Host smart-c661c039-3b19-42cf-840a-950a25efde80
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773313134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.773313134
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2147528324
Short name T22
Test name
Test status
Simulation time 128203849946 ps
CPU time 414.76 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 201888 kb
Host smart-ef0bc34c-ac5b-42a1-8758-12d5b465c649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147528324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2147528324
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2609801914
Short name T736
Test name
Test status
Simulation time 28064042097 ps
CPU time 63.62 seconds
Started Feb 21 12:47:47 PM PST 24
Finished Feb 21 12:48:52 PM PST 24
Peak memory 201292 kb
Host smart-613a1b42-08ba-422d-8661-c473b3d42488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609801914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2609801914
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3622656
Short name T568
Test name
Test status
Simulation time 3731289259 ps
CPU time 4.75 seconds
Started Feb 21 12:47:42 PM PST 24
Finished Feb 21 12:47:47 PM PST 24
Peak memory 201208 kb
Host smart-22adbb04-f785-4630-bf8f-3d447d2349e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3622656
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3857553188
Short name T425
Test name
Test status
Simulation time 5755343303 ps
CPU time 3.74 seconds
Started Feb 21 12:47:45 PM PST 24
Finished Feb 21 12:47:49 PM PST 24
Peak memory 201552 kb
Host smart-7033af0d-0243-4845-8e9d-8464bbd8a18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857553188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3857553188
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2975850604
Short name T239
Test name
Test status
Simulation time 62085773741 ps
CPU time 80.06 seconds
Started Feb 21 12:47:41 PM PST 24
Finished Feb 21 12:49:02 PM PST 24
Peak memory 211976 kb
Host smart-a9e7e54c-9734-4f20-965b-1e9faf028539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975850604 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2975850604
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2781067793
Short name T564
Test name
Test status
Simulation time 487584917 ps
CPU time 0.7 seconds
Started Feb 21 12:47:42 PM PST 24
Finished Feb 21 12:47:43 PM PST 24
Peak memory 201284 kb
Host smart-cd652667-34cc-47d4-a5c8-3163289ea663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781067793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2781067793
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3746669010
Short name T288
Test name
Test status
Simulation time 160177650005 ps
CPU time 357.22 seconds
Started Feb 21 12:47:50 PM PST 24
Finished Feb 21 12:53:48 PM PST 24
Peak memory 201444 kb
Host smart-7c4fa21d-67fd-4306-bc44-a3c35200f8df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746669010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3746669010
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.4178943954
Short name T214
Test name
Test status
Simulation time 167126985994 ps
CPU time 97.04 seconds
Started Feb 21 12:47:40 PM PST 24
Finished Feb 21 12:49:18 PM PST 24
Peak memory 201600 kb
Host smart-48aa6325-9085-4572-a2dd-b6325392fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178943954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4178943954
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1890079148
Short name T203
Test name
Test status
Simulation time 167763109762 ps
CPU time 416.31 seconds
Started Feb 21 12:47:43 PM PST 24
Finished Feb 21 12:54:40 PM PST 24
Peak memory 201388 kb
Host smart-7fa4eba9-0d20-45ad-b29b-0f85becd7e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890079148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1890079148
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2798993368
Short name T475
Test name
Test status
Simulation time 165132034498 ps
CPU time 93.93 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:49:22 PM PST 24
Peak memory 201744 kb
Host smart-1091a186-6f8d-4fa3-b0d4-5f54435fce9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798993368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2798993368
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.137338155
Short name T443
Test name
Test status
Simulation time 162885083028 ps
CPU time 97.77 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:49:25 PM PST 24
Peak memory 201496 kb
Host smart-3586dff3-5b3a-40fe-a238-a5ab16d8b63b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=137338155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.137338155
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3539608148
Short name T776
Test name
Test status
Simulation time 326150051126 ps
CPU time 752.22 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 01:00:20 PM PST 24
Peak memory 201508 kb
Host smart-c64a27b8-f657-4fb7-b88c-073b0a2e2316
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539608148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3539608148
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1607087594
Short name T566
Test name
Test status
Simulation time 331246154051 ps
CPU time 90 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:49:18 PM PST 24
Peak memory 201508 kb
Host smart-9044e938-680a-4b97-927d-91958363de26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607087594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1607087594
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.585825486
Short name T519
Test name
Test status
Simulation time 107009336977 ps
CPU time 428.62 seconds
Started Feb 21 12:47:42 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 201888 kb
Host smart-2bfd3d3d-6321-42a6-ba2b-9d0ef8b09ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585825486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.585825486
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.430361325
Short name T491
Test name
Test status
Simulation time 33336066464 ps
CPU time 6.74 seconds
Started Feb 21 12:47:58 PM PST 24
Finished Feb 21 12:48:06 PM PST 24
Peak memory 201352 kb
Host smart-346838ec-c2b4-4bed-8581-38ef422328bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430361325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.430361325
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2807120655
Short name T414
Test name
Test status
Simulation time 3643282387 ps
CPU time 9.4 seconds
Started Feb 21 12:47:48 PM PST 24
Finished Feb 21 12:47:58 PM PST 24
Peak memory 201328 kb
Host smart-77737884-4667-4cb9-bed1-f265f9f6894d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807120655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2807120655
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1951316203
Short name T1
Test name
Test status
Simulation time 5862732202 ps
CPU time 3.46 seconds
Started Feb 21 12:47:58 PM PST 24
Finished Feb 21 12:48:02 PM PST 24
Peak memory 201340 kb
Host smart-03a7847e-a4fa-4f05-b896-3bb251272d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951316203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1951316203
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.505085934
Short name T311
Test name
Test status
Simulation time 330343720688 ps
CPU time 388.98 seconds
Started Feb 21 12:47:41 PM PST 24
Finished Feb 21 12:54:11 PM PST 24
Peak memory 201544 kb
Host smart-9321b6c9-b468-4cd6-a449-d1043278447b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505085934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
505085934
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2827863996
Short name T444
Test name
Test status
Simulation time 463807893 ps
CPU time 0.89 seconds
Started Feb 21 12:47:50 PM PST 24
Finished Feb 21 12:47:51 PM PST 24
Peak memory 201244 kb
Host smart-03b72798-de37-4edf-a289-49715554cf43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827863996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2827863996
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1995301116
Short name T333
Test name
Test status
Simulation time 166052675800 ps
CPU time 358.73 seconds
Started Feb 21 12:47:53 PM PST 24
Finished Feb 21 12:53:52 PM PST 24
Peak memory 201592 kb
Host smart-4d93fc89-5923-4443-9d37-85e091fb258c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995301116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1995301116
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1838994156
Short name T83
Test name
Test status
Simulation time 487528319765 ps
CPU time 233.69 seconds
Started Feb 21 12:47:42 PM PST 24
Finished Feb 21 12:51:36 PM PST 24
Peak memory 201520 kb
Host smart-4682eec2-20e2-446f-b743-1efa0f701881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838994156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1838994156
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3561020299
Short name T191
Test name
Test status
Simulation time 329654126331 ps
CPU time 358.37 seconds
Started Feb 21 12:47:40 PM PST 24
Finished Feb 21 12:53:39 PM PST 24
Peak memory 201560 kb
Host smart-c0f65084-08bf-4bb9-95ed-a07d86c0c946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561020299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3561020299
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.4013274064
Short name T631
Test name
Test status
Simulation time 495952510956 ps
CPU time 255.01 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:52:04 PM PST 24
Peak memory 201596 kb
Host smart-efdcade7-33d3-444c-9369-13a282d563ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013274064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.4013274064
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.4161964352
Short name T18
Test name
Test status
Simulation time 492523278845 ps
CPU time 1017.79 seconds
Started Feb 21 12:47:53 PM PST 24
Finished Feb 21 01:04:51 PM PST 24
Peak memory 201552 kb
Host smart-90f2371c-1b55-4a4a-ad2d-2aeff0012915
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161964352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.4161964352
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.218144911
Short name T657
Test name
Test status
Simulation time 332999176012 ps
CPU time 182.65 seconds
Started Feb 21 12:47:50 PM PST 24
Finished Feb 21 12:50:53 PM PST 24
Peak memory 201480 kb
Host smart-f0e9ba47-da5d-4793-9897-cc0b7176b233
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218144911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.218144911
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.614942727
Short name T52
Test name
Test status
Simulation time 67125303546 ps
CPU time 260.47 seconds
Started Feb 21 12:47:42 PM PST 24
Finished Feb 21 12:52:09 PM PST 24
Peak memory 201880 kb
Host smart-9a76bc0c-4b4b-4abc-b920-97c8ee3b6ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614942727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.614942727
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3269809665
Short name T472
Test name
Test status
Simulation time 36170561243 ps
CPU time 22.33 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:48:10 PM PST 24
Peak memory 201308 kb
Host smart-10828736-88c7-4b99-bfb3-c8f5b985b8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269809665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3269809665
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2858815144
Short name T455
Test name
Test status
Simulation time 3487681231 ps
CPU time 8.55 seconds
Started Feb 21 12:47:56 PM PST 24
Finished Feb 21 12:48:05 PM PST 24
Peak memory 201288 kb
Host smart-8a0fa7a2-d7ee-4047-a447-af1421763e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858815144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2858815144
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2638317927
Short name T99
Test name
Test status
Simulation time 6088230441 ps
CPU time 13.58 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:48:03 PM PST 24
Peak memory 201232 kb
Host smart-91791d61-4fce-44ee-be2f-09f67dc6b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638317927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2638317927
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.76707032
Short name T51
Test name
Test status
Simulation time 334347503336 ps
CPU time 188.92 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:50:59 PM PST 24
Peak memory 201480 kb
Host smart-c9b4e59a-db65-4e9d-8368-2d1673fa3d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76707032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.76707032
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2069305527
Short name T344
Test name
Test status
Simulation time 21905948224 ps
CPU time 41.48 seconds
Started Feb 21 12:47:42 PM PST 24
Finished Feb 21 12:48:24 PM PST 24
Peak memory 209840 kb
Host smart-c2be6979-f2b1-45bd-8c24-d16e1dc96da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069305527 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2069305527
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2665616458
Short name T434
Test name
Test status
Simulation time 515457100 ps
CPU time 1.87 seconds
Started Feb 21 12:47:43 PM PST 24
Finished Feb 21 12:47:45 PM PST 24
Peak memory 201276 kb
Host smart-5568a860-92ab-4f2a-8068-18147a67a000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665616458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2665616458
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.925220295
Short name T195
Test name
Test status
Simulation time 495371591193 ps
CPU time 225.24 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:51:34 PM PST 24
Peak memory 201460 kb
Host smart-f6ab2b8e-5fb2-4d25-81f3-ddb25e925040
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925220295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.925220295
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4032319761
Short name T66
Test name
Test status
Simulation time 175070236124 ps
CPU time 31.07 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:48:23 PM PST 24
Peak memory 201604 kb
Host smart-7c6ba8fc-2dfd-49fd-9ffb-d175dff928d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032319761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4032319761
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3758646677
Short name T306
Test name
Test status
Simulation time 167728002986 ps
CPU time 110.72 seconds
Started Feb 21 12:47:43 PM PST 24
Finished Feb 21 12:49:34 PM PST 24
Peak memory 201388 kb
Host smart-43acaf22-454a-4099-9b2a-34b36440bf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758646677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3758646677
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3941246135
Short name T498
Test name
Test status
Simulation time 165550978517 ps
CPU time 157.31 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:50:27 PM PST 24
Peak memory 201492 kb
Host smart-0a1a0255-5182-4a0e-8a57-f5020158602b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941246135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3941246135
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2119051684
Short name T184
Test name
Test status
Simulation time 501293501492 ps
CPU time 183.01 seconds
Started Feb 21 12:47:44 PM PST 24
Finished Feb 21 12:50:47 PM PST 24
Peak memory 201568 kb
Host smart-f8338fbf-c5df-404b-8f59-e9ef5d2ae6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119051684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2119051684
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2357571261
Short name T730
Test name
Test status
Simulation time 331071121169 ps
CPU time 235.3 seconds
Started Feb 21 12:47:48 PM PST 24
Finished Feb 21 12:51:44 PM PST 24
Peak memory 201504 kb
Host smart-2fe5e2e4-9b28-406c-9cf4-6746c4cd4b66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357571261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2357571261
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1080006603
Short name T53
Test name
Test status
Simulation time 330622142273 ps
CPU time 782.23 seconds
Started Feb 21 12:47:47 PM PST 24
Finished Feb 21 01:00:51 PM PST 24
Peak memory 201480 kb
Host smart-ac3b8c67-3c2a-46e8-b88f-4f06b27892d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080006603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1080006603
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2383719527
Short name T404
Test name
Test status
Simulation time 322466424183 ps
CPU time 398.57 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:54:28 PM PST 24
Peak memory 201496 kb
Host smart-93119f75-8f3c-4a11-80d3-ddaf73a99036
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383719527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2383719527
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1600066919
Short name T503
Test name
Test status
Simulation time 98894274859 ps
CPU time 335.15 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:53:22 PM PST 24
Peak memory 201800 kb
Host smart-389ef039-8279-4492-8b60-c3f5f63ec8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600066919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1600066919
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2095316592
Short name T394
Test name
Test status
Simulation time 30284607968 ps
CPU time 71.15 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:49:00 PM PST 24
Peak memory 201276 kb
Host smart-1235236b-9c13-4247-ab71-2eb8b19f2b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095316592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2095316592
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2366924122
Short name T474
Test name
Test status
Simulation time 3255824189 ps
CPU time 8.17 seconds
Started Feb 21 12:47:47 PM PST 24
Finished Feb 21 12:47:57 PM PST 24
Peak memory 201292 kb
Host smart-9a1e655d-00f8-41a6-99b6-aaef307eb76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366924122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2366924122
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2997780430
Short name T742
Test name
Test status
Simulation time 6211888870 ps
CPU time 4.59 seconds
Started Feb 21 12:47:50 PM PST 24
Finished Feb 21 12:47:55 PM PST 24
Peak memory 201312 kb
Host smart-0aa24444-4dac-4f40-8cb4-3f445ae0daf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997780430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2997780430
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1275609987
Short name T648
Test name
Test status
Simulation time 608773474110 ps
CPU time 1528.6 seconds
Started Feb 21 12:48:01 PM PST 24
Finished Feb 21 01:13:31 PM PST 24
Peak memory 209992 kb
Host smart-54d7991d-c755-4bba-8880-75c0507e7371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275609987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1275609987
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.894372152
Short name T122
Test name
Test status
Simulation time 239118605783 ps
CPU time 171.32 seconds
Started Feb 21 12:47:43 PM PST 24
Finished Feb 21 12:50:34 PM PST 24
Peak memory 210076 kb
Host smart-5a7aa47f-5de0-40fa-a80b-7adf677dea42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894372152 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.894372152
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.665950425
Short name T413
Test name
Test status
Simulation time 543875073 ps
CPU time 0.94 seconds
Started Feb 21 12:47:06 PM PST 24
Finished Feb 21 12:47:07 PM PST 24
Peak memory 201204 kb
Host smart-dcd66f79-b97a-4cd5-a34d-dd5208d8fa2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665950425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.665950425
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1381703469
Short name T290
Test name
Test status
Simulation time 165385113684 ps
CPU time 309.22 seconds
Started Feb 21 12:47:01 PM PST 24
Finished Feb 21 12:52:11 PM PST 24
Peak memory 201560 kb
Host smart-c374cc1b-7a7f-4f00-b1a0-54e8a9b2a57b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381703469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1381703469
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.826658502
Short name T97
Test name
Test status
Simulation time 166776599021 ps
CPU time 165.86 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:50:04 PM PST 24
Peak memory 201508 kb
Host smart-0e2c2ef0-ce06-497d-9443-dc4fc8527a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826658502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.826658502
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1914855956
Short name T723
Test name
Test status
Simulation time 161506493321 ps
CPU time 79.67 seconds
Started Feb 21 12:47:10 PM PST 24
Finished Feb 21 12:48:30 PM PST 24
Peak memory 201444 kb
Host smart-3f8f846c-01b5-425f-81cf-2dae8ef77cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914855956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1914855956
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3051172501
Short name T563
Test name
Test status
Simulation time 172374970455 ps
CPU time 382.09 seconds
Started Feb 21 12:47:00 PM PST 24
Finished Feb 21 12:53:24 PM PST 24
Peak memory 201560 kb
Host smart-c224e017-e36c-49b6-a111-58a131f461d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051172501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3051172501
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3827961775
Short name T684
Test name
Test status
Simulation time 333376380285 ps
CPU time 374.05 seconds
Started Feb 21 12:47:00 PM PST 24
Finished Feb 21 12:53:15 PM PST 24
Peak memory 201552 kb
Host smart-7d8a35fe-24b8-494c-a750-9e5b56aaed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827961775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3827961775
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.752793642
Short name T542
Test name
Test status
Simulation time 161623464897 ps
CPU time 40.05 seconds
Started Feb 21 12:47:11 PM PST 24
Finished Feb 21 12:47:51 PM PST 24
Peak memory 201500 kb
Host smart-e9f093ce-122a-445d-b4ef-e7bdde1f30e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=752793642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.752793642
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3372117743
Short name T635
Test name
Test status
Simulation time 163636861403 ps
CPU time 173.29 seconds
Started Feb 21 12:47:13 PM PST 24
Finished Feb 21 12:50:06 PM PST 24
Peak memory 201496 kb
Host smart-e777de94-3b47-4abe-b60f-e0266be496b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372117743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3372117743
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.694677844
Short name T544
Test name
Test status
Simulation time 163166302131 ps
CPU time 95.63 seconds
Started Feb 21 12:47:00 PM PST 24
Finished Feb 21 12:48:37 PM PST 24
Peak memory 201564 kb
Host smart-b52cd1b9-3907-4f67-8f97-5c543b62c407
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694677844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.694677844
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.54785362
Short name T454
Test name
Test status
Simulation time 99498124877 ps
CPU time 367.2 seconds
Started Feb 21 12:47:10 PM PST 24
Finished Feb 21 12:53:17 PM PST 24
Peak memory 201812 kb
Host smart-aa38804d-eb4c-4d37-8fff-4e159778dc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54785362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.54785362
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3826633414
Short name T426
Test name
Test status
Simulation time 24724229577 ps
CPU time 5.36 seconds
Started Feb 21 12:47:12 PM PST 24
Finished Feb 21 12:47:18 PM PST 24
Peak memory 201240 kb
Host smart-4276958e-ab57-483c-bd75-837901201267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826633414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3826633414
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3479080022
Short name T663
Test name
Test status
Simulation time 4500302074 ps
CPU time 3.38 seconds
Started Feb 21 12:47:09 PM PST 24
Finished Feb 21 12:47:13 PM PST 24
Peak memory 201256 kb
Host smart-c412fb6f-8441-42ed-8eb4-0cfb7b74d943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479080022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3479080022
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4285097547
Short name T585
Test name
Test status
Simulation time 5869907568 ps
CPU time 12.72 seconds
Started Feb 21 12:47:06 PM PST 24
Finished Feb 21 12:47:19 PM PST 24
Peak memory 201232 kb
Host smart-a117bee9-5242-458e-85dc-1dc71fe4baf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285097547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4285097547
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1412734240
Short name T623
Test name
Test status
Simulation time 340128093918 ps
CPU time 186.1 seconds
Started Feb 21 12:47:09 PM PST 24
Finished Feb 21 12:50:16 PM PST 24
Peak memory 201412 kb
Host smart-cc8f8824-41d3-423c-9989-a34d254dd875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412734240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1412734240
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3631695973
Short name T62
Test name
Test status
Simulation time 65983666685 ps
CPU time 160.89 seconds
Started Feb 21 12:47:07 PM PST 24
Finished Feb 21 12:49:48 PM PST 24
Peak memory 217788 kb
Host smart-0836894f-6059-4636-b183-5d0f88d7467b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631695973 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3631695973
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3170004637
Short name T43
Test name
Test status
Simulation time 338579125 ps
CPU time 1.37 seconds
Started Feb 21 12:47:48 PM PST 24
Finished Feb 21 12:47:50 PM PST 24
Peak memory 201236 kb
Host smart-c0386340-7b23-4c77-bae4-be8e975cd7e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170004637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3170004637
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2418016517
Short name T331
Test name
Test status
Simulation time 490203030112 ps
CPU time 500.28 seconds
Started Feb 21 12:47:43 PM PST 24
Finished Feb 21 12:56:04 PM PST 24
Peak memory 201396 kb
Host smart-2d4c5c4b-e5a9-47d3-906c-f9ec6b24c882
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418016517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2418016517
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4292122339
Short name T243
Test name
Test status
Simulation time 163895858603 ps
CPU time 203.31 seconds
Started Feb 21 12:47:41 PM PST 24
Finished Feb 21 12:51:05 PM PST 24
Peak memory 201568 kb
Host smart-9e5648e8-c66a-49e0-aa82-b6a1df1f7b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292122339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4292122339
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1754979743
Short name T246
Test name
Test status
Simulation time 319430945887 ps
CPU time 333.03 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:53:25 PM PST 24
Peak memory 201524 kb
Host smart-c9c1140d-b421-4f0f-a2e0-537d42b65a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754979743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1754979743
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.911718621
Short name T793
Test name
Test status
Simulation time 484315170324 ps
CPU time 482.66 seconds
Started Feb 21 12:47:45 PM PST 24
Finished Feb 21 12:55:48 PM PST 24
Peak memory 201448 kb
Host smart-ec8d7ea9-2cf3-4f7a-a986-29bc9fc7dab5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=911718621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.911718621
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1153294761
Short name T360
Test name
Test status
Simulation time 498226807800 ps
CPU time 1124.33 seconds
Started Feb 21 12:47:43 PM PST 24
Finished Feb 21 01:06:28 PM PST 24
Peak memory 201512 kb
Host smart-72034b16-35b8-451c-a4cc-5821ad2778bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153294761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1153294761
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.4100310069
Short name T415
Test name
Test status
Simulation time 329835141559 ps
CPU time 382.02 seconds
Started Feb 21 12:47:47 PM PST 24
Finished Feb 21 12:54:10 PM PST 24
Peak memory 201500 kb
Host smart-8d36ed2a-1290-4221-869e-3712d67a161f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100310069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.4100310069
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.927793281
Short name T599
Test name
Test status
Simulation time 168887257877 ps
CPU time 200.17 seconds
Started Feb 21 12:47:44 PM PST 24
Finished Feb 21 12:51:05 PM PST 24
Peak memory 201452 kb
Host smart-0199ec6b-c9ce-4b04-8399-372562c6e5b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927793281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.927793281
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2852898628
Short name T573
Test name
Test status
Simulation time 329380500994 ps
CPU time 200.27 seconds
Started Feb 21 12:47:51 PM PST 24
Finished Feb 21 12:51:11 PM PST 24
Peak memory 201472 kb
Host smart-b25c1984-b6b6-4fea-9b84-d855903cd118
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852898628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2852898628
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.781985024
Short name T636
Test name
Test status
Simulation time 87004613536 ps
CPU time 460.15 seconds
Started Feb 21 12:47:51 PM PST 24
Finished Feb 21 12:55:32 PM PST 24
Peak memory 200788 kb
Host smart-26db5a3f-a4d0-4ef0-912b-fd33ed54d6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781985024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.781985024
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2497874727
Short name T213
Test name
Test status
Simulation time 30809416826 ps
CPU time 75.45 seconds
Started Feb 21 12:47:42 PM PST 24
Finished Feb 21 12:48:58 PM PST 24
Peak memory 201352 kb
Host smart-546c0dda-4948-41d2-8290-e5b3a92b1503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497874727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2497874727
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.313143661
Short name T559
Test name
Test status
Simulation time 3755314973 ps
CPU time 9.01 seconds
Started Feb 21 12:47:40 PM PST 24
Finished Feb 21 12:47:50 PM PST 24
Peak memory 201236 kb
Host smart-61f7f669-42a2-4ff0-9df5-cbe59a1673e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313143661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.313143661
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3715985400
Short name T580
Test name
Test status
Simulation time 5875896441 ps
CPU time 3.92 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:47:42 PM PST 24
Peak memory 201236 kb
Host smart-0502eb41-980a-41f2-91ee-3d6515f8edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715985400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3715985400
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3848019169
Short name T729
Test name
Test status
Simulation time 380720537491 ps
CPU time 55.56 seconds
Started Feb 21 12:47:54 PM PST 24
Finished Feb 21 12:48:50 PM PST 24
Peak memory 201576 kb
Host smart-d028cf44-e877-432b-a9ca-da7ae69cf9eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848019169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3848019169
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2899693554
Short name T507
Test name
Test status
Simulation time 378376594 ps
CPU time 1.07 seconds
Started Feb 21 12:47:54 PM PST 24
Finished Feb 21 12:47:56 PM PST 24
Peak memory 201224 kb
Host smart-8a1f47f5-485b-4237-a52a-f984c4e019cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899693554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2899693554
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3906464794
Short name T790
Test name
Test status
Simulation time 166555233414 ps
CPU time 385.39 seconds
Started Feb 21 12:47:56 PM PST 24
Finished Feb 21 12:54:23 PM PST 24
Peak memory 201496 kb
Host smart-b5305bd8-791c-4388-8cc0-6c89137465c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906464794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3906464794
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3457837596
Short name T605
Test name
Test status
Simulation time 478601124267 ps
CPU time 554.43 seconds
Started Feb 21 12:47:50 PM PST 24
Finished Feb 21 12:57:04 PM PST 24
Peak memory 201520 kb
Host smart-5b621226-fa55-4021-98fd-4f7ef0ba8450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457837596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3457837596
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2579808441
Short name T476
Test name
Test status
Simulation time 167590031791 ps
CPU time 347.06 seconds
Started Feb 21 12:47:58 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 201512 kb
Host smart-5f04e572-c1f3-40e2-a4f7-e1315a637a06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579808441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2579808441
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.131339156
Short name T204
Test name
Test status
Simulation time 166233430239 ps
CPU time 359.29 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 201500 kb
Host smart-c2b875f7-2e51-4ff9-8b5c-50ef088e8849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131339156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.131339156
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3857112638
Short name T528
Test name
Test status
Simulation time 331925569365 ps
CPU time 178.28 seconds
Started Feb 21 12:47:50 PM PST 24
Finished Feb 21 12:50:48 PM PST 24
Peak memory 201568 kb
Host smart-18d72448-2c9e-434f-8d9f-4d82c557cbab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857112638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3857112638
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1783985453
Short name T711
Test name
Test status
Simulation time 487177842293 ps
CPU time 995.36 seconds
Started Feb 21 12:47:45 PM PST 24
Finished Feb 21 01:04:20 PM PST 24
Peak memory 201440 kb
Host smart-ae6942a3-69e8-4e98-903e-c814f7ad2192
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783985453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1783985453
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3443671663
Short name T408
Test name
Test status
Simulation time 163969608686 ps
CPU time 97.97 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:49:28 PM PST 24
Peak memory 201512 kb
Host smart-8ea86bf4-000e-4a29-aae0-56fa90ebf833
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443671663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3443671663
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2449923285
Short name T439
Test name
Test status
Simulation time 79613658692 ps
CPU time 332.69 seconds
Started Feb 21 12:47:51 PM PST 24
Finished Feb 21 12:53:24 PM PST 24
Peak memory 200708 kb
Host smart-ff89953e-df61-4f44-bb10-f60257de88d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449923285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2449923285
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3603937351
Short name T524
Test name
Test status
Simulation time 31285040148 ps
CPU time 10.09 seconds
Started Feb 21 12:47:41 PM PST 24
Finished Feb 21 12:47:51 PM PST 24
Peak memory 201304 kb
Host smart-689f28ba-d276-4fdb-8e59-d0ccbb41f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603937351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3603937351
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1889317864
Short name T662
Test name
Test status
Simulation time 5243167712 ps
CPU time 6.93 seconds
Started Feb 21 12:47:47 PM PST 24
Finished Feb 21 12:47:55 PM PST 24
Peak memory 201252 kb
Host smart-dadd9630-8904-496e-b6c1-a59f58a24f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889317864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1889317864
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3892312339
Short name T735
Test name
Test status
Simulation time 6194866449 ps
CPU time 14.32 seconds
Started Feb 21 12:47:54 PM PST 24
Finished Feb 21 12:48:09 PM PST 24
Peak memory 201264 kb
Host smart-8ce40be8-b489-409b-91f3-3a700ac0f020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892312339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3892312339
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.770801052
Short name T628
Test name
Test status
Simulation time 178681639287 ps
CPU time 875.11 seconds
Started Feb 21 12:47:51 PM PST 24
Finished Feb 21 01:02:26 PM PST 24
Peak memory 201828 kb
Host smart-4952ee41-0391-461f-95ba-42df09efdee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770801052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
770801052
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3864074359
Short name T459
Test name
Test status
Simulation time 421221068 ps
CPU time 1.15 seconds
Started Feb 21 12:47:58 PM PST 24
Finished Feb 21 12:48:00 PM PST 24
Peak memory 201288 kb
Host smart-1227afb1-6e8e-417d-b66e-dfd26f795bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864074359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3864074359
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4236388979
Short name T355
Test name
Test status
Simulation time 488863401849 ps
CPU time 426.66 seconds
Started Feb 21 12:47:53 PM PST 24
Finished Feb 21 12:55:00 PM PST 24
Peak memory 201504 kb
Host smart-8539dad5-e90e-43ba-b2c1-a17c3d90cace
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236388979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4236388979
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2313204254
Short name T707
Test name
Test status
Simulation time 163381486058 ps
CPU time 406.77 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 201548 kb
Host smart-26cdb4b6-a510-405d-84f8-822d0d06dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313204254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2313204254
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.656728064
Short name T622
Test name
Test status
Simulation time 325628443440 ps
CPU time 190.44 seconds
Started Feb 21 12:47:54 PM PST 24
Finished Feb 21 12:51:05 PM PST 24
Peak memory 201468 kb
Host smart-938dd03d-1f35-46cd-99f7-f153c1de74ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=656728064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.656728064
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2627294585
Short name T100
Test name
Test status
Simulation time 495040102107 ps
CPU time 1078.62 seconds
Started Feb 21 12:47:53 PM PST 24
Finished Feb 21 01:05:52 PM PST 24
Peak memory 201476 kb
Host smart-dcba122c-c02c-4b15-97a6-81b1f2c84302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627294585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2627294585
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1021969980
Short name T448
Test name
Test status
Simulation time 335022445817 ps
CPU time 698.49 seconds
Started Feb 21 12:47:51 PM PST 24
Finished Feb 21 12:59:30 PM PST 24
Peak memory 201468 kb
Host smart-d47ff706-2dcc-4fec-bbf2-2818ddb63b7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021969980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1021969980
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1569395219
Short name T429
Test name
Test status
Simulation time 500390179379 ps
CPU time 335.03 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:53:25 PM PST 24
Peak memory 201560 kb
Host smart-7dbb5cd1-0e1a-4f39-916f-17a3e507027a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569395219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1569395219
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1111389297
Short name T379
Test name
Test status
Simulation time 83971851594 ps
CPU time 399.6 seconds
Started Feb 21 12:47:53 PM PST 24
Finished Feb 21 12:54:33 PM PST 24
Peak memory 201796 kb
Host smart-fe71c27f-5a51-4111-8ba0-09ec61e39f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111389297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1111389297
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3390524769
Short name T583
Test name
Test status
Simulation time 32081682241 ps
CPU time 7.55 seconds
Started Feb 21 12:48:11 PM PST 24
Finished Feb 21 12:48:19 PM PST 24
Peak memory 201276 kb
Host smart-64c1cd78-5dc2-46b3-8809-290a24e31204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390524769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3390524769
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2385525237
Short name T539
Test name
Test status
Simulation time 5283890570 ps
CPU time 6.44 seconds
Started Feb 21 12:48:08 PM PST 24
Finished Feb 21 12:48:15 PM PST 24
Peak memory 201288 kb
Host smart-e416e439-6456-49aa-aabf-ac67993caa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385525237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2385525237
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3486888384
Short name T611
Test name
Test status
Simulation time 5622296309 ps
CPU time 1.81 seconds
Started Feb 21 12:47:53 PM PST 24
Finished Feb 21 12:47:55 PM PST 24
Peak memory 201196 kb
Host smart-3789cebc-fae1-4f89-bae5-249d5d1ea947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486888384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3486888384
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.976357442
Short name T356
Test name
Test status
Simulation time 369108142803 ps
CPU time 415.2 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 12:54:59 PM PST 24
Peak memory 201472 kb
Host smart-e6c0a77c-3f13-42e9-99f1-cc86f9e7da3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976357442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
976357442
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3934644939
Short name T712
Test name
Test status
Simulation time 59125550626 ps
CPU time 94.86 seconds
Started Feb 21 12:47:48 PM PST 24
Finished Feb 21 12:49:24 PM PST 24
Peak memory 210176 kb
Host smart-6611d027-ed55-4bb4-b2ea-ac192ed8e238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934644939 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3934644939
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3965373536
Short name T446
Test name
Test status
Simulation time 504579868 ps
CPU time 0.91 seconds
Started Feb 21 12:48:11 PM PST 24
Finished Feb 21 12:48:12 PM PST 24
Peak memory 201224 kb
Host smart-2e9ff768-a3b2-49f0-a20e-2a118cc5bfd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965373536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3965373536
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2204131525
Short name T719
Test name
Test status
Simulation time 325067351144 ps
CPU time 177.65 seconds
Started Feb 21 12:48:10 PM PST 24
Finished Feb 21 12:51:08 PM PST 24
Peak memory 201492 kb
Host smart-a931694f-5004-46a0-8750-20baed93d25a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204131525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2204131525
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1357269930
Short name T513
Test name
Test status
Simulation time 163599204120 ps
CPU time 137.66 seconds
Started Feb 21 12:48:11 PM PST 24
Finished Feb 21 12:50:29 PM PST 24
Peak memory 201512 kb
Host smart-5d485ffc-e52b-41e5-9450-b0b07fe85d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357269930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1357269930
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2276568242
Short name T591
Test name
Test status
Simulation time 325073216219 ps
CPU time 192.94 seconds
Started Feb 21 12:47:50 PM PST 24
Finished Feb 21 12:51:03 PM PST 24
Peak memory 201560 kb
Host smart-86c22460-052a-4925-bcb7-281976fdca71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276568242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2276568242
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.4094404531
Short name T353
Test name
Test status
Simulation time 166915107924 ps
CPU time 98.65 seconds
Started Feb 21 12:47:46 PM PST 24
Finished Feb 21 12:49:26 PM PST 24
Peak memory 201524 kb
Host smart-2c7dcfd2-abce-4a31-add2-ccaa87cf3443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094404531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.4094404531
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1107830536
Short name T508
Test name
Test status
Simulation time 166070431788 ps
CPU time 103.51 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 12:49:48 PM PST 24
Peak memory 201480 kb
Host smart-6bcd4963-991e-4540-a2f8-98529fd83d14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107830536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1107830536
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1940871639
Short name T553
Test name
Test status
Simulation time 168588795650 ps
CPU time 103.29 seconds
Started Feb 21 12:47:58 PM PST 24
Finished Feb 21 12:49:42 PM PST 24
Peak memory 201548 kb
Host smart-f3fa1c4a-dd71-487f-98f4-4da1298b6817
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940871639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1940871639
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.718755096
Short name T574
Test name
Test status
Simulation time 168324169590 ps
CPU time 105.35 seconds
Started Feb 21 12:47:58 PM PST 24
Finished Feb 21 12:49:45 PM PST 24
Peak memory 201604 kb
Host smart-8fa2388a-804f-4b5f-b8ef-5e0651566387
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718755096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.718755096
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2542789151
Short name T369
Test name
Test status
Simulation time 91084734103 ps
CPU time 271.14 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:52:20 PM PST 24
Peak memory 201856 kb
Host smart-c91d761b-4b60-4922-994e-5ed7a6dd1985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542789151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2542789151
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1629804514
Short name T406
Test name
Test status
Simulation time 38090733438 ps
CPU time 45.04 seconds
Started Feb 21 12:47:51 PM PST 24
Finished Feb 21 12:48:36 PM PST 24
Peak memory 201288 kb
Host smart-d5aef3bb-7ffb-4d1c-9753-a18a6978bd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629804514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1629804514
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.4169403086
Short name T393
Test name
Test status
Simulation time 5222506585 ps
CPU time 13.11 seconds
Started Feb 21 12:47:54 PM PST 24
Finished Feb 21 12:48:08 PM PST 24
Peak memory 201272 kb
Host smart-cf266447-773b-4123-bf99-74e991ee1602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169403086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4169403086
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2262278314
Short name T694
Test name
Test status
Simulation time 5745672293 ps
CPU time 14.25 seconds
Started Feb 21 12:47:48 PM PST 24
Finished Feb 21 12:48:03 PM PST 24
Peak memory 201300 kb
Host smart-5c7096f9-9f97-4d47-a0d0-85dc4342d5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262278314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2262278314
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2546014811
Short name T488
Test name
Test status
Simulation time 84775450553 ps
CPU time 53.83 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:48:43 PM PST 24
Peak memory 201220 kb
Host smart-beb7dff1-bca5-40f8-b4cc-c23d7560d4ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546014811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2546014811
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1811797373
Short name T73
Test name
Test status
Simulation time 154396519351 ps
CPU time 165.95 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:50:39 PM PST 24
Peak memory 210184 kb
Host smart-60ef78fd-d8c5-4bd8-a84f-3ca830ceb78c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811797373 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1811797373
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.4223200565
Short name T92
Test name
Test status
Simulation time 505499947 ps
CPU time 1.18 seconds
Started Feb 21 12:47:56 PM PST 24
Finished Feb 21 12:47:59 PM PST 24
Peak memory 201232 kb
Host smart-540a1f45-416a-47cd-9689-860939ad1518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223200565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4223200565
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.893835143
Short name T198
Test name
Test status
Simulation time 492200454046 ps
CPU time 251.6 seconds
Started Feb 21 12:47:51 PM PST 24
Finished Feb 21 12:52:03 PM PST 24
Peak memory 201492 kb
Host smart-141e56f6-ab6a-4a3b-a699-cb27f8a3d1d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893835143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.893835143
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4235966334
Short name T307
Test name
Test status
Simulation time 359416644327 ps
CPU time 471.38 seconds
Started Feb 21 12:47:48 PM PST 24
Finished Feb 21 12:55:40 PM PST 24
Peak memory 201572 kb
Host smart-be09310d-7f63-496e-89d9-33a57cadb838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235966334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4235966334
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3464508631
Short name T748
Test name
Test status
Simulation time 163521064117 ps
CPU time 101.68 seconds
Started Feb 21 12:47:48 PM PST 24
Finished Feb 21 12:49:30 PM PST 24
Peak memory 201472 kb
Host smart-a13ea2c9-ac0d-487c-af2a-51262346a2ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464508631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3464508631
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1112314234
Short name T452
Test name
Test status
Simulation time 319118948666 ps
CPU time 725.9 seconds
Started Feb 21 12:47:53 PM PST 24
Finished Feb 21 12:59:59 PM PST 24
Peak memory 201564 kb
Host smart-f6e1569c-5af7-42fc-b042-f745beb23f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112314234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1112314234
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.486153374
Short name T530
Test name
Test status
Simulation time 327975800496 ps
CPU time 65.27 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 12:48:57 PM PST 24
Peak memory 201392 kb
Host smart-85224500-9bd9-499e-a0a1-d3df29a8fd12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=486153374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.486153374
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2187749418
Short name T604
Test name
Test status
Simulation time 524201861463 ps
CPU time 1238.83 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 01:08:43 PM PST 24
Peak memory 201552 kb
Host smart-c08b69c2-2fb2-4a58-a9af-a58b0a1a775e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187749418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2187749418
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1037349462
Short name T550
Test name
Test status
Simulation time 337361063444 ps
CPU time 748.01 seconds
Started Feb 21 12:47:52 PM PST 24
Finished Feb 21 01:00:20 PM PST 24
Peak memory 201536 kb
Host smart-076c65b3-6796-4e75-bd6f-3b6527b0b244
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037349462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1037349462
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.69334675
Short name T717
Test name
Test status
Simulation time 42551970946 ps
CPU time 95.26 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:49:25 PM PST 24
Peak memory 201220 kb
Host smart-93ce0df2-fc5d-4e6d-8e2c-60e67e66fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69334675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.69334675
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.715618927
Short name T489
Test name
Test status
Simulation time 3472799170 ps
CPU time 9.03 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 12:48:13 PM PST 24
Peak memory 201300 kb
Host smart-67661424-0380-43ac-96a5-d9883852b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715618927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.715618927
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2451709109
Short name T705
Test name
Test status
Simulation time 5781619869 ps
CPU time 7.16 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 12:48:11 PM PST 24
Peak memory 201248 kb
Host smart-f0163389-e56b-4067-8abd-dab0a16a7ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451709109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2451709109
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3201891894
Short name T473
Test name
Test status
Simulation time 305288501658 ps
CPU time 361.8 seconds
Started Feb 21 12:47:48 PM PST 24
Finished Feb 21 12:53:51 PM PST 24
Peak memory 218216 kb
Host smart-36f90186-7e4d-41c2-b92e-c2690873e11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201891894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3201891894
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2536266460
Short name T782
Test name
Test status
Simulation time 430714996 ps
CPU time 1.54 seconds
Started Feb 21 12:48:12 PM PST 24
Finished Feb 21 12:48:14 PM PST 24
Peak memory 201212 kb
Host smart-a37cdfd6-5e65-42cc-9dd7-933a8c9ef8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536266460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2536266460
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2079204110
Short name T136
Test name
Test status
Simulation time 329238618384 ps
CPU time 709.16 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 12:59:53 PM PST 24
Peak memory 201548 kb
Host smart-9fda08f7-753a-4d1f-a670-9438534c8187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079204110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2079204110
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3156194685
Short name T438
Test name
Test status
Simulation time 339470739962 ps
CPU time 729.22 seconds
Started Feb 21 12:48:02 PM PST 24
Finished Feb 21 01:00:12 PM PST 24
Peak memory 201524 kb
Host smart-1b3c938d-b64f-4c0f-ab45-94ef51a218e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156194685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3156194685
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3145432962
Short name T588
Test name
Test status
Simulation time 485582653251 ps
CPU time 643.24 seconds
Started Feb 21 12:47:47 PM PST 24
Finished Feb 21 12:58:32 PM PST 24
Peak memory 201760 kb
Host smart-37c95943-6f78-47f2-9f1b-0157bc4ed9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145432962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3145432962
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3172863432
Short name T594
Test name
Test status
Simulation time 491269090348 ps
CPU time 119.12 seconds
Started Feb 21 12:47:49 PM PST 24
Finished Feb 21 12:49:48 PM PST 24
Peak memory 201480 kb
Host smart-b7eeb9fe-f5d6-429f-bb89-678585bd8daf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172863432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3172863432
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1696568556
Short name T521
Test name
Test status
Simulation time 331391863772 ps
CPU time 749.36 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 01:00:34 PM PST 24
Peak memory 201564 kb
Host smart-a7a5147e-4c00-4121-bd18-9aa2a88b1590
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696568556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1696568556
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.20256965
Short name T21
Test name
Test status
Simulation time 116075129257 ps
CPU time 636.03 seconds
Started Feb 21 12:48:10 PM PST 24
Finished Feb 21 12:58:46 PM PST 24
Peak memory 201776 kb
Host smart-93de64a4-6286-4894-a8ed-4e498ffd2c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20256965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.20256965
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.952742169
Short name T665
Test name
Test status
Simulation time 42219992466 ps
CPU time 90.97 seconds
Started Feb 21 12:48:10 PM PST 24
Finished Feb 21 12:49:41 PM PST 24
Peak memory 201268 kb
Host smart-c12b7cb3-7b48-4183-9e52-c5ecc466b022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952742169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.952742169
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.4259848863
Short name T596
Test name
Test status
Simulation time 4638721468 ps
CPU time 5.89 seconds
Started Feb 21 12:48:01 PM PST 24
Finished Feb 21 12:48:08 PM PST 24
Peak memory 201232 kb
Host smart-0200d002-05b5-484b-be0a-bedc0eb17ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259848863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.4259848863
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.4021494212
Short name T518
Test name
Test status
Simulation time 6171805904 ps
CPU time 3.84 seconds
Started Feb 21 12:47:57 PM PST 24
Finished Feb 21 12:48:01 PM PST 24
Peak memory 201244 kb
Host smart-1a15ae91-04ab-450b-b90d-da9fae4361d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021494212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.4021494212
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.199276425
Short name T362
Test name
Test status
Simulation time 476699183857 ps
CPU time 1865.44 seconds
Started Feb 21 12:48:01 PM PST 24
Finished Feb 21 01:19:08 PM PST 24
Peak memory 209960 kb
Host smart-b0041bf6-3747-45d6-a40d-e314540e7b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199276425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
199276425
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1953395164
Short name T348
Test name
Test status
Simulation time 67089928649 ps
CPU time 93.96 seconds
Started Feb 21 12:48:12 PM PST 24
Finished Feb 21 12:49:46 PM PST 24
Peak memory 215888 kb
Host smart-5285e7dc-8da7-49bf-b891-582c77f56a5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953395164 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1953395164
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2498434587
Short name T603
Test name
Test status
Simulation time 435702467 ps
CPU time 1.5 seconds
Started Feb 21 12:48:08 PM PST 24
Finished Feb 21 12:48:10 PM PST 24
Peak memory 201244 kb
Host smart-f45ae97b-b118-4f28-bf10-e7e78b138528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498434587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2498434587
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.347190077
Short name T316
Test name
Test status
Simulation time 329987823076 ps
CPU time 326.99 seconds
Started Feb 21 12:48:02 PM PST 24
Finished Feb 21 12:53:30 PM PST 24
Peak memory 201552 kb
Host smart-f5c0a8b8-ec56-4f56-afeb-4ca78142b40a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347190077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.347190077
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1019934416
Short name T714
Test name
Test status
Simulation time 329622957756 ps
CPU time 799 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 01:01:23 PM PST 24
Peak memory 201532 kb
Host smart-6fe9cbac-b356-40de-8861-04d8ac4993f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019934416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1019934416
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.468335322
Short name T762
Test name
Test status
Simulation time 492066178592 ps
CPU time 546.76 seconds
Started Feb 21 12:48:01 PM PST 24
Finished Feb 21 12:57:09 PM PST 24
Peak memory 201448 kb
Host smart-75034f8f-5653-45d6-a5f7-e9ea45c11fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468335322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.468335322
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.837132298
Short name T220
Test name
Test status
Simulation time 328453418502 ps
CPU time 197.63 seconds
Started Feb 21 12:48:04 PM PST 24
Finished Feb 21 12:51:22 PM PST 24
Peak memory 201476 kb
Host smart-e1b8ca04-23bf-4b2d-8ea9-4aedf08de1d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=837132298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.837132298
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2782975256
Short name T352
Test name
Test status
Simulation time 166471892949 ps
CPU time 92.78 seconds
Started Feb 21 12:48:02 PM PST 24
Finished Feb 21 12:49:36 PM PST 24
Peak memory 201584 kb
Host smart-92ce2b13-b566-4be7-8fa3-378aabf5a99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782975256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2782975256
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.947884111
Short name T733
Test name
Test status
Simulation time 499553046047 ps
CPU time 139.51 seconds
Started Feb 21 12:48:08 PM PST 24
Finished Feb 21 12:50:28 PM PST 24
Peak memory 201476 kb
Host smart-91905725-8194-4d0f-960d-569197551fe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=947884111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.947884111
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1439833257
Short name T716
Test name
Test status
Simulation time 332192181631 ps
CPU time 745.79 seconds
Started Feb 21 12:48:07 PM PST 24
Finished Feb 21 01:00:33 PM PST 24
Peak memory 201488 kb
Host smart-4e368679-86aa-46c3-a020-525f8fae592e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439833257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1439833257
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.273580207
Short name T235
Test name
Test status
Simulation time 489061840098 ps
CPU time 580.54 seconds
Started Feb 21 12:48:08 PM PST 24
Finished Feb 21 12:57:49 PM PST 24
Peak memory 201516 kb
Host smart-1675b2c2-54db-4c1d-96b4-0755f715c795
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273580207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.273580207
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2248456686
Short name T485
Test name
Test status
Simulation time 76291949148 ps
CPU time 412.79 seconds
Started Feb 21 12:48:12 PM PST 24
Finished Feb 21 12:55:05 PM PST 24
Peak memory 201888 kb
Host smart-be6f5d3e-c2d6-4d5d-bbb0-f2212a7f5787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248456686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2248456686
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2670461123
Short name T720
Test name
Test status
Simulation time 22770189734 ps
CPU time 24.23 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 12:48:28 PM PST 24
Peak memory 201276 kb
Host smart-4b0d94d6-5229-48bb-a9a3-ee9db5a1661e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670461123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2670461123
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.600678629
Short name T8
Test name
Test status
Simulation time 3638658773 ps
CPU time 9.06 seconds
Started Feb 21 12:48:11 PM PST 24
Finished Feb 21 12:48:21 PM PST 24
Peak memory 201280 kb
Host smart-d2321b76-4473-47cc-96d8-2c3da27f65bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600678629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.600678629
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3304958424
Short name T450
Test name
Test status
Simulation time 5706070654 ps
CPU time 14.91 seconds
Started Feb 21 12:48:01 PM PST 24
Finished Feb 21 12:48:17 PM PST 24
Peak memory 201216 kb
Host smart-87209754-56c5-4b0d-81bd-f47be1e5f5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304958424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3304958424
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1889079545
Short name T632
Test name
Test status
Simulation time 356540020339 ps
CPU time 1295.74 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 01:09:40 PM PST 24
Peak memory 210000 kb
Host smart-070a42f3-7a48-4037-b7a8-8672e9025677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889079545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1889079545
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2319185820
Short name T190
Test name
Test status
Simulation time 94362499588 ps
CPU time 94.26 seconds
Started Feb 21 12:48:04 PM PST 24
Finished Feb 21 12:49:39 PM PST 24
Peak memory 210180 kb
Host smart-4d1c9a44-a4f5-4170-9070-ea297a8095b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319185820 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2319185820
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.825600534
Short name T215
Test name
Test status
Simulation time 551648207 ps
CPU time 0.92 seconds
Started Feb 21 12:48:07 PM PST 24
Finished Feb 21 12:48:09 PM PST 24
Peak memory 201148 kb
Host smart-1a28211f-5a62-4164-9a4a-e3c4d280c216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825600534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.825600534
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2728909421
Short name T210
Test name
Test status
Simulation time 163720210966 ps
CPU time 102.67 seconds
Started Feb 21 12:48:07 PM PST 24
Finished Feb 21 12:49:50 PM PST 24
Peak memory 201584 kb
Host smart-476a82e5-186f-426c-9f1e-f0c077ccce16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728909421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2728909421
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1807662341
Short name T681
Test name
Test status
Simulation time 164965973860 ps
CPU time 193.32 seconds
Started Feb 21 12:48:05 PM PST 24
Finished Feb 21 12:51:18 PM PST 24
Peak memory 201472 kb
Host smart-e063c395-c706-41a9-8014-c1b68f90a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807662341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1807662341
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2673173445
Short name T642
Test name
Test status
Simulation time 321510481298 ps
CPU time 383.01 seconds
Started Feb 21 12:48:06 PM PST 24
Finished Feb 21 12:54:29 PM PST 24
Peak memory 201472 kb
Host smart-6f28defd-e62a-47fe-ae42-cc1b0425c44a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673173445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2673173445
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2587181317
Short name T768
Test name
Test status
Simulation time 172230625792 ps
CPU time 181.28 seconds
Started Feb 21 12:47:57 PM PST 24
Finished Feb 21 12:50:59 PM PST 24
Peak memory 201412 kb
Host smart-64b51543-2d53-4db3-a1c3-f0c05cb145ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587181317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2587181317
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4050866007
Short name T616
Test name
Test status
Simulation time 490666116466 ps
CPU time 576.18 seconds
Started Feb 21 12:48:01 PM PST 24
Finished Feb 21 12:57:38 PM PST 24
Peak memory 201476 kb
Host smart-92596664-d959-48b7-98f9-a3a22b9b8a33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050866007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4050866007
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3859188996
Short name T4
Test name
Test status
Simulation time 165118744894 ps
CPU time 173.35 seconds
Started Feb 21 12:48:11 PM PST 24
Finished Feb 21 12:51:05 PM PST 24
Peak memory 201480 kb
Host smart-d45d9550-60c8-4dd7-a173-0e606ac1d4fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859188996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3859188996
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.923586279
Short name T646
Test name
Test status
Simulation time 337877960117 ps
CPU time 195.99 seconds
Started Feb 21 12:48:09 PM PST 24
Finished Feb 21 12:51:26 PM PST 24
Peak memory 201472 kb
Host smart-3495e49f-db9a-48dd-a8dc-a408a0c1782f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923586279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.923586279
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2562328506
Short name T560
Test name
Test status
Simulation time 66945902270 ps
CPU time 352.46 seconds
Started Feb 21 12:48:04 PM PST 24
Finished Feb 21 12:53:57 PM PST 24
Peak memory 201796 kb
Host smart-c00f48df-15f1-4099-b38c-4e180155c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562328506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2562328506
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3336160233
Short name T397
Test name
Test status
Simulation time 39494640337 ps
CPU time 50.44 seconds
Started Feb 21 12:48:03 PM PST 24
Finished Feb 21 12:48:55 PM PST 24
Peak memory 201308 kb
Host smart-4f8b0724-50b7-47a6-8def-1de1f9ebd6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336160233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3336160233
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.302399941
Short name T621
Test name
Test status
Simulation time 4253571946 ps
CPU time 2.86 seconds
Started Feb 21 12:48:05 PM PST 24
Finished Feb 21 12:48:08 PM PST 24
Peak memory 201320 kb
Host smart-42b384c1-24c4-4381-a411-853854050108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302399941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.302399941
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2309598389
Short name T419
Test name
Test status
Simulation time 5907886433 ps
CPU time 4.03 seconds
Started Feb 21 12:48:10 PM PST 24
Finished Feb 21 12:48:14 PM PST 24
Peak memory 201280 kb
Host smart-4b04b8be-2589-47e6-a300-052b87bbdcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309598389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2309598389
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3434806583
Short name T298
Test name
Test status
Simulation time 354015614458 ps
CPU time 780.93 seconds
Started Feb 21 12:48:11 PM PST 24
Finished Feb 21 01:01:12 PM PST 24
Peak memory 201484 kb
Host smart-eb5e6356-8d65-4565-be36-533205da99b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434806583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3434806583
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.895087550
Short name T61
Test name
Test status
Simulation time 139929627387 ps
CPU time 105.39 seconds
Started Feb 21 12:48:09 PM PST 24
Finished Feb 21 12:49:55 PM PST 24
Peak memory 201676 kb
Host smart-f5849fbc-896d-4097-bf69-1edb1fb8dd98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895087550 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.895087550
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1919316672
Short name T224
Test name
Test status
Simulation time 476599886 ps
CPU time 1.59 seconds
Started Feb 21 12:48:16 PM PST 24
Finished Feb 21 12:48:18 PM PST 24
Peak memory 201136 kb
Host smart-d8488f28-59d0-4ce5-adcc-fc8a1b79d41f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919316672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1919316672
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1609010579
Short name T278
Test name
Test status
Simulation time 331989837674 ps
CPU time 388.27 seconds
Started Feb 21 12:48:16 PM PST 24
Finished Feb 21 12:54:45 PM PST 24
Peak memory 201524 kb
Host smart-c9ed1002-a60c-484f-96cb-323e2a7e2193
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609010579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1609010579
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1353386441
Short name T260
Test name
Test status
Simulation time 497717316547 ps
CPU time 342.36 seconds
Started Feb 21 12:48:17 PM PST 24
Finished Feb 21 12:54:00 PM PST 24
Peak memory 201600 kb
Host smart-eea6bf6a-8959-4933-bcff-53f8f3475c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353386441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1353386441
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2230659696
Short name T275
Test name
Test status
Simulation time 328426173118 ps
CPU time 420.76 seconds
Started Feb 21 12:48:10 PM PST 24
Finished Feb 21 12:55:11 PM PST 24
Peak memory 201524 kb
Host smart-d9eab08b-011a-4b96-af19-3e7f2d2f1ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230659696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2230659696
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3473809841
Short name T794
Test name
Test status
Simulation time 496687388387 ps
CPU time 1061.71 seconds
Started Feb 21 12:48:09 PM PST 24
Finished Feb 21 01:05:51 PM PST 24
Peak memory 201480 kb
Host smart-a31ad716-f9c5-432f-9581-4abbdb7a0676
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473809841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3473809841
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3407075241
Short name T471
Test name
Test status
Simulation time 159936679108 ps
CPU time 353.68 seconds
Started Feb 21 12:48:06 PM PST 24
Finished Feb 21 12:54:00 PM PST 24
Peak memory 201580 kb
Host smart-fb5e1a2a-c6d1-4ce9-8ab3-e3f50eb255f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407075241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3407075241
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3061677732
Short name T478
Test name
Test status
Simulation time 165242165736 ps
CPU time 102.58 seconds
Started Feb 21 12:48:06 PM PST 24
Finished Feb 21 12:49:49 PM PST 24
Peak memory 201496 kb
Host smart-37104024-a950-4a05-88e3-b0f32b728f35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061677732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3061677732
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.632629539
Short name T682
Test name
Test status
Simulation time 495520433651 ps
CPU time 271.74 seconds
Started Feb 21 12:48:06 PM PST 24
Finished Feb 21 12:52:38 PM PST 24
Peak memory 201496 kb
Host smart-821e22b1-61d7-4e2f-a61b-6140cc966882
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632629539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.632629539
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1585867157
Short name T421
Test name
Test status
Simulation time 81481081638 ps
CPU time 326.2 seconds
Started Feb 21 12:48:21 PM PST 24
Finished Feb 21 12:53:47 PM PST 24
Peak memory 201804 kb
Host smart-87e6cf5c-9c49-452e-9ba2-4ad16c689782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585867157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1585867157
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.989670259
Short name T645
Test name
Test status
Simulation time 24672423668 ps
CPU time 17.14 seconds
Started Feb 21 12:48:18 PM PST 24
Finished Feb 21 12:48:35 PM PST 24
Peak memory 201272 kb
Host smart-b681e053-33a2-4a41-a74b-9cdfbab270c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989670259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.989670259
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3593747485
Short name T567
Test name
Test status
Simulation time 3580149160 ps
CPU time 8.4 seconds
Started Feb 21 12:48:18 PM PST 24
Finished Feb 21 12:48:27 PM PST 24
Peak memory 201320 kb
Host smart-53b1355f-653e-4a74-86f5-79622e86d30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593747485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3593747485
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2782295311
Short name T555
Test name
Test status
Simulation time 5822765735 ps
CPU time 14.02 seconds
Started Feb 21 12:48:17 PM PST 24
Finished Feb 21 12:48:31 PM PST 24
Peak memory 201316 kb
Host smart-65e0c3f2-9cad-4afc-85a3-1d44ade944a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782295311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2782295311
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.537107581
Short name T258
Test name
Test status
Simulation time 44888014682 ps
CPU time 115.76 seconds
Started Feb 21 12:48:15 PM PST 24
Finished Feb 21 12:50:11 PM PST 24
Peak memory 210076 kb
Host smart-ec559511-6cdb-43d7-acff-130fce9ae047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537107581 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.537107581
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4035654744
Short name T395
Test name
Test status
Simulation time 351962512 ps
CPU time 1.01 seconds
Started Feb 21 12:48:22 PM PST 24
Finished Feb 21 12:48:23 PM PST 24
Peak memory 201244 kb
Host smart-f0c3ff39-8450-4d60-a430-03714037a4fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035654744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4035654744
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.122601841
Short name T279
Test name
Test status
Simulation time 321564197832 ps
CPU time 240.49 seconds
Started Feb 21 12:48:17 PM PST 24
Finished Feb 21 12:52:18 PM PST 24
Peak memory 201504 kb
Host smart-762c2b72-013e-472e-b674-33ecb47cc49e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122601841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.122601841
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1585709692
Short name T11
Test name
Test status
Simulation time 164125039816 ps
CPU time 185.2 seconds
Started Feb 21 12:48:25 PM PST 24
Finished Feb 21 12:51:31 PM PST 24
Peak memory 201512 kb
Host smart-306cc256-6188-4e9f-a5ca-d0391d2264aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585709692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1585709692
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3195089989
Short name T169
Test name
Test status
Simulation time 502176692485 ps
CPU time 580.75 seconds
Started Feb 21 12:48:18 PM PST 24
Finished Feb 21 12:57:59 PM PST 24
Peak memory 201508 kb
Host smart-3808848e-71f5-49bc-b7f2-0b2ee62ef5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195089989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3195089989
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1092001067
Short name T193
Test name
Test status
Simulation time 162821537429 ps
CPU time 66.83 seconds
Started Feb 21 12:48:19 PM PST 24
Finished Feb 21 12:49:26 PM PST 24
Peak memory 201384 kb
Host smart-6b5f2035-afc7-4f97-839a-c10cddcf9d28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092001067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1092001067
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3452123852
Short name T767
Test name
Test status
Simulation time 324550588555 ps
CPU time 697.68 seconds
Started Feb 21 12:48:17 PM PST 24
Finished Feb 21 12:59:55 PM PST 24
Peak memory 201584 kb
Host smart-a6f3be97-0310-4017-9bda-32bcd38509e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452123852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3452123852
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2297134017
Short name T417
Test name
Test status
Simulation time 500846951163 ps
CPU time 1213.3 seconds
Started Feb 21 12:48:18 PM PST 24
Finished Feb 21 01:08:31 PM PST 24
Peak memory 201500 kb
Host smart-b8ad0815-b34e-4d6e-bee0-048f5f845f9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297134017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2297134017
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2773833952
Short name T3
Test name
Test status
Simulation time 332711266493 ps
CPU time 197.98 seconds
Started Feb 21 12:48:19 PM PST 24
Finished Feb 21 12:51:38 PM PST 24
Peak memory 201528 kb
Host smart-834143d3-0b65-4628-a3a8-792fa265e389
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773833952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2773833952
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.455094201
Short name T428
Test name
Test status
Simulation time 320322488076 ps
CPU time 262.23 seconds
Started Feb 21 12:48:21 PM PST 24
Finished Feb 21 12:52:44 PM PST 24
Peak memory 201492 kb
Host smart-12755be9-7af3-4032-b1ad-30dec22937d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455094201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.455094201
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3543694509
Short name T795
Test name
Test status
Simulation time 126145035295 ps
CPU time 721.45 seconds
Started Feb 21 12:48:18 PM PST 24
Finished Feb 21 01:00:20 PM PST 24
Peak memory 201884 kb
Host smart-093b89e4-0877-4b4c-bc33-1f9db1a67c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543694509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3543694509
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.173690968
Short name T418
Test name
Test status
Simulation time 23358151737 ps
CPU time 52.8 seconds
Started Feb 21 12:48:19 PM PST 24
Finished Feb 21 12:49:12 PM PST 24
Peak memory 201284 kb
Host smart-a00988c9-6c2a-42aa-91a8-c952ec78bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173690968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.173690968
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2490206681
Short name T587
Test name
Test status
Simulation time 4134281706 ps
CPU time 5.04 seconds
Started Feb 21 12:48:21 PM PST 24
Finished Feb 21 12:48:27 PM PST 24
Peak memory 201300 kb
Host smart-a2ed0fab-2531-4483-b411-777f884119c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490206681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2490206681
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3350365766
Short name T644
Test name
Test status
Simulation time 5872958320 ps
CPU time 14.22 seconds
Started Feb 21 12:48:22 PM PST 24
Finished Feb 21 12:48:37 PM PST 24
Peak memory 201260 kb
Host smart-744586b1-7a3c-46fa-9695-4fc88299bee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350365766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3350365766
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.719756203
Short name T313
Test name
Test status
Simulation time 366824359866 ps
CPU time 839.84 seconds
Started Feb 21 12:48:23 PM PST 24
Finished Feb 21 01:02:23 PM PST 24
Peak memory 201556 kb
Host smart-0b917126-0375-4c28-a574-58d7a2b33a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719756203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
719756203
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4207129149
Short name T158
Test name
Test status
Simulation time 38533703024 ps
CPU time 83.42 seconds
Started Feb 21 12:48:23 PM PST 24
Finished Feb 21 12:49:46 PM PST 24
Peak memory 209772 kb
Host smart-66397391-b51b-4ed5-8326-b56250bb3b76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207129149 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4207129149
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2722553143
Short name T164
Test name
Test status
Simulation time 435471820 ps
CPU time 0.84 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:47:19 PM PST 24
Peak memory 201040 kb
Host smart-8f58ac68-ba0f-4453-9579-b372cb2e574c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722553143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2722553143
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.4163177662
Short name T183
Test name
Test status
Simulation time 165510311534 ps
CPU time 174.06 seconds
Started Feb 21 12:47:12 PM PST 24
Finished Feb 21 12:50:07 PM PST 24
Peak memory 201444 kb
Host smart-88ee6632-6019-4373-8ad5-2cf1470e152f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163177662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.4163177662
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1567472877
Short name T159
Test name
Test status
Simulation time 496121997193 ps
CPU time 91.14 seconds
Started Feb 21 12:47:11 PM PST 24
Finished Feb 21 12:48:43 PM PST 24
Peak memory 201576 kb
Host smart-bae79082-542b-466b-9e5f-1c05d78c0499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567472877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1567472877
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.456101444
Short name T789
Test name
Test status
Simulation time 322509207968 ps
CPU time 161.11 seconds
Started Feb 21 12:47:04 PM PST 24
Finished Feb 21 12:49:46 PM PST 24
Peak memory 201540 kb
Host smart-53c53507-4edb-4862-9353-c292415df675
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=456101444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.456101444
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2100988542
Short name T205
Test name
Test status
Simulation time 499699453826 ps
CPU time 264.23 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:51:42 PM PST 24
Peak memory 201564 kb
Host smart-3a7f5f1f-83f3-4c17-94b7-d106b293c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100988542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2100988542
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3945648249
Short name T396
Test name
Test status
Simulation time 334296477950 ps
CPU time 723.29 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:59:22 PM PST 24
Peak memory 201552 kb
Host smart-a14c88a0-5f26-4acd-b321-afa150ae9f11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945648249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3945648249
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2052142810
Short name T327
Test name
Test status
Simulation time 331602908411 ps
CPU time 184.11 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:50:22 PM PST 24
Peak memory 201364 kb
Host smart-5c957ad2-ecf9-475a-b58b-f4a825a3e0e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052142810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2052142810
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1969667348
Short name T641
Test name
Test status
Simulation time 487214076677 ps
CPU time 513.13 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:55:53 PM PST 24
Peak memory 201548 kb
Host smart-9adddc97-df05-4f3f-8ddd-f27014cc3861
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969667348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1969667348
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1766101439
Short name T765
Test name
Test status
Simulation time 73590312829 ps
CPU time 431.78 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:54:32 PM PST 24
Peak memory 201952 kb
Host smart-3c9914b8-8761-49cd-bdd5-414cf54df187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766101439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1766101439
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2237148009
Short name T701
Test name
Test status
Simulation time 21628655474 ps
CPU time 47.2 seconds
Started Feb 21 12:47:21 PM PST 24
Finished Feb 21 12:48:08 PM PST 24
Peak memory 201192 kb
Host smart-acbcf71c-2da0-48ce-9b16-6d314b6a6072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237148009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2237148009
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2385097136
Short name T401
Test name
Test status
Simulation time 3174344359 ps
CPU time 8.05 seconds
Started Feb 21 12:47:11 PM PST 24
Finished Feb 21 12:47:20 PM PST 24
Peak memory 201300 kb
Host smart-54f5839b-1710-4bfc-b6f4-1c8a1482f6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385097136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2385097136
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1967107072
Short name T48
Test name
Test status
Simulation time 4212163806 ps
CPU time 5.29 seconds
Started Feb 21 12:47:14 PM PST 24
Finished Feb 21 12:47:20 PM PST 24
Peak memory 216536 kb
Host smart-e34ff030-6274-42c1-9961-da595c0b0bc6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967107072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1967107072
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2500685170
Short name T777
Test name
Test status
Simulation time 5934336059 ps
CPU time 4.26 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:47:22 PM PST 24
Peak memory 201364 kb
Host smart-fc4611ac-5024-4750-af28-fd9bfc0c31b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500685170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2500685170
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3993766040
Short name T745
Test name
Test status
Simulation time 163362989075 ps
CPU time 77.54 seconds
Started Feb 21 12:47:11 PM PST 24
Finished Feb 21 12:48:29 PM PST 24
Peak memory 201468 kb
Host smart-cc745e7b-322a-4ce2-b51f-3133c8c17490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993766040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3993766040
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.613273816
Short name T228
Test name
Test status
Simulation time 386972151652 ps
CPU time 224.72 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:51:04 PM PST 24
Peak memory 218232 kb
Host smart-b14a9eb8-35c4-4c7a-b0d0-8ce9b2833639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613273816 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.613273816
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.958737316
Short name T741
Test name
Test status
Simulation time 475700049 ps
CPU time 0.76 seconds
Started Feb 21 12:48:19 PM PST 24
Finished Feb 21 12:48:20 PM PST 24
Peak memory 201164 kb
Host smart-639d751b-05fb-49d4-8504-73293acd423d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958737316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.958737316
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1914876894
Short name T252
Test name
Test status
Simulation time 497380308297 ps
CPU time 1145.44 seconds
Started Feb 21 12:48:20 PM PST 24
Finished Feb 21 01:07:25 PM PST 24
Peak memory 201572 kb
Host smart-bd2a5fe7-d574-4faa-9f70-3240015797db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914876894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1914876894
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.945268217
Short name T50
Test name
Test status
Simulation time 163671765734 ps
CPU time 365.9 seconds
Started Feb 21 12:48:18 PM PST 24
Finished Feb 21 12:54:25 PM PST 24
Peak memory 201512 kb
Host smart-6b3f1443-7586-42e6-bb11-e631b9394097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945268217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.945268217
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1822628331
Short name T626
Test name
Test status
Simulation time 158141965977 ps
CPU time 363.88 seconds
Started Feb 21 12:48:22 PM PST 24
Finished Feb 21 12:54:26 PM PST 24
Peak memory 201476 kb
Host smart-e3062523-da19-4e02-87d4-1268e0bcefc3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822628331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1822628331
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3428498296
Short name T315
Test name
Test status
Simulation time 316644300294 ps
CPU time 99.11 seconds
Started Feb 21 12:48:21 PM PST 24
Finished Feb 21 12:50:00 PM PST 24
Peak memory 201828 kb
Host smart-77504e11-75bd-49fd-9862-a727c77256ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428498296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3428498296
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1831055248
Short name T93
Test name
Test status
Simulation time 489208091847 ps
CPU time 614.79 seconds
Started Feb 21 12:48:20 PM PST 24
Finished Feb 21 12:58:35 PM PST 24
Peak memory 201532 kb
Host smart-4d0dae96-2b82-4c83-9338-07311024b7d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831055248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1831055248
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.52637771
Short name T160
Test name
Test status
Simulation time 166998523421 ps
CPU time 376.76 seconds
Started Feb 21 12:48:21 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 201416 kb
Host smart-282a912d-d31d-49cd-8ada-7a9cd9750a45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52637771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_w
akeup.52637771
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.556781654
Short name T5
Test name
Test status
Simulation time 498886143592 ps
CPU time 547.05 seconds
Started Feb 21 12:48:20 PM PST 24
Finished Feb 21 12:57:28 PM PST 24
Peak memory 201504 kb
Host smart-8b7567b5-f93e-456a-b3fb-c8200e62d394
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556781654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.556781654
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.949538033
Short name T375
Test name
Test status
Simulation time 105590735134 ps
CPU time 573.66 seconds
Started Feb 21 12:48:20 PM PST 24
Finished Feb 21 12:57:54 PM PST 24
Peak memory 201912 kb
Host smart-714dcc3d-829a-4e4b-8b08-2580152efa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949538033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.949538033
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2227246005
Short name T486
Test name
Test status
Simulation time 39132103919 ps
CPU time 85.4 seconds
Started Feb 21 12:48:20 PM PST 24
Finished Feb 21 12:49:46 PM PST 24
Peak memory 201308 kb
Host smart-a38dee6b-1c43-4867-a747-a71ec074777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227246005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2227246005
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2315611961
Short name T538
Test name
Test status
Simulation time 3732873918 ps
CPU time 3.11 seconds
Started Feb 21 12:48:25 PM PST 24
Finished Feb 21 12:48:29 PM PST 24
Peak memory 201352 kb
Host smart-2bc408b5-ebe4-4f8d-b03f-d0de33457acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315611961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2315611961
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2719728576
Short name T537
Test name
Test status
Simulation time 5882678032 ps
CPU time 6.16 seconds
Started Feb 21 12:48:22 PM PST 24
Finished Feb 21 12:48:29 PM PST 24
Peak memory 201292 kb
Host smart-ca806070-469a-4678-a841-bfb842c374c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719728576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2719728576
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.4154798307
Short name T86
Test name
Test status
Simulation time 314931293 ps
CPU time 0.75 seconds
Started Feb 21 12:48:28 PM PST 24
Finished Feb 21 12:48:29 PM PST 24
Peak memory 201220 kb
Host smart-bdd3d830-fb7c-470c-8e72-5036a96d3c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154798307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.4154798307
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2437743943
Short name T637
Test name
Test status
Simulation time 163804334601 ps
CPU time 94.03 seconds
Started Feb 21 12:48:28 PM PST 24
Finished Feb 21 12:50:02 PM PST 24
Peak memory 201468 kb
Host smart-2aa4e64c-fd95-4d9e-87f5-63e37e9b0cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437743943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2437743943
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.301255733
Short name T265
Test name
Test status
Simulation time 492693888042 ps
CPU time 336.48 seconds
Started Feb 21 12:48:28 PM PST 24
Finished Feb 21 12:54:05 PM PST 24
Peak memory 201516 kb
Host smart-85158259-dca3-493b-8195-f35c926d3a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301255733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.301255733
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1244989173
Short name T447
Test name
Test status
Simulation time 168385816181 ps
CPU time 187.27 seconds
Started Feb 21 12:48:28 PM PST 24
Finished Feb 21 12:51:35 PM PST 24
Peak memory 201544 kb
Host smart-50549003-f2d6-4853-9da5-3b683d5cbabe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244989173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1244989173
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.4117612808
Short name T721
Test name
Test status
Simulation time 319557649485 ps
CPU time 285.2 seconds
Started Feb 21 12:48:20 PM PST 24
Finished Feb 21 12:53:06 PM PST 24
Peak memory 201524 kb
Host smart-1125eeb0-aa57-4fc4-831e-d77d9bc54d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117612808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4117612808
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3731362854
Short name T606
Test name
Test status
Simulation time 322543270250 ps
CPU time 382.56 seconds
Started Feb 21 12:48:19 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 201556 kb
Host smart-349e7b0c-2031-40d4-80a0-e26244c80201
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731362854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3731362854
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2251259873
Short name T520
Test name
Test status
Simulation time 166165046911 ps
CPU time 388.48 seconds
Started Feb 21 12:48:31 PM PST 24
Finished Feb 21 12:55:01 PM PST 24
Peak memory 201540 kb
Host smart-20ba31d6-fe45-4a76-8648-12f38723fadd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251259873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2251259873
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2045974410
Short name T483
Test name
Test status
Simulation time 167387307232 ps
CPU time 387.17 seconds
Started Feb 21 12:48:28 PM PST 24
Finished Feb 21 12:54:56 PM PST 24
Peak memory 201484 kb
Host smart-c665b759-e4c0-4ab0-b2ab-fc9f586911ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045974410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2045974410
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3902358506
Short name T493
Test name
Test status
Simulation time 84798303196 ps
CPU time 399.67 seconds
Started Feb 21 12:48:29 PM PST 24
Finished Feb 21 12:55:09 PM PST 24
Peak memory 201752 kb
Host smart-ab33b676-f5cf-4586-8cab-85bb3a69dfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902358506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3902358506
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2185206094
Short name T457
Test name
Test status
Simulation time 25444575425 ps
CPU time 15.78 seconds
Started Feb 21 12:48:41 PM PST 24
Finished Feb 21 12:48:58 PM PST 24
Peak memory 201308 kb
Host smart-521c21b2-6daa-4fb0-a5c1-97343d8bec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185206094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2185206094
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3488328669
Short name T238
Test name
Test status
Simulation time 5114639195 ps
CPU time 3.42 seconds
Started Feb 21 12:48:27 PM PST 24
Finished Feb 21 12:48:31 PM PST 24
Peak memory 201320 kb
Host smart-915a0375-7650-4312-85c8-adf7ce8c4f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488328669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3488328669
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3892317213
Short name T405
Test name
Test status
Simulation time 5934358794 ps
CPU time 15.21 seconds
Started Feb 21 12:48:23 PM PST 24
Finished Feb 21 12:48:39 PM PST 24
Peak memory 201312 kb
Host smart-e1f2c584-cb6f-459e-837d-133555e847ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892317213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3892317213
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3648877606
Short name T643
Test name
Test status
Simulation time 51289651765 ps
CPU time 72.87 seconds
Started Feb 21 12:48:28 PM PST 24
Finished Feb 21 12:49:42 PM PST 24
Peak memory 210184 kb
Host smart-2da8265f-5f4d-40b0-8bd9-3e5806fd0979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648877606 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3648877606
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3915476429
Short name T625
Test name
Test status
Simulation time 418125017 ps
CPU time 1.13 seconds
Started Feb 21 12:48:39 PM PST 24
Finished Feb 21 12:48:40 PM PST 24
Peak memory 201200 kb
Host smart-ec837fb9-28df-4178-a680-0f0b170c00e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915476429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3915476429
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3627375176
Short name T589
Test name
Test status
Simulation time 331240861512 ps
CPU time 718.42 seconds
Started Feb 21 12:48:43 PM PST 24
Finished Feb 21 01:00:42 PM PST 24
Peak memory 201580 kb
Host smart-de02974e-c52f-43bc-a2c7-e9f48b43c749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627375176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3627375176
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.285034671
Short name T613
Test name
Test status
Simulation time 326680632425 ps
CPU time 193.84 seconds
Started Feb 21 12:48:27 PM PST 24
Finished Feb 21 12:51:42 PM PST 24
Peak memory 201556 kb
Host smart-feb85823-956b-4386-be2b-64c6f74a78df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285034671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.285034671
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.183215540
Short name T435
Test name
Test status
Simulation time 488187268942 ps
CPU time 1164.23 seconds
Started Feb 21 12:48:29 PM PST 24
Finished Feb 21 01:07:53 PM PST 24
Peak memory 201496 kb
Host smart-0bd4ef13-5776-4002-a129-386704c51ded
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=183215540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.183215540
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2537045215
Short name T152
Test name
Test status
Simulation time 496459025966 ps
CPU time 515.81 seconds
Started Feb 21 12:48:42 PM PST 24
Finished Feb 21 12:57:18 PM PST 24
Peak memory 201488 kb
Host smart-8df43b2e-4272-4818-b559-8c7503609542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537045215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2537045215
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.245331146
Short name T666
Test name
Test status
Simulation time 162051712162 ps
CPU time 330.18 seconds
Started Feb 21 12:48:27 PM PST 24
Finished Feb 21 12:53:57 PM PST 24
Peak memory 201492 kb
Host smart-af891b60-e28b-41a0-a7d9-7ce994714729
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=245331146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.245331146
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3403887135
Short name T345
Test name
Test status
Simulation time 171256199148 ps
CPU time 257.55 seconds
Started Feb 21 12:48:28 PM PST 24
Finished Feb 21 12:52:45 PM PST 24
Peak memory 201548 kb
Host smart-48d5ba61-9801-457f-8522-d393c447b855
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403887135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3403887135
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.506974544
Short name T389
Test name
Test status
Simulation time 157694729875 ps
CPU time 46.2 seconds
Started Feb 21 12:48:31 PM PST 24
Finished Feb 21 12:49:18 PM PST 24
Peak memory 201528 kb
Host smart-59f50dc4-1756-4579-a4f4-eaf9fd417010
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506974544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.506974544
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2734165150
Short name T516
Test name
Test status
Simulation time 93184574020 ps
CPU time 494.25 seconds
Started Feb 21 12:48:39 PM PST 24
Finished Feb 21 12:56:53 PM PST 24
Peak memory 201864 kb
Host smart-abcadc28-18d2-4ddd-869e-dad5fc198dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734165150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2734165150
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1765735686
Short name T522
Test name
Test status
Simulation time 31095972356 ps
CPU time 13.01 seconds
Started Feb 21 12:48:27 PM PST 24
Finished Feb 21 12:48:41 PM PST 24
Peak memory 201280 kb
Host smart-e5a459fe-41f5-4fdb-a9f1-01e9303f0b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765735686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1765735686
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2479646703
Short name T218
Test name
Test status
Simulation time 4727653962 ps
CPU time 11.08 seconds
Started Feb 21 12:48:42 PM PST 24
Finished Feb 21 12:48:54 PM PST 24
Peak memory 201320 kb
Host smart-1bb675c3-49da-4cb4-be2a-c00e35873b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479646703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2479646703
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.569593327
Short name T536
Test name
Test status
Simulation time 5621082757 ps
CPU time 3.88 seconds
Started Feb 21 12:48:29 PM PST 24
Finished Feb 21 12:48:33 PM PST 24
Peak memory 201272 kb
Host smart-eb664734-3ca0-4fd1-8493-bc7f232529fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569593327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.569593327
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.937232506
Short name T301
Test name
Test status
Simulation time 419559473933 ps
CPU time 500.51 seconds
Started Feb 21 12:48:37 PM PST 24
Finished Feb 21 12:56:58 PM PST 24
Peak memory 211232 kb
Host smart-27443c7a-641a-45eb-a382-a596d71d2f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937232506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
937232506
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2384957596
Short name T409
Test name
Test status
Simulation time 486247674 ps
CPU time 0.68 seconds
Started Feb 21 12:48:38 PM PST 24
Finished Feb 21 12:48:39 PM PST 24
Peak memory 201240 kb
Host smart-a8363e76-a5fd-451a-b0ec-48ff86f95ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384957596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2384957596
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.822607537
Short name T358
Test name
Test status
Simulation time 497105190026 ps
CPU time 312.56 seconds
Started Feb 21 12:48:35 PM PST 24
Finished Feb 21 12:53:48 PM PST 24
Peak memory 201516 kb
Host smart-fdba071d-a5ff-45dc-99b0-5f8a374a7fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822607537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.822607537
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.807277400
Short name T647
Test name
Test status
Simulation time 163441183512 ps
CPU time 390.95 seconds
Started Feb 21 12:48:38 PM PST 24
Finished Feb 21 12:55:09 PM PST 24
Peak memory 201564 kb
Host smart-78dde6cc-bfa3-444a-9efe-4e7e86ddd72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807277400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.807277400
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2760246617
Short name T792
Test name
Test status
Simulation time 168195249978 ps
CPU time 171.45 seconds
Started Feb 21 12:48:34 PM PST 24
Finished Feb 21 12:51:26 PM PST 24
Peak memory 201556 kb
Host smart-0a3eed47-1b0a-4fb3-9910-b7210559a19f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760246617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2760246617
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1383213399
Short name T186
Test name
Test status
Simulation time 479325705226 ps
CPU time 147.94 seconds
Started Feb 21 12:48:35 PM PST 24
Finished Feb 21 12:51:03 PM PST 24
Peak memory 201532 kb
Host smart-8d80f365-73da-489a-830e-e2ae4e9d17a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383213399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1383213399
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2829611327
Short name T575
Test name
Test status
Simulation time 158916928479 ps
CPU time 92.01 seconds
Started Feb 21 12:48:35 PM PST 24
Finished Feb 21 12:50:07 PM PST 24
Peak memory 201544 kb
Host smart-77f82639-4753-4bbb-8567-2bd665265b34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829611327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2829611327
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1199394114
Short name T189
Test name
Test status
Simulation time 498023057841 ps
CPU time 101.11 seconds
Started Feb 21 12:48:38 PM PST 24
Finished Feb 21 12:50:19 PM PST 24
Peak memory 201488 kb
Host smart-b64c929b-41cc-4cee-a493-7c8568ea11ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199394114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1199394114
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.340094679
Short name T470
Test name
Test status
Simulation time 166105280404 ps
CPU time 203.25 seconds
Started Feb 21 12:48:38 PM PST 24
Finished Feb 21 12:52:02 PM PST 24
Peak memory 201472 kb
Host smart-d6db9733-b342-48ce-a041-b6046c62ff3b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340094679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.340094679
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2735787077
Short name T477
Test name
Test status
Simulation time 67290000796 ps
CPU time 278.85 seconds
Started Feb 21 12:48:38 PM PST 24
Finished Feb 21 12:53:18 PM PST 24
Peak memory 201804 kb
Host smart-569ca243-fccf-4f27-8e76-e60c6849a35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735787077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2735787077
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.885297159
Short name T656
Test name
Test status
Simulation time 22556359364 ps
CPU time 25.22 seconds
Started Feb 21 12:48:39 PM PST 24
Finished Feb 21 12:49:04 PM PST 24
Peak memory 201260 kb
Host smart-e1c54620-cefb-494b-b43c-c13db6f5a529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885297159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.885297159
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3439240039
Short name T212
Test name
Test status
Simulation time 4940352327 ps
CPU time 3.83 seconds
Started Feb 21 12:48:37 PM PST 24
Finished Feb 21 12:48:41 PM PST 24
Peak memory 201360 kb
Host smart-3af7394b-52af-4f6b-b09a-07356ce5c146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439240039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3439240039
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2522999321
Short name T590
Test name
Test status
Simulation time 5691081200 ps
CPU time 4.37 seconds
Started Feb 21 12:48:38 PM PST 24
Finished Feb 21 12:48:42 PM PST 24
Peak memory 201308 kb
Host smart-3ccaaacd-8cee-4431-91e1-3126a57d57dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522999321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2522999321
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1247833112
Short name T433
Test name
Test status
Simulation time 581303634 ps
CPU time 0.73 seconds
Started Feb 21 12:48:54 PM PST 24
Finished Feb 21 12:48:55 PM PST 24
Peak memory 201256 kb
Host smart-834dceca-2853-4a96-9dfc-3607f7ad0d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247833112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1247833112
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3157995888
Short name T264
Test name
Test status
Simulation time 332255420324 ps
CPU time 336.68 seconds
Started Feb 21 12:48:49 PM PST 24
Finished Feb 21 12:54:26 PM PST 24
Peak memory 201436 kb
Host smart-f447b4a5-ecf0-4210-85f7-a45c39559e0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157995888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3157995888
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2098012798
Short name T155
Test name
Test status
Simulation time 484459548069 ps
CPU time 263.12 seconds
Started Feb 21 12:48:49 PM PST 24
Finished Feb 21 12:53:13 PM PST 24
Peak memory 201816 kb
Host smart-8e5bc5b5-e2ed-4e27-b8e2-76e3b5d7413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098012798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2098012798
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1399854039
Short name T412
Test name
Test status
Simulation time 328146037287 ps
CPU time 192.02 seconds
Started Feb 21 12:48:55 PM PST 24
Finished Feb 21 12:52:08 PM PST 24
Peak memory 201540 kb
Host smart-bf462685-9356-450c-b908-5996176e49a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399854039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1399854039
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3101455739
Short name T785
Test name
Test status
Simulation time 492976316892 ps
CPU time 289.04 seconds
Started Feb 21 12:48:49 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 201520 kb
Host smart-b83c46ac-2832-43e1-83f2-ce701c66825d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101455739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3101455739
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1619583707
Short name T384
Test name
Test status
Simulation time 330080608176 ps
CPU time 352.24 seconds
Started Feb 21 12:48:55 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 201488 kb
Host smart-b1b48807-b105-4602-ab92-8abf0c35fb10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619583707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1619583707
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.693844405
Short name T552
Test name
Test status
Simulation time 337288989879 ps
CPU time 197.71 seconds
Started Feb 21 12:48:48 PM PST 24
Finished Feb 21 12:52:07 PM PST 24
Peak memory 201492 kb
Host smart-2de7b619-b108-4a7b-8043-8eb15c427e3f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693844405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.693844405
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1433820037
Short name T200
Test name
Test status
Simulation time 133922512760 ps
CPU time 390.06 seconds
Started Feb 21 12:48:50 PM PST 24
Finished Feb 21 12:55:20 PM PST 24
Peak memory 201792 kb
Host smart-e90684c4-52bf-42db-a4d6-53c2e5de0d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433820037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1433820037
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.637842963
Short name T181
Test name
Test status
Simulation time 28886518597 ps
CPU time 5.04 seconds
Started Feb 21 12:48:49 PM PST 24
Finished Feb 21 12:48:54 PM PST 24
Peak memory 201312 kb
Host smart-eb08e2ec-e29e-4edd-b495-4368bb35dd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637842963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.637842963
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.957308351
Short name T668
Test name
Test status
Simulation time 3989293805 ps
CPU time 9.67 seconds
Started Feb 21 12:48:47 PM PST 24
Finished Feb 21 12:48:58 PM PST 24
Peak memory 201288 kb
Host smart-f158bd04-4033-45f5-9ede-9d6203d3a78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957308351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.957308351
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.388916028
Short name T693
Test name
Test status
Simulation time 5684761147 ps
CPU time 4.09 seconds
Started Feb 21 12:48:48 PM PST 24
Finished Feb 21 12:48:53 PM PST 24
Peak memory 201264 kb
Host smart-60249424-0469-4f56-8c3a-199b6c427223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388916028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.388916028
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3021374756
Short name T90
Test name
Test status
Simulation time 29718856979 ps
CPU time 87.38 seconds
Started Feb 21 12:48:52 PM PST 24
Finished Feb 21 12:50:20 PM PST 24
Peak memory 211124 kb
Host smart-7f85cae2-5a40-49d7-8111-dc3d13fdd7cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021374756 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3021374756
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3426072865
Short name T584
Test name
Test status
Simulation time 397622221 ps
CPU time 0.78 seconds
Started Feb 21 12:48:56 PM PST 24
Finished Feb 21 12:48:57 PM PST 24
Peak memory 201164 kb
Host smart-4a7dfcc2-faf8-4825-80fe-39dd034290c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426072865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3426072865
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2107088453
Short name T58
Test name
Test status
Simulation time 328445734921 ps
CPU time 99.9 seconds
Started Feb 21 12:48:52 PM PST 24
Finished Feb 21 12:50:33 PM PST 24
Peak memory 201528 kb
Host smart-485362f2-904e-4868-8190-c3004afcf8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107088453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2107088453
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.786022400
Short name T430
Test name
Test status
Simulation time 166782222764 ps
CPU time 292.79 seconds
Started Feb 21 12:48:58 PM PST 24
Finished Feb 21 12:53:51 PM PST 24
Peak memory 201464 kb
Host smart-1c6987d2-869c-444c-a482-79a2b919c01c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=786022400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.786022400
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4278199349
Short name T479
Test name
Test status
Simulation time 334184127439 ps
CPU time 724.81 seconds
Started Feb 21 12:48:55 PM PST 24
Finished Feb 21 01:01:00 PM PST 24
Peak memory 201520 kb
Host smart-fb9ccc59-f33d-48fc-b9c7-c2b50b302d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278199349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4278199349
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2686479861
Short name T746
Test name
Test status
Simulation time 165125445503 ps
CPU time 93.54 seconds
Started Feb 21 12:49:01 PM PST 24
Finished Feb 21 12:50:36 PM PST 24
Peak memory 201436 kb
Host smart-af93938d-a7bf-40d9-a386-df2033f79477
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686479861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2686479861
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3928608666
Short name T700
Test name
Test status
Simulation time 484021367948 ps
CPU time 1029.1 seconds
Started Feb 21 12:48:53 PM PST 24
Finished Feb 21 01:06:02 PM PST 24
Peak memory 201460 kb
Host smart-d6225950-1fec-40ea-9e1b-0e8aebc3d754
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928608666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3928608666
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2254933121
Short name T766
Test name
Test status
Simulation time 160282237745 ps
CPU time 182.35 seconds
Started Feb 21 12:48:56 PM PST 24
Finished Feb 21 12:51:59 PM PST 24
Peak memory 201748 kb
Host smart-5fae1b33-53dd-4c9a-a376-e28127f4f81d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254933121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2254933121
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3922715521
Short name T469
Test name
Test status
Simulation time 134807337079 ps
CPU time 700.48 seconds
Started Feb 21 12:48:54 PM PST 24
Finished Feb 21 01:00:35 PM PST 24
Peak memory 201780 kb
Host smart-f1a3ad3e-4e71-46e8-955d-923258860f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922715521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3922715521
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.359173549
Short name T468
Test name
Test status
Simulation time 33924309198 ps
CPU time 29.16 seconds
Started Feb 21 12:48:58 PM PST 24
Finished Feb 21 12:49:27 PM PST 24
Peak memory 201352 kb
Host smart-de846211-07e2-4167-89c6-33308bc81d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359173549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.359173549
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1406957573
Short name T532
Test name
Test status
Simulation time 5556024810 ps
CPU time 15.32 seconds
Started Feb 21 12:48:56 PM PST 24
Finished Feb 21 12:49:12 PM PST 24
Peak memory 201208 kb
Host smart-f22de6f1-ffea-4fce-94ae-63ba544cc818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406957573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1406957573
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1267617644
Short name T87
Test name
Test status
Simulation time 5788021649 ps
CPU time 2.6 seconds
Started Feb 21 12:49:00 PM PST 24
Finished Feb 21 12:49:03 PM PST 24
Peak memory 201304 kb
Host smart-d6b693d7-758e-4a2d-8af7-b637fc871d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267617644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1267617644
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2883829169
Short name T482
Test name
Test status
Simulation time 159109190965 ps
CPU time 77.17 seconds
Started Feb 21 12:48:56 PM PST 24
Finished Feb 21 12:50:13 PM PST 24
Peak memory 201456 kb
Host smart-9de964ec-763c-4b68-86c9-cc564f754bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883829169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2883829169
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1458904607
Short name T34
Test name
Test status
Simulation time 31418544387 ps
CPU time 35.59 seconds
Started Feb 21 12:48:58 PM PST 24
Finished Feb 21 12:49:34 PM PST 24
Peak memory 201604 kb
Host smart-969e3c2f-05bd-41cd-b2c0-0499355970a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458904607 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1458904607
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4040312122
Short name T695
Test name
Test status
Simulation time 284304546 ps
CPU time 0.91 seconds
Started Feb 21 12:49:07 PM PST 24
Finished Feb 21 12:49:09 PM PST 24
Peak memory 201228 kb
Host smart-707edac6-1395-4672-bb0b-3ed24de4164a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040312122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4040312122
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3036920691
Short name T750
Test name
Test status
Simulation time 333642498982 ps
CPU time 793.68 seconds
Started Feb 21 12:49:02 PM PST 24
Finished Feb 21 01:02:17 PM PST 24
Peak memory 201540 kb
Host smart-83361fda-408a-428a-a502-68b969204abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036920691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3036920691
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1331172570
Short name T731
Test name
Test status
Simulation time 495211218139 ps
CPU time 1118.01 seconds
Started Feb 21 12:48:55 PM PST 24
Finished Feb 21 01:07:33 PM PST 24
Peak memory 201556 kb
Host smart-39853384-ef4d-4c79-ba2e-7a6a44412007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331172570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1331172570
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2664339265
Short name T225
Test name
Test status
Simulation time 326424835091 ps
CPU time 200.15 seconds
Started Feb 21 12:48:54 PM PST 24
Finished Feb 21 12:52:14 PM PST 24
Peak memory 201556 kb
Host smart-83a719f4-5209-4215-b5ef-827f9afc9d27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664339265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2664339265
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.918225203
Short name T791
Test name
Test status
Simulation time 484157825643 ps
CPU time 564.21 seconds
Started Feb 21 12:49:02 PM PST 24
Finished Feb 21 12:58:27 PM PST 24
Peak memory 201604 kb
Host smart-1a2ff259-463c-4ced-97d1-6a8e814451ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918225203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.918225203
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.94917152
Short name T634
Test name
Test status
Simulation time 335840400445 ps
CPU time 181.29 seconds
Started Feb 21 12:48:54 PM PST 24
Finished Feb 21 12:51:56 PM PST 24
Peak memory 201496 kb
Host smart-caedde8e-a822-47a8-b02a-496a65f2fd7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=94917152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed
.94917152
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2790508763
Short name T607
Test name
Test status
Simulation time 162060650269 ps
CPU time 98.49 seconds
Started Feb 21 12:48:56 PM PST 24
Finished Feb 21 12:50:35 PM PST 24
Peak memory 201756 kb
Host smart-984dc8f4-50cd-4a47-875e-7ee205d8041a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790508763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2790508763
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3531172020
Short name T554
Test name
Test status
Simulation time 325669374255 ps
CPU time 748.1 seconds
Started Feb 21 12:48:55 PM PST 24
Finished Feb 21 01:01:23 PM PST 24
Peak memory 201440 kb
Host smart-a21318ca-494a-476a-8ea4-91b5a4e60cba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531172020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3531172020
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3806848491
Short name T499
Test name
Test status
Simulation time 95716096315 ps
CPU time 526.14 seconds
Started Feb 21 12:49:03 PM PST 24
Finished Feb 21 12:57:51 PM PST 24
Peak memory 202128 kb
Host smart-a769d230-830d-4237-b070-ea8999de9d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806848491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3806848491
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3073630710
Short name T601
Test name
Test status
Simulation time 41400269535 ps
CPU time 80.37 seconds
Started Feb 21 12:49:03 PM PST 24
Finished Feb 21 12:50:24 PM PST 24
Peak memory 201300 kb
Host smart-d8a1fb56-e971-44d2-b6a5-62f947a03eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073630710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3073630710
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3876429591
Short name T89
Test name
Test status
Simulation time 3377816244 ps
CPU time 8.04 seconds
Started Feb 21 12:49:05 PM PST 24
Finished Feb 21 12:49:15 PM PST 24
Peak memory 201312 kb
Host smart-d1086c55-76ba-4590-a583-0bfded4aeba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876429591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3876429591
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3787147933
Short name T390
Test name
Test status
Simulation time 5839964128 ps
CPU time 7.12 seconds
Started Feb 21 12:48:58 PM PST 24
Finished Feb 21 12:49:05 PM PST 24
Peak memory 201356 kb
Host smart-d1b67aa3-7933-4cc9-95b5-c2b66f01e4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787147933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3787147933
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2163150091
Short name T182
Test name
Test status
Simulation time 172628704579 ps
CPU time 21.63 seconds
Started Feb 21 12:49:11 PM PST 24
Finished Feb 21 12:49:33 PM PST 24
Peak memory 201504 kb
Host smart-43db888f-38a4-440f-9c1a-106a22e47caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163150091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2163150091
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2078912996
Short name T35
Test name
Test status
Simulation time 17811806143 ps
CPU time 67.76 seconds
Started Feb 21 12:49:05 PM PST 24
Finished Feb 21 12:50:14 PM PST 24
Peak memory 210228 kb
Host smart-4cde7722-e663-4e41-8f9f-10d48457ad23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078912996 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2078912996
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2295619886
Short name T661
Test name
Test status
Simulation time 421686957 ps
CPU time 1.08 seconds
Started Feb 21 12:49:12 PM PST 24
Finished Feb 21 12:49:14 PM PST 24
Peak memory 201248 kb
Host smart-309b2ba8-60f8-44e8-94a2-989b72b47878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295619886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2295619886
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1565382423
Short name T617
Test name
Test status
Simulation time 157825178347 ps
CPU time 42.26 seconds
Started Feb 21 12:49:01 PM PST 24
Finished Feb 21 12:49:44 PM PST 24
Peak memory 201556 kb
Host smart-3d4f599d-cc55-432d-bdca-c9dacb689d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565382423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1565382423
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3166341859
Short name T740
Test name
Test status
Simulation time 167623794131 ps
CPU time 399.17 seconds
Started Feb 21 12:49:11 PM PST 24
Finished Feb 21 12:55:51 PM PST 24
Peak memory 201504 kb
Host smart-6fa60438-d524-4756-9b2a-c3c3bdebfea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166341859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3166341859
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3525488094
Short name T654
Test name
Test status
Simulation time 496740894480 ps
CPU time 551.55 seconds
Started Feb 21 12:49:11 PM PST 24
Finished Feb 21 12:58:23 PM PST 24
Peak memory 201468 kb
Host smart-00d66448-1bfa-4c67-b355-ee7b259e9c93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525488094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3525488094
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2613714068
Short name T256
Test name
Test status
Simulation time 490754368539 ps
CPU time 264.51 seconds
Started Feb 21 12:49:08 PM PST 24
Finished Feb 21 12:53:32 PM PST 24
Peak memory 201436 kb
Host smart-40e65cc0-f59d-4466-9395-aef834ea3893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613714068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2613714068
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3556062080
Short name T561
Test name
Test status
Simulation time 163690467686 ps
CPU time 154.83 seconds
Started Feb 21 12:49:03 PM PST 24
Finished Feb 21 12:51:39 PM PST 24
Peak memory 201536 kb
Host smart-23dc307e-1181-4c59-b789-18f5a358c4c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556062080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3556062080
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.403226455
Short name T676
Test name
Test status
Simulation time 162027159687 ps
CPU time 99.05 seconds
Started Feb 21 12:49:05 PM PST 24
Finished Feb 21 12:50:45 PM PST 24
Peak memory 201552 kb
Host smart-2c8be51d-5c22-4525-aa30-9534e1df145e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403226455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.403226455
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.635474848
Short name T24
Test name
Test status
Simulation time 108649471943 ps
CPU time 609.46 seconds
Started Feb 21 12:49:05 PM PST 24
Finished Feb 21 12:59:15 PM PST 24
Peak memory 201824 kb
Host smart-98289576-ea98-438e-aab1-e8bb5edb48e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635474848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.635474848
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.722768390
Short name T161
Test name
Test status
Simulation time 42854182698 ps
CPU time 25.24 seconds
Started Feb 21 12:49:03 PM PST 24
Finished Feb 21 12:49:30 PM PST 24
Peak memory 201308 kb
Host smart-edbf872a-a03a-4d91-b992-61ec9f0c05de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722768390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.722768390
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1421670665
Short name T67
Test name
Test status
Simulation time 4677655472 ps
CPU time 2.09 seconds
Started Feb 21 12:49:11 PM PST 24
Finished Feb 21 12:49:14 PM PST 24
Peak memory 201320 kb
Host smart-e48e6383-2ca8-4086-8c6d-5aa7d062123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421670665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1421670665
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1700291367
Short name T7
Test name
Test status
Simulation time 5999042770 ps
CPU time 7.63 seconds
Started Feb 21 12:49:08 PM PST 24
Finished Feb 21 12:49:15 PM PST 24
Peak memory 201200 kb
Host smart-9d6a20db-0811-4315-8cd6-809dc71bd332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700291367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1700291367
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3116860097
Short name T689
Test name
Test status
Simulation time 404557568857 ps
CPU time 1584.08 seconds
Started Feb 21 12:49:08 PM PST 24
Finished Feb 21 01:15:33 PM PST 24
Peak memory 209964 kb
Host smart-e79d2485-b385-49b2-a352-a1b4a742fd77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116860097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3116860097
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.715249902
Short name T576
Test name
Test status
Simulation time 123134926200 ps
CPU time 320.16 seconds
Started Feb 21 12:49:01 PM PST 24
Finished Feb 21 12:54:22 PM PST 24
Peak memory 210184 kb
Host smart-53ce7141-620a-44c8-bc3a-ebd86b37c300
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715249902 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.715249902
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.840128679
Short name T582
Test name
Test status
Simulation time 299585006 ps
CPU time 0.9 seconds
Started Feb 21 12:49:23 PM PST 24
Finished Feb 21 12:49:25 PM PST 24
Peak memory 201248 kb
Host smart-801da3f0-84f6-4f69-90c7-f890cc86560b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840128679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.840128679
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.669732473
Short name T30
Test name
Test status
Simulation time 166533573077 ps
CPU time 99.96 seconds
Started Feb 21 12:49:09 PM PST 24
Finished Feb 21 12:50:49 PM PST 24
Peak memory 201492 kb
Host smart-e9435916-e9a1-415d-9442-1bcb426f8000
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669732473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.669732473
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.738262857
Short name T216
Test name
Test status
Simulation time 488448035361 ps
CPU time 136.1 seconds
Started Feb 21 12:49:08 PM PST 24
Finished Feb 21 12:51:24 PM PST 24
Peak memory 201504 kb
Host smart-4647ef1b-ad97-4382-b05a-949df939e08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738262857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.738262857
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2668595532
Short name T302
Test name
Test status
Simulation time 496167190040 ps
CPU time 174.28 seconds
Started Feb 21 12:49:15 PM PST 24
Finished Feb 21 12:52:09 PM PST 24
Peak memory 201548 kb
Host smart-bc128e00-d959-4ead-a162-3b8e4b4862c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668595532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2668595532
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1307259759
Short name T12
Test name
Test status
Simulation time 162612831695 ps
CPU time 93.55 seconds
Started Feb 21 12:49:08 PM PST 24
Finished Feb 21 12:50:42 PM PST 24
Peak memory 201536 kb
Host smart-0f9ea27e-0e02-4dcf-ba84-9533449d2553
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307259759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1307259759
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.231132760
Short name T713
Test name
Test status
Simulation time 164355511973 ps
CPU time 404.69 seconds
Started Feb 21 12:49:10 PM PST 24
Finished Feb 21 12:55:55 PM PST 24
Peak memory 201412 kb
Host smart-1d0fb8f1-17c1-4b9d-a3d3-c27234746874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231132760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.231132760
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3820681775
Short name T724
Test name
Test status
Simulation time 329398321449 ps
CPU time 655.93 seconds
Started Feb 21 12:49:09 PM PST 24
Finished Feb 21 01:00:05 PM PST 24
Peak memory 201504 kb
Host smart-e41650ee-b0cd-4cf2-bc95-7809a8d78f7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820681775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3820681775
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.583181621
Short name T788
Test name
Test status
Simulation time 326540505009 ps
CPU time 744.39 seconds
Started Feb 21 12:49:13 PM PST 24
Finished Feb 21 01:01:38 PM PST 24
Peak memory 201504 kb
Host smart-434841ff-9e90-4bac-be5e-96d7443ec648
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583181621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.583181621
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2541870477
Short name T708
Test name
Test status
Simulation time 141457808783 ps
CPU time 475.39 seconds
Started Feb 21 12:49:09 PM PST 24
Finished Feb 21 12:57:05 PM PST 24
Peak memory 201856 kb
Host smart-d3967205-6a1a-41fa-be68-41b31796b8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541870477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2541870477
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3550569839
Short name T165
Test name
Test status
Simulation time 34615536996 ps
CPU time 39.64 seconds
Started Feb 21 12:49:15 PM PST 24
Finished Feb 21 12:49:55 PM PST 24
Peak memory 201304 kb
Host smart-1ef603ea-b3d5-4c42-845a-ced22e39447b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550569839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3550569839
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3255318483
Short name T402
Test name
Test status
Simulation time 3760698675 ps
CPU time 4.38 seconds
Started Feb 21 12:49:09 PM PST 24
Finished Feb 21 12:49:14 PM PST 24
Peak memory 201324 kb
Host smart-33f895ec-225e-4f5e-ac60-0c9ef4466a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255318483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3255318483
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.721770670
Short name T531
Test name
Test status
Simulation time 5856828701 ps
CPU time 7.62 seconds
Started Feb 21 12:49:13 PM PST 24
Finished Feb 21 12:49:21 PM PST 24
Peak memory 201312 kb
Host smart-d3dcad14-ca89-41a0-a445-01c1f00763fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721770670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.721770670
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.464354118
Short name T296
Test name
Test status
Simulation time 207359528648 ps
CPU time 465.06 seconds
Started Feb 21 12:49:25 PM PST 24
Finished Feb 21 12:57:10 PM PST 24
Peak memory 201472 kb
Host smart-8f2bd069-e46d-4ecc-a71a-cf8c6cfba196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464354118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
464354118
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2734957778
Short name T744
Test name
Test status
Simulation time 349980923 ps
CPU time 1.01 seconds
Started Feb 21 12:49:19 PM PST 24
Finished Feb 21 12:49:21 PM PST 24
Peak memory 201208 kb
Host smart-8062b811-fc62-4546-b649-b89d6dbcfcb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734957778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2734957778
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.554829698
Short name T280
Test name
Test status
Simulation time 492376842368 ps
CPU time 585.81 seconds
Started Feb 21 12:49:22 PM PST 24
Finished Feb 21 12:59:09 PM PST 24
Peak memory 201488 kb
Host smart-8b548ca9-8912-401c-93bd-2ff52f429519
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554829698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.554829698
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3330126581
Short name T558
Test name
Test status
Simulation time 162476466620 ps
CPU time 95.28 seconds
Started Feb 21 12:49:20 PM PST 24
Finished Feb 21 12:50:56 PM PST 24
Peak memory 201580 kb
Host smart-63e1a7bc-33a8-4f4e-9ef6-2ab6c4032621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330126581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3330126581
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.227508190
Short name T726
Test name
Test status
Simulation time 327923597457 ps
CPU time 74.18 seconds
Started Feb 21 12:49:23 PM PST 24
Finished Feb 21 12:50:38 PM PST 24
Peak memory 201528 kb
Host smart-aaee3893-f5be-4223-b2ce-b0cd287932f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=227508190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.227508190
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1295182145
Short name T336
Test name
Test status
Simulation time 330762970870 ps
CPU time 719.28 seconds
Started Feb 21 12:49:20 PM PST 24
Finished Feb 21 01:01:21 PM PST 24
Peak memory 201520 kb
Host smart-e0aa5e14-333e-4b52-a5de-536504556c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295182145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1295182145
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.351144252
Short name T96
Test name
Test status
Simulation time 325016887781 ps
CPU time 729.02 seconds
Started Feb 21 12:49:23 PM PST 24
Finished Feb 21 01:01:33 PM PST 24
Peak memory 201440 kb
Host smart-3e65b808-ddd8-467a-9b65-4d622045d128
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=351144252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.351144252
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2922824513
Short name T677
Test name
Test status
Simulation time 161792163971 ps
CPU time 382.94 seconds
Started Feb 21 12:49:20 PM PST 24
Finished Feb 21 12:55:44 PM PST 24
Peak memory 201584 kb
Host smart-d49275d5-de85-4649-9956-3597836be6ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922824513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2922824513
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.909134028
Short name T597
Test name
Test status
Simulation time 162528829647 ps
CPU time 93 seconds
Started Feb 21 12:49:21 PM PST 24
Finished Feb 21 12:50:55 PM PST 24
Peak memory 201564 kb
Host smart-5b34683e-6856-4bfe-877f-5e1b854ac982
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909134028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.909134028
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.851221555
Short name T515
Test name
Test status
Simulation time 23096033387 ps
CPU time 53.25 seconds
Started Feb 21 12:49:20 PM PST 24
Finished Feb 21 12:50:15 PM PST 24
Peak memory 201280 kb
Host smart-9d8896bc-288b-48fa-a205-327473e8dcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851221555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.851221555
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3714696440
Short name T526
Test name
Test status
Simulation time 4405847330 ps
CPU time 1.37 seconds
Started Feb 21 12:49:21 PM PST 24
Finished Feb 21 12:49:23 PM PST 24
Peak memory 201316 kb
Host smart-c2917bfe-61f1-4488-91ca-5294ff2fb9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714696440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3714696440
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2341031444
Short name T386
Test name
Test status
Simulation time 5884499874 ps
CPU time 4.14 seconds
Started Feb 21 12:49:20 PM PST 24
Finished Feb 21 12:49:26 PM PST 24
Peak memory 201284 kb
Host smart-da77dbce-9e94-4b19-8058-b98d7db7e89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341031444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2341031444
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3313038341
Short name T377
Test name
Test status
Simulation time 252035107358 ps
CPU time 511.77 seconds
Started Feb 21 12:49:26 PM PST 24
Finished Feb 21 12:57:58 PM PST 24
Peak memory 201820 kb
Host smart-e1a8019e-1d4a-4073-9ec9-f3824ee2de78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313038341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3313038341
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1907281308
Short name T74
Test name
Test status
Simulation time 47958233963 ps
CPU time 86.17 seconds
Started Feb 21 12:49:23 PM PST 24
Finished Feb 21 12:50:50 PM PST 24
Peak memory 211164 kb
Host smart-070460d6-ff65-4f41-8ba6-222c9dc3b680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907281308 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1907281308
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.701604934
Short name T614
Test name
Test status
Simulation time 343236940 ps
CPU time 1.17 seconds
Started Feb 21 12:47:10 PM PST 24
Finished Feb 21 12:47:11 PM PST 24
Peak memory 201100 kb
Host smart-4e8a5461-3d05-45f1-a1fc-a65b561d0e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701604934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.701604934
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.4056950526
Short name T188
Test name
Test status
Simulation time 495450953510 ps
CPU time 104.38 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:49:04 PM PST 24
Peak memory 201580 kb
Host smart-b457bbfd-ee21-4f7f-bc14-4ccf6c81642d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056950526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.4056950526
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2512323056
Short name T592
Test name
Test status
Simulation time 164902196659 ps
CPU time 82.18 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:48:40 PM PST 24
Peak memory 201600 kb
Host smart-f36c0982-77e0-48ff-a454-b28f3ca02a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512323056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2512323056
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.944181944
Short name T185
Test name
Test status
Simulation time 326622934454 ps
CPU time 168.72 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:50:22 PM PST 24
Peak memory 201620 kb
Host smart-061ac882-aeed-4be2-bbef-93afef7d3de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944181944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.944181944
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2365571327
Short name T706
Test name
Test status
Simulation time 319091176772 ps
CPU time 775.37 seconds
Started Feb 21 12:47:15 PM PST 24
Finished Feb 21 01:00:10 PM PST 24
Peak memory 201480 kb
Host smart-a9ea5892-c1ae-4e10-9f1e-5076a19437cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365571327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2365571327
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3947608306
Short name T517
Test name
Test status
Simulation time 158508480000 ps
CPU time 370.37 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:53:29 PM PST 24
Peak memory 201428 kb
Host smart-896a3f60-84f5-4f5f-8ee0-80ade421f101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947608306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3947608306
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.970326908
Short name T10
Test name
Test status
Simulation time 502499682041 ps
CPU time 389.99 seconds
Started Feb 21 12:47:13 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 201484 kb
Host smart-99d1dd47-1378-4437-abd5-518aac7a4697
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=970326908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.970326908
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1737105931
Short name T173
Test name
Test status
Simulation time 322734203474 ps
CPU time 113.14 seconds
Started Feb 21 12:47:11 PM PST 24
Finished Feb 21 12:49:05 PM PST 24
Peak memory 201584 kb
Host smart-59b0187e-4e6c-4f81-83c7-d585f79406e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737105931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1737105931
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.380884257
Short name T431
Test name
Test status
Simulation time 501567737303 ps
CPU time 596.99 seconds
Started Feb 21 12:47:12 PM PST 24
Finished Feb 21 12:57:10 PM PST 24
Peak memory 201512 kb
Host smart-277bb3c0-95e1-47b8-b551-a1422a751e42
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380884257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.380884257
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1568391429
Short name T675
Test name
Test status
Simulation time 75519784295 ps
CPU time 250.38 seconds
Started Feb 21 12:47:15 PM PST 24
Finished Feb 21 12:51:26 PM PST 24
Peak memory 201828 kb
Host smart-f7e50dd7-0cd6-4192-bafa-058287d42956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568391429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1568391429
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4233098301
Short name T702
Test name
Test status
Simulation time 29578830257 ps
CPU time 66.81 seconds
Started Feb 21 12:47:13 PM PST 24
Finished Feb 21 12:48:20 PM PST 24
Peak memory 201308 kb
Host smart-bdcd3f09-4526-494a-a189-5df2378ea058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233098301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4233098301
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.4248228901
Short name T718
Test name
Test status
Simulation time 2917454294 ps
CPU time 4.12 seconds
Started Feb 21 12:47:05 PM PST 24
Finished Feb 21 12:47:10 PM PST 24
Peak memory 201216 kb
Host smart-955507a2-9c0c-4d9a-90a7-2ba9bd3efd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248228901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.4248228901
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1724891008
Short name T45
Test name
Test status
Simulation time 4091258093 ps
CPU time 10.25 seconds
Started Feb 21 12:47:12 PM PST 24
Finished Feb 21 12:47:23 PM PST 24
Peak memory 216348 kb
Host smart-c843beb8-2bc8-4e06-9874-d7afe9423385
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724891008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1724891008
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3544719663
Short name T759
Test name
Test status
Simulation time 5981582813 ps
CPU time 15.06 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:47:35 PM PST 24
Peak memory 201312 kb
Host smart-5455cd5b-a06d-4d2c-98c9-2d6d2cb8bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544719663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3544719663
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1317262351
Short name T208
Test name
Test status
Simulation time 13997534794 ps
CPU time 40.93 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:47:58 PM PST 24
Peak memory 210144 kb
Host smart-df7ed056-388c-46fb-b7ae-5db631cb0bf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317262351 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1317262351
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1216274219
Short name T698
Test name
Test status
Simulation time 325975505 ps
CPU time 1.4 seconds
Started Feb 21 12:49:30 PM PST 24
Finished Feb 21 12:49:31 PM PST 24
Peak memory 201168 kb
Host smart-11d14901-432b-4e2e-a49a-ecbb6291add4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216274219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1216274219
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3510040332
Short name T282
Test name
Test status
Simulation time 321248248826 ps
CPU time 723.94 seconds
Started Feb 21 12:49:30 PM PST 24
Finished Feb 21 01:01:34 PM PST 24
Peak memory 201444 kb
Host smart-30d080b1-e1e8-4aba-8caf-ef0bd38edd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510040332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3510040332
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.143637062
Short name T253
Test name
Test status
Simulation time 331912340709 ps
CPU time 265.53 seconds
Started Feb 21 12:49:23 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 201544 kb
Host smart-d1672932-15b0-4158-91cb-e824fd0ee24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143637062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.143637062
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2931651104
Short name T761
Test name
Test status
Simulation time 335513020094 ps
CPU time 765.8 seconds
Started Feb 21 12:49:31 PM PST 24
Finished Feb 21 01:02:17 PM PST 24
Peak memory 201568 kb
Host smart-f5ebc0d3-f5ef-4bcb-84b5-db3a85b5c60a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931651104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2931651104
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2340727674
Short name T640
Test name
Test status
Simulation time 332410772193 ps
CPU time 192.41 seconds
Started Feb 21 12:49:20 PM PST 24
Finished Feb 21 12:52:33 PM PST 24
Peak memory 201528 kb
Host smart-e9c2d136-2076-4542-83d7-5e2f52d3a1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340727674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2340727674
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.736845172
Short name T629
Test name
Test status
Simulation time 163532882305 ps
CPU time 405 seconds
Started Feb 21 12:49:19 PM PST 24
Finished Feb 21 12:56:05 PM PST 24
Peak memory 201500 kb
Host smart-816e7140-f76d-428e-a219-d7f535a86c6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=736845172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.736845172
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2212518508
Short name T595
Test name
Test status
Simulation time 488512185282 ps
CPU time 1061.25 seconds
Started Feb 21 12:49:33 PM PST 24
Finished Feb 21 01:07:15 PM PST 24
Peak memory 201504 kb
Host smart-43db5ad0-a2a7-428d-b685-5042ec6f35a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212518508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2212518508
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3779529147
Short name T696
Test name
Test status
Simulation time 60029168634 ps
CPU time 259.65 seconds
Started Feb 21 12:49:29 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 202044 kb
Host smart-a22a3d37-599f-4a4e-9e82-ca4ebbee3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779529147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3779529147
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.759212004
Short name T506
Test name
Test status
Simulation time 30185971163 ps
CPU time 31.85 seconds
Started Feb 21 12:49:29 PM PST 24
Finished Feb 21 12:50:02 PM PST 24
Peak memory 201312 kb
Host smart-470d9370-c1e2-45f3-a547-511c1440c880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759212004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.759212004
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2806391612
Short name T410
Test name
Test status
Simulation time 4004698924 ps
CPU time 3.5 seconds
Started Feb 21 12:49:31 PM PST 24
Finished Feb 21 12:49:35 PM PST 24
Peak memory 201296 kb
Host smart-7dc5083f-6620-4fe8-8ecb-b886e46b40cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806391612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2806391612
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2068250759
Short name T461
Test name
Test status
Simulation time 5729944719 ps
CPU time 3.81 seconds
Started Feb 21 12:49:23 PM PST 24
Finished Feb 21 12:49:27 PM PST 24
Peak memory 201264 kb
Host smart-fce78d4c-e7d8-4239-b7e5-4a810b21f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068250759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2068250759
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.445849358
Short name T261
Test name
Test status
Simulation time 196571754989 ps
CPU time 30.82 seconds
Started Feb 21 12:49:31 PM PST 24
Finished Feb 21 12:50:02 PM PST 24
Peak memory 201504 kb
Host smart-4421c158-a28a-4b15-bfaa-aad6ef9c40b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445849358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
445849358
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1884666560
Short name T177
Test name
Test status
Simulation time 59567780286 ps
CPU time 60.66 seconds
Started Feb 21 12:49:31 PM PST 24
Finished Feb 21 12:50:32 PM PST 24
Peak memory 210144 kb
Host smart-28fa41a6-59e2-4f07-ae30-981a4b123ee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884666560 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1884666560
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2154406581
Short name T772
Test name
Test status
Simulation time 516922248 ps
CPU time 1.68 seconds
Started Feb 21 12:49:41 PM PST 24
Finished Feb 21 12:49:43 PM PST 24
Peak memory 201128 kb
Host smart-180170e8-b088-451c-80d1-a5b1a0e51dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154406581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2154406581
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3572918182
Short name T749
Test name
Test status
Simulation time 166043864332 ps
CPU time 413.75 seconds
Started Feb 21 12:49:30 PM PST 24
Finished Feb 21 12:56:24 PM PST 24
Peak memory 201488 kb
Host smart-786514f5-474c-48ff-9585-7e41066603da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572918182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3572918182
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2680197925
Short name T548
Test name
Test status
Simulation time 161998106042 ps
CPU time 180.74 seconds
Started Feb 21 12:49:29 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 201560 kb
Host smart-dc440b20-03a5-48e3-a251-3d37635cc0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680197925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2680197925
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2365710393
Short name T743
Test name
Test status
Simulation time 495275553902 ps
CPU time 1038.27 seconds
Started Feb 21 12:49:29 PM PST 24
Finished Feb 21 01:06:48 PM PST 24
Peak memory 201396 kb
Host smart-e16b16cf-dc7a-4da5-81ba-3f0190b21311
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365710393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2365710393
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2897714218
Short name T291
Test name
Test status
Simulation time 338091013642 ps
CPU time 387.69 seconds
Started Feb 21 12:49:29 PM PST 24
Finished Feb 21 12:55:57 PM PST 24
Peak memory 201516 kb
Host smart-152a424d-d1f5-456c-aef3-5e55dcff1384
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897714218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2897714218
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1633837318
Short name T163
Test name
Test status
Simulation time 336059499743 ps
CPU time 678.43 seconds
Started Feb 21 12:49:32 PM PST 24
Finished Feb 21 01:00:52 PM PST 24
Peak memory 201504 kb
Host smart-bfd46a46-b301-4eb9-a7f1-852ccd7d6f35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633837318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1633837318
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3043119828
Short name T481
Test name
Test status
Simulation time 75338677997 ps
CPU time 375.59 seconds
Started Feb 21 12:49:37 PM PST 24
Finished Feb 21 12:55:53 PM PST 24
Peak memory 201820 kb
Host smart-f33e177d-a4ad-4b16-afcd-0b8bca467cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043119828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3043119828
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.894884732
Short name T504
Test name
Test status
Simulation time 47953943926 ps
CPU time 102.52 seconds
Started Feb 21 12:49:38 PM PST 24
Finished Feb 21 12:51:21 PM PST 24
Peak memory 201284 kb
Host smart-68775bf1-4205-471b-ac31-fafd630ed059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894884732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.894884732
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3613647120
Short name T615
Test name
Test status
Simulation time 3948068061 ps
CPU time 4.97 seconds
Started Feb 21 12:49:41 PM PST 24
Finished Feb 21 12:49:46 PM PST 24
Peak memory 201292 kb
Host smart-64c0eee9-337d-42ec-ab04-1c1f3574660c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613647120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3613647120
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1428624648
Short name T449
Test name
Test status
Simulation time 5658816578 ps
CPU time 7.6 seconds
Started Feb 21 12:49:28 PM PST 24
Finished Feb 21 12:49:36 PM PST 24
Peak memory 201304 kb
Host smart-c9eca67a-5b39-4399-9baa-8b58f9ec6e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428624648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1428624648
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1617536036
Short name T774
Test name
Test status
Simulation time 207233394909 ps
CPU time 126.56 seconds
Started Feb 21 12:49:36 PM PST 24
Finished Feb 21 12:51:43 PM PST 24
Peak memory 201488 kb
Host smart-2a22003b-4a4f-43e7-b5e8-2456a4250f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617536036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1617536036
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3678344532
Short name T14
Test name
Test status
Simulation time 77069129524 ps
CPU time 191.53 seconds
Started Feb 21 12:49:44 PM PST 24
Finished Feb 21 12:52:56 PM PST 24
Peak memory 210176 kb
Host smart-6cb49d27-5515-4e3c-8d22-2e72343b88e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678344532 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3678344532
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.4254015303
Short name T453
Test name
Test status
Simulation time 305130841 ps
CPU time 1.34 seconds
Started Feb 21 12:49:48 PM PST 24
Finished Feb 21 12:49:50 PM PST 24
Peak memory 201292 kb
Host smart-5f6b81be-c1a8-41be-82c2-e8605bbb5d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254015303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.4254015303
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3032768881
Short name T512
Test name
Test status
Simulation time 161597887119 ps
CPU time 284.19 seconds
Started Feb 21 12:49:45 PM PST 24
Finished Feb 21 12:54:31 PM PST 24
Peak memory 201492 kb
Host smart-b0c0598c-3922-4b0a-958d-8dcfef18edce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032768881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3032768881
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.655004600
Short name T132
Test name
Test status
Simulation time 160384962140 ps
CPU time 350.21 seconds
Started Feb 21 12:49:45 PM PST 24
Finished Feb 21 12:55:36 PM PST 24
Peak memory 201580 kb
Host smart-ff73fbd1-a36a-44b9-b4b5-9ba75e3d339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655004600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.655004600
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.4291561642
Short name T727
Test name
Test status
Simulation time 325141918870 ps
CPU time 718.75 seconds
Started Feb 21 12:49:36 PM PST 24
Finished Feb 21 01:01:35 PM PST 24
Peak memory 201616 kb
Host smart-134f8f71-69aa-4241-8c32-9ecfa0a84afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291561642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.4291561642
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2032197996
Short name T734
Test name
Test status
Simulation time 162703068666 ps
CPU time 355.42 seconds
Started Feb 21 12:49:37 PM PST 24
Finished Feb 21 12:55:33 PM PST 24
Peak memory 201496 kb
Host smart-4963425c-df65-4b77-af4a-a2fab9b43919
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032197996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2032197996
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2947905302
Short name T760
Test name
Test status
Simulation time 164589316928 ps
CPU time 188.8 seconds
Started Feb 21 12:49:40 PM PST 24
Finished Feb 21 12:52:49 PM PST 24
Peak memory 201524 kb
Host smart-74655e11-cfa9-4faa-ae39-9a90e9ea1607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947905302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2947905302
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2384888797
Short name T388
Test name
Test status
Simulation time 161136457169 ps
CPU time 343.03 seconds
Started Feb 21 12:49:42 PM PST 24
Finished Feb 21 12:55:26 PM PST 24
Peak memory 201500 kb
Host smart-e00efc08-b243-4834-8c53-5ace555bac2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384888797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2384888797
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3702030936
Short name T56
Test name
Test status
Simulation time 328156423334 ps
CPU time 700.58 seconds
Started Feb 21 12:49:36 PM PST 24
Finished Feb 21 01:01:17 PM PST 24
Peak memory 201552 kb
Host smart-47036f12-1b1e-4b46-9741-723cd9e4f935
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702030936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3702030936
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1365834662
Short name T141
Test name
Test status
Simulation time 108743719375 ps
CPU time 322.22 seconds
Started Feb 21 12:49:47 PM PST 24
Finished Feb 21 12:55:10 PM PST 24
Peak memory 201908 kb
Host smart-c64951ab-0d5a-4e13-9c93-24cb1a80d61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365834662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1365834662
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1116595435
Short name T407
Test name
Test status
Simulation time 44614652857 ps
CPU time 50.33 seconds
Started Feb 21 12:49:45 PM PST 24
Finished Feb 21 12:50:36 PM PST 24
Peak memory 201224 kb
Host smart-3b2a5ce7-01ab-49f6-94b3-c99475e21a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116595435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1116595435
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3367854502
Short name T441
Test name
Test status
Simulation time 4725223105 ps
CPU time 3.98 seconds
Started Feb 21 12:49:45 PM PST 24
Finished Feb 21 12:49:50 PM PST 24
Peak memory 201292 kb
Host smart-b791566f-03fe-482f-acdd-1738bacbe6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367854502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3367854502
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.395228230
Short name T399
Test name
Test status
Simulation time 5690140113 ps
CPU time 3.91 seconds
Started Feb 21 12:49:43 PM PST 24
Finished Feb 21 12:49:48 PM PST 24
Peak memory 201248 kb
Host smart-3206b082-4833-4e14-af0c-d67747b08e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395228230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.395228230
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4030173920
Short name T466
Test name
Test status
Simulation time 446811062 ps
CPU time 0.82 seconds
Started Feb 21 12:49:54 PM PST 24
Finished Feb 21 12:49:56 PM PST 24
Peak memory 201296 kb
Host smart-c0c0ee57-89e5-44bf-a4e3-3d8f0b1730a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030173920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4030173920
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1029470046
Short name T658
Test name
Test status
Simulation time 166300206531 ps
CPU time 139.79 seconds
Started Feb 21 12:49:45 PM PST 24
Finished Feb 21 12:52:05 PM PST 24
Peak memory 201524 kb
Host smart-08c21485-1a46-4684-9134-bb4a13f1c7ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029470046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1029470046
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2050330733
Short name T351
Test name
Test status
Simulation time 331796551410 ps
CPU time 195.21 seconds
Started Feb 21 12:49:49 PM PST 24
Finished Feb 21 12:53:05 PM PST 24
Peak memory 201604 kb
Host smart-29f49879-69bf-46a1-959a-67491a49cdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050330733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2050330733
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1166327713
Short name T527
Test name
Test status
Simulation time 166362661104 ps
CPU time 384.38 seconds
Started Feb 21 12:49:44 PM PST 24
Finished Feb 21 12:56:09 PM PST 24
Peak memory 201488 kb
Host smart-4e6e0231-901a-4233-b651-1765d12b2182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166327713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1166327713
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.237362918
Short name T562
Test name
Test status
Simulation time 165689589509 ps
CPU time 188.57 seconds
Started Feb 21 12:49:48 PM PST 24
Finished Feb 21 12:52:57 PM PST 24
Peak memory 201492 kb
Host smart-630dc38b-3ae8-43a9-a4da-c8056edbbd8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=237362918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.237362918
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.64117699
Short name T295
Test name
Test status
Simulation time 485477184989 ps
CPU time 270.34 seconds
Started Feb 21 12:49:50 PM PST 24
Finished Feb 21 12:54:21 PM PST 24
Peak memory 201760 kb
Host smart-c761dfec-79b4-4ce9-9857-36037144b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64117699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.64117699
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3511631063
Short name T773
Test name
Test status
Simulation time 169705363785 ps
CPU time 375.97 seconds
Started Feb 21 12:49:48 PM PST 24
Finished Feb 21 12:56:05 PM PST 24
Peak memory 201604 kb
Host smart-99f9f2a2-06d5-4ed5-93f4-750ffe2d7073
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511631063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3511631063
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1508885623
Short name T221
Test name
Test status
Simulation time 169785108541 ps
CPU time 370.86 seconds
Started Feb 21 12:49:44 PM PST 24
Finished Feb 21 12:55:56 PM PST 24
Peak memory 201556 kb
Host smart-bf583f80-286e-4eb0-8bbc-f947c5cd9bf4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508885623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1508885623
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1224773097
Short name T17
Test name
Test status
Simulation time 333917929358 ps
CPU time 814.81 seconds
Started Feb 21 12:49:44 PM PST 24
Finished Feb 21 01:03:19 PM PST 24
Peak memory 201472 kb
Host smart-69dfe0a2-7535-4a6b-be62-4ef035d59239
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224773097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1224773097
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3081877690
Short name T758
Test name
Test status
Simulation time 127823613932 ps
CPU time 636.09 seconds
Started Feb 21 12:49:51 PM PST 24
Finished Feb 21 01:00:29 PM PST 24
Peak memory 201884 kb
Host smart-66b8baf4-b04b-430c-9a14-34e6c0bdc4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081877690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3081877690
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.667692244
Short name T541
Test name
Test status
Simulation time 40471703711 ps
CPU time 90.98 seconds
Started Feb 21 12:49:53 PM PST 24
Finished Feb 21 12:51:25 PM PST 24
Peak memory 201300 kb
Host smart-1a8df9b1-cbb5-447a-a38c-bef814566101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667692244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.667692244
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4086629168
Short name T754
Test name
Test status
Simulation time 4988638612 ps
CPU time 3.19 seconds
Started Feb 21 12:49:51 PM PST 24
Finished Feb 21 12:49:56 PM PST 24
Peak memory 201200 kb
Host smart-60932c81-e08f-4883-b6fc-70dbd58dee16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086629168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4086629168
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1800900084
Short name T201
Test name
Test status
Simulation time 5820980848 ps
CPU time 7.78 seconds
Started Feb 21 12:49:46 PM PST 24
Finished Feb 21 12:49:55 PM PST 24
Peak memory 201256 kb
Host smart-d63cf75e-f715-41b6-a46b-c9be2db1d824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800900084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1800900084
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.266674059
Short name T620
Test name
Test status
Simulation time 4583876742 ps
CPU time 9.42 seconds
Started Feb 21 12:49:52 PM PST 24
Finished Feb 21 12:50:03 PM PST 24
Peak memory 201200 kb
Host smart-542c3e58-78e2-40b0-b8c6-306882567683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266674059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
266674059
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.4094226937
Short name T465
Test name
Test status
Simulation time 328101351 ps
CPU time 1.39 seconds
Started Feb 21 12:50:01 PM PST 24
Finished Feb 21 12:50:03 PM PST 24
Peak memory 201216 kb
Host smart-511fc438-be91-4e31-a2c0-16c3d3e29192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094226937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.4094226937
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3994591477
Short name T338
Test name
Test status
Simulation time 323782022317 ps
CPU time 665.57 seconds
Started Feb 21 12:49:51 PM PST 24
Finished Feb 21 01:00:58 PM PST 24
Peak memory 201528 kb
Host smart-87d775c6-0c0d-4831-9c59-649f14c6a2f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994591477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3994591477
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1070218143
Short name T354
Test name
Test status
Simulation time 171452047106 ps
CPU time 399.91 seconds
Started Feb 21 12:49:53 PM PST 24
Finished Feb 21 12:56:34 PM PST 24
Peak memory 201512 kb
Host smart-c38c47be-8036-4d5b-bc9b-2581c6ca2257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070218143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1070218143
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.4067238827
Short name T145
Test name
Test status
Simulation time 327358253726 ps
CPU time 759.6 seconds
Started Feb 21 12:49:51 PM PST 24
Finished Feb 21 01:02:32 PM PST 24
Peak memory 201448 kb
Host smart-e52f5ba3-2918-44d5-86c3-08a04f6fb66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067238827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4067238827
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.346655819
Short name T680
Test name
Test status
Simulation time 507662742304 ps
CPU time 1214.23 seconds
Started Feb 21 12:49:53 PM PST 24
Finished Feb 21 01:10:08 PM PST 24
Peak memory 201524 kb
Host smart-ced96380-67ad-4610-a1e5-04c7f9833bbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=346655819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.346655819
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3907291111
Short name T349
Test name
Test status
Simulation time 326454922242 ps
CPU time 557.05 seconds
Started Feb 21 12:49:52 PM PST 24
Finished Feb 21 12:59:10 PM PST 24
Peak memory 201580 kb
Host smart-a13a01cf-8a9a-4609-967d-e6c6a1bc842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907291111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3907291111
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2849946428
Short name T529
Test name
Test status
Simulation time 332439155256 ps
CPU time 570.05 seconds
Started Feb 21 12:49:53 PM PST 24
Finished Feb 21 12:59:24 PM PST 24
Peak memory 201492 kb
Host smart-43edfc84-8362-4204-a1ac-627a727aa86f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849946428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2849946428
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3929376727
Short name T557
Test name
Test status
Simulation time 330163806060 ps
CPU time 484.15 seconds
Started Feb 21 12:49:51 PM PST 24
Finished Feb 21 12:57:56 PM PST 24
Peak memory 201564 kb
Host smart-28a629c3-81b7-43d0-9add-994e21e2959e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929376727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3929376727
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1537848965
Short name T633
Test name
Test status
Simulation time 162956718011 ps
CPU time 392.99 seconds
Started Feb 21 12:49:53 PM PST 24
Finished Feb 21 12:56:27 PM PST 24
Peak memory 201556 kb
Host smart-e1a601e9-50a1-42ce-9db2-06a7cf2bbb0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537848965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1537848965
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2580017788
Short name T732
Test name
Test status
Simulation time 118027594838 ps
CPU time 705.2 seconds
Started Feb 21 12:49:54 PM PST 24
Finished Feb 21 01:01:40 PM PST 24
Peak memory 201932 kb
Host smart-572fc22d-a1f0-4cf9-b885-e164c6c02c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580017788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2580017788
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1688901805
Short name T416
Test name
Test status
Simulation time 26639406928 ps
CPU time 14.85 seconds
Started Feb 21 12:49:51 PM PST 24
Finished Feb 21 12:50:07 PM PST 24
Peak memory 201308 kb
Host smart-f7776608-8757-467e-ba9f-0c056325b464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688901805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1688901805
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3882952139
Short name T391
Test name
Test status
Simulation time 3891026571 ps
CPU time 9.37 seconds
Started Feb 21 12:49:51 PM PST 24
Finished Feb 21 12:50:02 PM PST 24
Peak memory 201220 kb
Host smart-bd875072-5c93-46b4-ba55-a7259fd53d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882952139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3882952139
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.204453851
Short name T551
Test name
Test status
Simulation time 5515281215 ps
CPU time 6.86 seconds
Started Feb 21 12:49:52 PM PST 24
Finished Feb 21 12:49:59 PM PST 24
Peak memory 201268 kb
Host smart-9badcb1a-5e6c-46f9-b660-f5870f5414d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204453851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.204453851
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.310072666
Short name T747
Test name
Test status
Simulation time 131428622872 ps
CPU time 297.34 seconds
Started Feb 21 12:50:02 PM PST 24
Finished Feb 21 12:55:00 PM PST 24
Peak memory 201920 kb
Host smart-2a8b3af7-6295-4cd4-a008-25bd70bb3251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310072666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
310072666
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1576079010
Short name T578
Test name
Test status
Simulation time 51382829825 ps
CPU time 120.54 seconds
Started Feb 21 12:50:00 PM PST 24
Finished Feb 21 12:52:01 PM PST 24
Peak memory 210196 kb
Host smart-e19d708b-b445-4b43-ba65-8d9775bf3226
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576079010 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1576079010
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.130817075
Short name T15
Test name
Test status
Simulation time 422835470 ps
CPU time 0.84 seconds
Started Feb 21 12:50:14 PM PST 24
Finished Feb 21 12:50:17 PM PST 24
Peak memory 201252 kb
Host smart-a2e8d95c-dc07-4969-953b-1f8f16208fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130817075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.130817075
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3500928378
Short name T341
Test name
Test status
Simulation time 162456861178 ps
CPU time 368.83 seconds
Started Feb 21 12:50:00 PM PST 24
Finished Feb 21 12:56:10 PM PST 24
Peak memory 201492 kb
Host smart-f91ffe58-9cc4-4f85-b2fe-140774486bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500928378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3500928378
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3242407007
Short name T57
Test name
Test status
Simulation time 166726094081 ps
CPU time 34.17 seconds
Started Feb 21 12:50:02 PM PST 24
Finished Feb 21 12:50:37 PM PST 24
Peak memory 201384 kb
Host smart-f2b204ca-d406-4f7f-ac98-5bb1a5f302e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242407007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3242407007
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2437480454
Short name T739
Test name
Test status
Simulation time 488389939060 ps
CPU time 969.69 seconds
Started Feb 21 12:50:00 PM PST 24
Finished Feb 21 01:06:10 PM PST 24
Peak memory 201580 kb
Host smart-e6b19cfb-591e-4bec-962e-67c0539d8a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437480454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2437480454
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3904792542
Short name T671
Test name
Test status
Simulation time 162208490835 ps
CPU time 103.71 seconds
Started Feb 21 12:50:00 PM PST 24
Finished Feb 21 12:51:45 PM PST 24
Peak memory 201708 kb
Host smart-d8d9f9f9-881c-4da3-ab78-fe1ebb261ebc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904792542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3904792542
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.603392240
Short name T577
Test name
Test status
Simulation time 330636494354 ps
CPU time 388.1 seconds
Started Feb 21 12:50:01 PM PST 24
Finished Feb 21 12:56:30 PM PST 24
Peak memory 201504 kb
Host smart-304337d0-52e4-404f-bd63-17b0f7c62463
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603392240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.603392240
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.159072489
Short name T440
Test name
Test status
Simulation time 331717215915 ps
CPU time 732.29 seconds
Started Feb 21 12:50:03 PM PST 24
Finished Feb 21 01:02:16 PM PST 24
Peak memory 201552 kb
Host smart-b87119bf-1a8c-4d85-a0db-f85428966a57
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159072489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.159072489
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3726570913
Short name T168
Test name
Test status
Simulation time 92681047614 ps
CPU time 336.09 seconds
Started Feb 21 12:50:00 PM PST 24
Finished Feb 21 12:55:37 PM PST 24
Peak memory 201924 kb
Host smart-73c8715f-ca6f-40f1-83b6-e5d23ae1aeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726570913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3726570913
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1970345245
Short name T492
Test name
Test status
Simulation time 39737065418 ps
CPU time 23.22 seconds
Started Feb 21 12:50:04 PM PST 24
Finished Feb 21 12:50:27 PM PST 24
Peak memory 201352 kb
Host smart-e8c8fd24-2af5-47f6-9495-8be3be994bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970345245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1970345245
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.750446241
Short name T54
Test name
Test status
Simulation time 5167923480 ps
CPU time 6.98 seconds
Started Feb 21 12:50:00 PM PST 24
Finished Feb 21 12:50:07 PM PST 24
Peak memory 201228 kb
Host smart-dc258230-8df7-4fe7-945a-5b9a59838b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750446241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.750446241
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1888203462
Short name T618
Test name
Test status
Simulation time 6022607661 ps
CPU time 14.72 seconds
Started Feb 21 12:50:00 PM PST 24
Finished Feb 21 12:50:15 PM PST 24
Peak memory 201276 kb
Host smart-8e05bdb0-3d99-488a-8c1b-3d9d4f607675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888203462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1888203462
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.868912182
Short name T240
Test name
Test status
Simulation time 167558325962 ps
CPU time 104.14 seconds
Started Feb 21 12:50:01 PM PST 24
Finished Feb 21 12:51:46 PM PST 24
Peak memory 201732 kb
Host smart-6bbe5047-fa5d-48d1-9e70-b01262c1a5f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868912182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
868912182
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1522654940
Short name T361
Test name
Test status
Simulation time 217888902134 ps
CPU time 231.83 seconds
Started Feb 21 12:50:00 PM PST 24
Finished Feb 21 12:53:53 PM PST 24
Peak memory 210208 kb
Host smart-dbb3fc23-34a6-4163-ae7a-2d8bac933fdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522654940 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1522654940
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.49257444
Short name T82
Test name
Test status
Simulation time 330192294 ps
CPU time 0.8 seconds
Started Feb 21 12:50:25 PM PST 24
Finished Feb 21 12:50:26 PM PST 24
Peak memory 201224 kb
Host smart-1bd659f8-5557-44c7-b2ca-e22a9b3a0715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49257444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.49257444
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.4102431057
Short name T547
Test name
Test status
Simulation time 323735918123 ps
CPU time 763.67 seconds
Started Feb 21 12:50:10 PM PST 24
Finished Feb 21 01:02:54 PM PST 24
Peak memory 201588 kb
Host smart-8f846fe4-d1a8-41ff-8c33-9e5a7559ef69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102431057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.4102431057
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2081988695
Short name T653
Test name
Test status
Simulation time 170319717596 ps
CPU time 93.79 seconds
Started Feb 21 12:50:11 PM PST 24
Finished Feb 21 12:51:45 PM PST 24
Peak memory 201552 kb
Host smart-f1192885-af4a-48e1-87ce-8105182feb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081988695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2081988695
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1820518805
Short name T778
Test name
Test status
Simulation time 330904252153 ps
CPU time 746.2 seconds
Started Feb 21 12:50:12 PM PST 24
Finished Feb 21 01:02:38 PM PST 24
Peak memory 201416 kb
Host smart-a089b874-9ebd-47e7-b6d5-d54e0eb16ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820518805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1820518805
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1420426675
Short name T437
Test name
Test status
Simulation time 336747255326 ps
CPU time 194.13 seconds
Started Feb 21 12:50:14 PM PST 24
Finished Feb 21 12:53:29 PM PST 24
Peak memory 201492 kb
Host smart-bc680ea7-ead4-40e6-a4d2-0545a959c193
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420426675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1420426675
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3134919409
Short name T147
Test name
Test status
Simulation time 492032744299 ps
CPU time 1085.5 seconds
Started Feb 21 12:50:13 PM PST 24
Finished Feb 21 01:08:19 PM PST 24
Peak memory 201556 kb
Host smart-76c44103-1d80-49c7-b3ac-69af2267ee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134919409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3134919409
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.667915579
Short name T223
Test name
Test status
Simulation time 340503632650 ps
CPU time 210.74 seconds
Started Feb 21 12:50:13 PM PST 24
Finished Feb 21 12:53:44 PM PST 24
Peak memory 201488 kb
Host smart-574712c1-fb1c-47d1-b7f4-c75051d41576
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=667915579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.667915579
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.598082309
Short name T156
Test name
Test status
Simulation time 504833294478 ps
CPU time 293.73 seconds
Started Feb 21 12:50:16 PM PST 24
Finished Feb 21 12:55:11 PM PST 24
Peak memory 201544 kb
Host smart-6fdbb645-98f4-41df-add5-580d2485d763
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598082309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.598082309
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1894645220
Short name T432
Test name
Test status
Simulation time 161692701750 ps
CPU time 59.78 seconds
Started Feb 21 12:50:09 PM PST 24
Finished Feb 21 12:51:09 PM PST 24
Peak memory 201508 kb
Host smart-83bf6bb8-aace-4c05-8822-2da6ae7caaaf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894645220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1894645220
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2850973631
Short name T70
Test name
Test status
Simulation time 113353362116 ps
CPU time 434.76 seconds
Started Feb 21 12:50:14 PM PST 24
Finished Feb 21 12:57:31 PM PST 24
Peak memory 201864 kb
Host smart-df4de90c-aefc-4473-85e1-bc2d16219d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850973631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2850973631
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.818737264
Short name T771
Test name
Test status
Simulation time 23778307509 ps
CPU time 55.05 seconds
Started Feb 21 12:50:10 PM PST 24
Finished Feb 21 12:51:06 PM PST 24
Peak memory 201304 kb
Host smart-eea1ad01-aa53-49a5-b9c8-30f288cad3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818737264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.818737264
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.765333402
Short name T25
Test name
Test status
Simulation time 3733320343 ps
CPU time 9.33 seconds
Started Feb 21 12:50:09 PM PST 24
Finished Feb 21 12:50:19 PM PST 24
Peak memory 201324 kb
Host smart-166bf036-84b5-4dc7-830e-f4285be474be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765333402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.765333402
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1986129441
Short name T651
Test name
Test status
Simulation time 5740688151 ps
CPU time 14.6 seconds
Started Feb 21 12:50:13 PM PST 24
Finished Feb 21 12:50:29 PM PST 24
Peak memory 201324 kb
Host smart-b8f03fe3-1c2e-4c3b-9904-7dc03c8fce72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986129441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1986129441
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2161750142
Short name T174
Test name
Test status
Simulation time 205402121872 ps
CPU time 508.57 seconds
Started Feb 21 12:50:26 PM PST 24
Finished Feb 21 12:58:55 PM PST 24
Peak memory 201512 kb
Host smart-64982c8a-e8fa-41a0-853c-e6720384e863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161750142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2161750142
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2184911318
Short name T76
Test name
Test status
Simulation time 374454926714 ps
CPU time 111.7 seconds
Started Feb 21 12:50:11 PM PST 24
Finished Feb 21 12:52:03 PM PST 24
Peak memory 210108 kb
Host smart-8c683211-e337-4356-979e-c85715d343bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184911318 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2184911318
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2616058022
Short name T652
Test name
Test status
Simulation time 497690039 ps
CPU time 1.82 seconds
Started Feb 21 12:50:36 PM PST 24
Finished Feb 21 12:50:38 PM PST 24
Peak memory 201152 kb
Host smart-c4db11aa-8cbc-4b79-bae5-82fb276e7b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616058022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2616058022
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.22619925
Short name T33
Test name
Test status
Simulation time 335148214341 ps
CPU time 88.96 seconds
Started Feb 21 12:50:25 PM PST 24
Finished Feb 21 12:51:54 PM PST 24
Peak memory 201364 kb
Host smart-acb9526e-353a-46ce-b283-41b8e8273ac4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22619925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gatin
g.22619925
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3130643472
Short name T339
Test name
Test status
Simulation time 162821149626 ps
CPU time 102.25 seconds
Started Feb 21 12:50:26 PM PST 24
Finished Feb 21 12:52:09 PM PST 24
Peak memory 201448 kb
Host smart-388c5745-4920-4b4b-bc49-f07452c01ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130643472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3130643472
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2149716427
Short name T565
Test name
Test status
Simulation time 166595121871 ps
CPU time 358 seconds
Started Feb 21 12:50:26 PM PST 24
Finished Feb 21 12:56:24 PM PST 24
Peak memory 201520 kb
Host smart-107e7acb-4876-4b22-a17b-5baa0b7478b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149716427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2149716427
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1279668366
Short name T608
Test name
Test status
Simulation time 334297881716 ps
CPU time 633.8 seconds
Started Feb 21 12:50:26 PM PST 24
Finished Feb 21 01:01:01 PM PST 24
Peak memory 201488 kb
Host smart-4392ac1c-a01a-4373-b6f9-768a498be6c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279668366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1279668366
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3117222714
Short name T294
Test name
Test status
Simulation time 164218305446 ps
CPU time 99.05 seconds
Started Feb 21 12:50:25 PM PST 24
Finished Feb 21 12:52:05 PM PST 24
Peak memory 201524 kb
Host smart-30eb0d39-ac36-49d4-a42a-c33370d12a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117222714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3117222714
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4081034337
Short name T784
Test name
Test status
Simulation time 163171204800 ps
CPU time 56.92 seconds
Started Feb 21 12:50:26 PM PST 24
Finished Feb 21 12:51:23 PM PST 24
Peak memory 201496 kb
Host smart-635ab6c9-3e01-4575-a0fe-2277c66e5b59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081034337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4081034337
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.4092444605
Short name T679
Test name
Test status
Simulation time 496411958202 ps
CPU time 308.72 seconds
Started Feb 21 12:50:25 PM PST 24
Finished Feb 21 12:55:34 PM PST 24
Peak memory 201484 kb
Host smart-8865e000-6d8c-4cde-b348-ccd094616b82
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092444605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.4092444605
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.331459482
Short name T463
Test name
Test status
Simulation time 23234162357 ps
CPU time 13.71 seconds
Started Feb 21 12:50:26 PM PST 24
Finished Feb 21 12:50:41 PM PST 24
Peak memory 201520 kb
Host smart-77847c37-d95f-41af-a267-0f937c31798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331459482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.331459482
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3971506341
Short name T420
Test name
Test status
Simulation time 3317616889 ps
CPU time 8.58 seconds
Started Feb 21 12:50:24 PM PST 24
Finished Feb 21 12:50:33 PM PST 24
Peak memory 201308 kb
Host smart-0778daa8-e8ff-450e-9148-20e69b80f1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971506341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3971506341
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2850438116
Short name T494
Test name
Test status
Simulation time 5709680479 ps
CPU time 2.86 seconds
Started Feb 21 12:50:24 PM PST 24
Finished Feb 21 12:50:28 PM PST 24
Peak memory 201284 kb
Host smart-9f14e00b-8668-4aac-9226-44dc33a81dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850438116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2850438116
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2042887122
Short name T738
Test name
Test status
Simulation time 62107906572 ps
CPU time 357.87 seconds
Started Feb 21 12:50:31 PM PST 24
Finished Feb 21 12:56:30 PM PST 24
Peak memory 201904 kb
Host smart-b3e61ebb-e93b-4d86-9ec4-122a69c72733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042887122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2042887122
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2725528740
Short name T310
Test name
Test status
Simulation time 83614781655 ps
CPU time 143.37 seconds
Started Feb 21 12:50:33 PM PST 24
Finished Feb 21 12:52:57 PM PST 24
Peak memory 201568 kb
Host smart-f2e1ebda-e5ea-46b0-bfd7-a7787432e8da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725528740 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2725528740
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1856696892
Short name T71
Test name
Test status
Simulation time 440237599 ps
CPU time 1.63 seconds
Started Feb 21 12:50:32 PM PST 24
Finished Feb 21 12:50:34 PM PST 24
Peak memory 201252 kb
Host smart-c65ad39a-65b7-4661-a8e3-1cd8f7471960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856696892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1856696892
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2676427220
Short name T197
Test name
Test status
Simulation time 318680240550 ps
CPU time 48.9 seconds
Started Feb 21 12:50:33 PM PST 24
Finished Feb 21 12:51:22 PM PST 24
Peak memory 201612 kb
Host smart-ba103996-fe70-47ad-919b-f7f98976f3cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676427220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2676427220
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2232703171
Short name T262
Test name
Test status
Simulation time 158559573500 ps
CPU time 192.87 seconds
Started Feb 21 12:50:31 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 201568 kb
Host smart-24c3ead9-0c9a-4b46-8ea6-5890d638e5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232703171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2232703171
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3788520521
Short name T150
Test name
Test status
Simulation time 166844105115 ps
CPU time 61 seconds
Started Feb 21 12:50:33 PM PST 24
Finished Feb 21 12:51:34 PM PST 24
Peak memory 201556 kb
Host smart-46d1a902-f54d-444c-ac80-d6549b4dce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788520521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3788520521
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4288796889
Short name T670
Test name
Test status
Simulation time 502548812504 ps
CPU time 284.19 seconds
Started Feb 21 12:50:31 PM PST 24
Finished Feb 21 12:55:16 PM PST 24
Peak memory 201396 kb
Host smart-ac62266d-52b3-45cb-a907-be7f1ca0ffb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288796889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4288796889
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3019679164
Short name T187
Test name
Test status
Simulation time 324484595331 ps
CPU time 741.9 seconds
Started Feb 21 12:50:34 PM PST 24
Finished Feb 21 01:02:56 PM PST 24
Peak memory 201568 kb
Host smart-eace2fd0-b412-4c9d-96c4-586ab23406a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019679164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3019679164
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2834197223
Short name T688
Test name
Test status
Simulation time 499253992853 ps
CPU time 287.49 seconds
Started Feb 21 12:50:31 PM PST 24
Finished Feb 21 12:55:19 PM PST 24
Peak memory 201556 kb
Host smart-975567ef-5d64-448b-869c-4f47966f40d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834197223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2834197223
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.63198458
Short name T755
Test name
Test status
Simulation time 169511735423 ps
CPU time 361.77 seconds
Started Feb 21 12:50:33 PM PST 24
Finished Feb 21 12:56:35 PM PST 24
Peak memory 201520 kb
Host smart-3af90f7f-42d3-4f88-b038-7938dc1fe2f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63198458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_w
akeup.63198458
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2883886809
Short name T728
Test name
Test status
Simulation time 496961417991 ps
CPU time 605.54 seconds
Started Feb 21 12:50:31 PM PST 24
Finished Feb 21 01:00:37 PM PST 24
Peak memory 201532 kb
Host smart-278ddf0c-ac0d-44d1-b118-967ded33e9dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883886809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2883886809
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1371120042
Short name T770
Test name
Test status
Simulation time 121673747018 ps
CPU time 436.92 seconds
Started Feb 21 12:50:35 PM PST 24
Finished Feb 21 12:57:52 PM PST 24
Peak memory 200988 kb
Host smart-c14800bc-18ef-4abb-a1bd-67024ab32b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371120042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1371120042
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3594347970
Short name T763
Test name
Test status
Simulation time 44597756797 ps
CPU time 50.96 seconds
Started Feb 21 12:50:32 PM PST 24
Finished Feb 21 12:51:23 PM PST 24
Peak memory 201284 kb
Host smart-afab8000-a5f3-42b5-ac13-21df0454986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594347970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3594347970
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2899271473
Short name T525
Test name
Test status
Simulation time 4280072340 ps
CPU time 10.94 seconds
Started Feb 21 12:50:32 PM PST 24
Finished Feb 21 12:50:43 PM PST 24
Peak memory 201196 kb
Host smart-2952a9a1-4165-4eed-9f07-dd3e3e65811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899271473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2899271473
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.4189163691
Short name T780
Test name
Test status
Simulation time 5778742910 ps
CPU time 14.68 seconds
Started Feb 21 12:50:36 PM PST 24
Finished Feb 21 12:50:50 PM PST 24
Peak memory 201224 kb
Host smart-8e9c0a5b-231b-43da-85a7-24cd6bd311e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189163691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.4189163691
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1905990617
Short name T710
Test name
Test status
Simulation time 171328827846 ps
CPU time 389.82 seconds
Started Feb 21 12:50:32 PM PST 24
Finished Feb 21 12:57:03 PM PST 24
Peak memory 201572 kb
Host smart-b7605adf-5b8f-4aa1-877f-194969177e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905990617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1905990617
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1499193347
Short name T63
Test name
Test status
Simulation time 236320269833 ps
CPU time 187.31 seconds
Started Feb 21 12:50:32 PM PST 24
Finished Feb 21 12:53:40 PM PST 24
Peak memory 210016 kb
Host smart-ecf469cf-9114-4305-801c-65245713ea8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499193347 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1499193347
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1592854842
Short name T456
Test name
Test status
Simulation time 328993547 ps
CPU time 1.3 seconds
Started Feb 21 12:50:43 PM PST 24
Finished Feb 21 12:50:45 PM PST 24
Peak memory 201260 kb
Host smart-33d26d6a-6436-4288-a916-ee48db946803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592854842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1592854842
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.167299456
Short name T167
Test name
Test status
Simulation time 168556192908 ps
CPU time 230.52 seconds
Started Feb 21 12:50:49 PM PST 24
Finished Feb 21 12:54:40 PM PST 24
Peak memory 201392 kb
Host smart-1c865ace-8778-4ce6-95ec-e2aba15348e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167299456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.167299456
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.637941643
Short name T194
Test name
Test status
Simulation time 334481993424 ps
CPU time 411.56 seconds
Started Feb 21 12:50:44 PM PST 24
Finished Feb 21 12:57:36 PM PST 24
Peak memory 201512 kb
Host smart-21b81de1-2347-4c82-9342-76fec7d2b678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637941643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.637941643
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2868556745
Short name T510
Test name
Test status
Simulation time 491580108342 ps
CPU time 1056.76 seconds
Started Feb 21 12:50:46 PM PST 24
Finished Feb 21 01:08:24 PM PST 24
Peak memory 201464 kb
Host smart-c61e2afe-c3af-4edd-a6cc-45ca5a9e3f16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868556745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2868556745
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2128420773
Short name T570
Test name
Test status
Simulation time 324244843939 ps
CPU time 331.53 seconds
Started Feb 21 12:50:32 PM PST 24
Finished Feb 21 12:56:04 PM PST 24
Peak memory 201552 kb
Host smart-80a3bddd-7895-4051-a012-4bd0db531140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128420773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2128420773
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3841038577
Short name T686
Test name
Test status
Simulation time 329042855558 ps
CPU time 362.68 seconds
Started Feb 21 12:50:43 PM PST 24
Finished Feb 21 12:56:47 PM PST 24
Peak memory 201492 kb
Host smart-48816051-cad6-4830-9beb-2b8892ad117a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841038577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3841038577
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2427737739
Short name T267
Test name
Test status
Simulation time 162857827329 ps
CPU time 45.97 seconds
Started Feb 21 12:50:43 PM PST 24
Finished Feb 21 12:51:29 PM PST 24
Peak memory 201504 kb
Host smart-8e5da810-c415-4a8a-a4f3-466b32a464ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427737739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2427737739
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2898370744
Short name T166
Test name
Test status
Simulation time 163373596457 ps
CPU time 89.22 seconds
Started Feb 21 12:50:47 PM PST 24
Finished Feb 21 12:52:17 PM PST 24
Peak memory 201720 kb
Host smart-b7ce6606-6196-4b06-84ed-1483965f4c45
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898370744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2898370744
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2887460992
Short name T497
Test name
Test status
Simulation time 112244266978 ps
CPU time 407.66 seconds
Started Feb 21 12:50:44 PM PST 24
Finished Feb 21 12:57:33 PM PST 24
Peak memory 201816 kb
Host smart-e04ff403-62ad-403b-bc36-70c35f29cb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887460992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2887460992
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3174830651
Short name T398
Test name
Test status
Simulation time 29172147932 ps
CPU time 63.5 seconds
Started Feb 21 12:50:47 PM PST 24
Finished Feb 21 12:51:52 PM PST 24
Peak memory 201192 kb
Host smart-37bc72f5-cfef-42d2-a5a9-046cb9823ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174830651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3174830651
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3877233727
Short name T545
Test name
Test status
Simulation time 4257781531 ps
CPU time 11.25 seconds
Started Feb 21 12:50:47 PM PST 24
Finished Feb 21 12:50:59 PM PST 24
Peak memory 201220 kb
Host smart-ce1d9263-bfa0-45ba-9338-ad0c6ede2fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877233727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3877233727
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3409737504
Short name T612
Test name
Test status
Simulation time 5584381884 ps
CPU time 14.12 seconds
Started Feb 21 12:50:35 PM PST 24
Finished Feb 21 12:50:49 PM PST 24
Peak memory 200220 kb
Host smart-aecfb316-277a-4562-8c59-0c48fb80f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409737504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3409737504
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3091134045
Short name T659
Test name
Test status
Simulation time 455434223 ps
CPU time 0.87 seconds
Started Feb 21 12:47:15 PM PST 24
Finished Feb 21 12:47:16 PM PST 24
Peak memory 201204 kb
Host smart-c3bb6956-5614-4579-8bfd-ab0cc1a3a0d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091134045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3091134045
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2612257829
Short name T330
Test name
Test status
Simulation time 167445958204 ps
CPU time 61.12 seconds
Started Feb 21 12:47:14 PM PST 24
Finished Feb 21 12:48:15 PM PST 24
Peak memory 201548 kb
Host smart-122d122f-153d-4173-8177-f7b660158132
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612257829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2612257829
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3890553595
Short name T697
Test name
Test status
Simulation time 164062045002 ps
CPU time 329.93 seconds
Started Feb 21 12:47:13 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 201544 kb
Host smart-0c715c84-9202-4b4a-925c-f55305d25205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890553595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3890553595
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3538991260
Short name T783
Test name
Test status
Simulation time 495011349112 ps
CPU time 529.97 seconds
Started Feb 21 12:47:07 PM PST 24
Finished Feb 21 12:55:58 PM PST 24
Peak memory 201500 kb
Host smart-c59fa6c5-4295-4179-876e-b81a49340047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538991260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3538991260
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.152785593
Short name T387
Test name
Test status
Simulation time 160423342867 ps
CPU time 349.62 seconds
Started Feb 21 12:47:13 PM PST 24
Finished Feb 21 12:53:03 PM PST 24
Peak memory 201492 kb
Host smart-5ac3833f-8afa-4329-be0c-a97fe97d735b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=152785593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.152785593
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.4074815416
Short name T151
Test name
Test status
Simulation time 158914304208 ps
CPU time 95.64 seconds
Started Feb 21 12:47:15 PM PST 24
Finished Feb 21 12:48:51 PM PST 24
Peak memory 201544 kb
Host smart-d5c75c0d-f18b-4821-bfcc-d3e4e00ee39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074815416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.4074815416
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2995206240
Short name T84
Test name
Test status
Simulation time 494682835777 ps
CPU time 291.02 seconds
Started Feb 21 12:47:32 PM PST 24
Finished Feb 21 12:52:25 PM PST 24
Peak memory 201552 kb
Host smart-9aa2bad1-4ca8-43de-8bd1-2f94b72af39d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995206240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2995206240
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.611168026
Short name T320
Test name
Test status
Simulation time 332950090528 ps
CPU time 443.81 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 201536 kb
Host smart-c302baa1-ad74-4c33-a765-42b96a0d32c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611168026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.611168026
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1302304791
Short name T411
Test name
Test status
Simulation time 496765214457 ps
CPU time 597.55 seconds
Started Feb 21 12:47:16 PM PST 24
Finished Feb 21 12:57:14 PM PST 24
Peak memory 201484 kb
Host smart-d8762469-8299-4c8d-9adb-89ca401de566
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302304791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1302304791
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4161621462
Short name T769
Test name
Test status
Simulation time 136895725853 ps
CPU time 499.24 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:55:37 PM PST 24
Peak memory 201768 kb
Host smart-daab0ad1-6cd8-4565-bde7-d2c62e4427fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161621462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4161621462
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1704778436
Short name T667
Test name
Test status
Simulation time 40875791218 ps
CPU time 97.63 seconds
Started Feb 21 12:47:13 PM PST 24
Finished Feb 21 12:48:51 PM PST 24
Peak memory 201288 kb
Host smart-477d5ed6-6dbd-46c8-8034-00a852313859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704778436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1704778436
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2740178251
Short name T436
Test name
Test status
Simulation time 3709267984 ps
CPU time 2.58 seconds
Started Feb 21 12:47:13 PM PST 24
Finished Feb 21 12:47:16 PM PST 24
Peak memory 201304 kb
Host smart-e515ad00-b072-40fe-b7c8-6817d403935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740178251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2740178251
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2594118254
Short name T571
Test name
Test status
Simulation time 5817751122 ps
CPU time 1.93 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:47:21 PM PST 24
Peak memory 201324 kb
Host smart-854b4fb4-7585-4423-9109-a9d5ae040c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594118254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2594118254
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3090472397
Short name T276
Test name
Test status
Simulation time 339464643353 ps
CPU time 70.43 seconds
Started Feb 21 12:47:09 PM PST 24
Finished Feb 21 12:48:20 PM PST 24
Peak memory 201368 kb
Host smart-802b09ca-1785-45cb-bd22-d2684af84343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090472397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3090472397
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1284518215
Short name T422
Test name
Test status
Simulation time 507928519 ps
CPU time 1.79 seconds
Started Feb 21 12:47:24 PM PST 24
Finished Feb 21 12:47:28 PM PST 24
Peak memory 201224 kb
Host smart-8e16cc69-d717-468a-8b91-9e652a965248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284518215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1284518215
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1497785282
Short name T722
Test name
Test status
Simulation time 163837209819 ps
CPU time 175.17 seconds
Started Feb 21 12:47:22 PM PST 24
Finished Feb 21 12:50:18 PM PST 24
Peak memory 201472 kb
Host smart-f2774d84-7f8c-48bf-8cfb-1d6ca64b3e1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497785282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1497785282
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3771842806
Short name T756
Test name
Test status
Simulation time 481000419744 ps
CPU time 1046.41 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 01:04:45 PM PST 24
Peak memory 201572 kb
Host smart-2529e851-1d01-4f38-9d4b-065448bd5a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771842806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3771842806
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3483838715
Short name T237
Test name
Test status
Simulation time 327762057274 ps
CPU time 361.28 seconds
Started Feb 21 12:47:15 PM PST 24
Finished Feb 21 12:53:16 PM PST 24
Peak memory 201580 kb
Host smart-9df69f56-af3f-42c5-97ec-062fe1421166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483838715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3483838715
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3957750377
Short name T655
Test name
Test status
Simulation time 327263776529 ps
CPU time 626.87 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:57:46 PM PST 24
Peak memory 201476 kb
Host smart-6be6a11b-5a72-436d-b157-6d04cb3ecfcf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957750377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3957750377
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3634799155
Short name T55
Test name
Test status
Simulation time 487791511955 ps
CPU time 291.79 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:52:10 PM PST 24
Peak memory 201472 kb
Host smart-3253982f-5ef1-4fcf-a460-3571769f0cf1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634799155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3634799155
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1698986967
Short name T312
Test name
Test status
Simulation time 502090059082 ps
CPU time 291.19 seconds
Started Feb 21 12:47:04 PM PST 24
Finished Feb 21 12:51:56 PM PST 24
Peak memory 201476 kb
Host smart-98db1974-019f-411b-b7a5-629dc23e976b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698986967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1698986967
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.617284339
Short name T511
Test name
Test status
Simulation time 168821481640 ps
CPU time 399.03 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:53:57 PM PST 24
Peak memory 201476 kb
Host smart-b174cb16-4c03-4182-af3c-b4ce69722311
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617284339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.617284339
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.915090882
Short name T664
Test name
Test status
Simulation time 25251493517 ps
CPU time 54.64 seconds
Started Feb 21 12:47:23 PM PST 24
Finished Feb 21 12:48:19 PM PST 24
Peak memory 201208 kb
Host smart-e2ca5b73-a63a-44a5-961f-988c3e813946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915090882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.915090882
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2756259709
Short name T683
Test name
Test status
Simulation time 4634787590 ps
CPU time 10.83 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:47:30 PM PST 24
Peak memory 201296 kb
Host smart-7792437f-64f5-49ba-a2a0-0e7b594591bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756259709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2756259709
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1558410522
Short name T501
Test name
Test status
Simulation time 5940340544 ps
CPU time 7.18 seconds
Started Feb 21 12:47:15 PM PST 24
Finished Feb 21 12:47:23 PM PST 24
Peak memory 201288 kb
Host smart-070cb515-d428-476b-afa9-4fe53dcc171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558410522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1558410522
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2205297289
Short name T347
Test name
Test status
Simulation time 532246146310 ps
CPU time 299.19 seconds
Started Feb 21 12:47:25 PM PST 24
Finished Feb 21 12:52:26 PM PST 24
Peak memory 201488 kb
Host smart-e235674c-b2bd-4056-a8a2-19b652b0ce75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205297289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2205297289
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3984791290
Short name T231
Test name
Test status
Simulation time 198866222940 ps
CPU time 119.42 seconds
Started Feb 21 12:47:24 PM PST 24
Finished Feb 21 12:49:24 PM PST 24
Peak memory 209772 kb
Host smart-a12a5eb4-16a9-42f2-9118-6d24aaa1a22a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984791290 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3984791290
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3601259976
Short name T509
Test name
Test status
Simulation time 352141297 ps
CPU time 1.4 seconds
Started Feb 21 12:47:37 PM PST 24
Finished Feb 21 12:47:39 PM PST 24
Peak memory 201232 kb
Host smart-b201905a-aa99-44ce-b7bc-7d042f3f7c0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601259976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3601259976
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2767770155
Short name T202
Test name
Test status
Simulation time 161376410385 ps
CPU time 411.93 seconds
Started Feb 21 12:47:20 PM PST 24
Finished Feb 21 12:54:13 PM PST 24
Peak memory 201564 kb
Host smart-9525d3ce-f25c-469d-a4d0-b7d067c5f0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767770155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2767770155
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3784148995
Short name T319
Test name
Test status
Simulation time 329401225294 ps
CPU time 728.26 seconds
Started Feb 21 12:47:29 PM PST 24
Finished Feb 21 12:59:38 PM PST 24
Peak memory 201516 kb
Host smart-4e996134-b7ee-4e8e-93e3-6ac716b3226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784148995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3784148995
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.4248166318
Short name T630
Test name
Test status
Simulation time 325712265976 ps
CPU time 116.72 seconds
Started Feb 21 12:47:15 PM PST 24
Finished Feb 21 12:49:12 PM PST 24
Peak memory 201432 kb
Host smart-004da6e5-f988-4d37-9cdb-02f39b723cdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248166318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.4248166318
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.604347460
Short name T757
Test name
Test status
Simulation time 162671872054 ps
CPU time 27.27 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:47:45 PM PST 24
Peak memory 201464 kb
Host smart-719a3e0c-cead-44b9-b000-752a24f46fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604347460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.604347460
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3004686139
Short name T385
Test name
Test status
Simulation time 163012796682 ps
CPU time 102.55 seconds
Started Feb 21 12:47:24 PM PST 24
Finished Feb 21 12:49:08 PM PST 24
Peak memory 201472 kb
Host smart-2b05bde8-a783-4c3a-ad8a-49e73bcad8e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004686139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3004686139
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2754761667
Short name T342
Test name
Test status
Simulation time 340706184782 ps
CPU time 809.72 seconds
Started Feb 21 12:47:13 PM PST 24
Finished Feb 21 01:00:43 PM PST 24
Peak memory 201432 kb
Host smart-2e77e0fc-5542-434b-a6a2-bdaf439193e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754761667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2754761667
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4268122303
Short name T480
Test name
Test status
Simulation time 328295908149 ps
CPU time 762.73 seconds
Started Feb 21 12:47:22 PM PST 24
Finished Feb 21 01:00:05 PM PST 24
Peak memory 201568 kb
Host smart-c0fe6b21-0982-4da7-8322-366f4852777d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268122303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4268122303
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1898613455
Short name T370
Test name
Test status
Simulation time 76653104333 ps
CPU time 250.43 seconds
Started Feb 21 12:47:22 PM PST 24
Finished Feb 21 12:51:33 PM PST 24
Peak memory 201704 kb
Host smart-54afa758-29ac-474b-a931-4c366c0fcf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898613455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1898613455
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1771111494
Short name T779
Test name
Test status
Simulation time 26813313578 ps
CPU time 14.12 seconds
Started Feb 21 12:47:23 PM PST 24
Finished Feb 21 12:47:39 PM PST 24
Peak memory 201524 kb
Host smart-6ebcd57a-9e76-4b70-93de-a1a88588a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771111494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1771111494
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2666989082
Short name T464
Test name
Test status
Simulation time 3540766005 ps
CPU time 9.16 seconds
Started Feb 21 12:47:21 PM PST 24
Finished Feb 21 12:47:30 PM PST 24
Peak memory 201316 kb
Host smart-98a4cc72-494f-4b16-8fad-7a5dd458cad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666989082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2666989082
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4093509068
Short name T2
Test name
Test status
Simulation time 6262024874 ps
CPU time 4.94 seconds
Started Feb 21 12:47:25 PM PST 24
Finished Feb 21 12:47:31 PM PST 24
Peak memory 201240 kb
Host smart-f0838593-09f3-4a35-9ac9-dde2065c312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093509068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4093509068
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1967817539
Short name T540
Test name
Test status
Simulation time 12661073499 ps
CPU time 15.96 seconds
Started Feb 21 12:47:12 PM PST 24
Finished Feb 21 12:47:29 PM PST 24
Peak memory 201480 kb
Host smart-e0da64d5-a183-43d2-bd47-a35fb1eb13bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967817539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1967817539
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3013133932
Short name T162
Test name
Test status
Simulation time 28549174469 ps
CPU time 41.22 seconds
Started Feb 21 12:47:25 PM PST 24
Finished Feb 21 12:48:08 PM PST 24
Peak memory 201524 kb
Host smart-2c0c1210-9f41-43c5-a3f6-a027bf14e262
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013133932 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3013133932
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2592737677
Short name T691
Test name
Test status
Simulation time 320405941 ps
CPU time 1.18 seconds
Started Feb 21 12:47:14 PM PST 24
Finished Feb 21 12:47:16 PM PST 24
Peak memory 201244 kb
Host smart-2874f030-241c-4c77-8982-87a406f63661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592737677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2592737677
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.4127129945
Short name T287
Test name
Test status
Simulation time 222711592659 ps
CPU time 134 seconds
Started Feb 21 12:47:25 PM PST 24
Finished Feb 21 12:49:41 PM PST 24
Peak memory 201828 kb
Host smart-bec59697-8c48-4bf1-a0cb-b7ef2c61a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127129945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4127129945
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.367472402
Short name T350
Test name
Test status
Simulation time 328895032755 ps
CPU time 388.25 seconds
Started Feb 21 12:47:24 PM PST 24
Finished Feb 21 12:53:54 PM PST 24
Peak memory 201580 kb
Host smart-5f8ead8b-f41f-4a7b-8872-bab1e04df4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367472402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.367472402
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3991349780
Short name T678
Test name
Test status
Simulation time 493376001876 ps
CPU time 119.02 seconds
Started Feb 21 12:47:15 PM PST 24
Finished Feb 21 12:49:15 PM PST 24
Peak memory 201380 kb
Host smart-b563c694-04e9-411c-8681-591c2d1f8b25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991349780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3991349780
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1709231332
Short name T581
Test name
Test status
Simulation time 332742139064 ps
CPU time 791.82 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 01:00:31 PM PST 24
Peak memory 201492 kb
Host smart-cc451ba6-4660-462b-ba31-04399ac6cced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709231332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1709231332
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3466835096
Short name T669
Test name
Test status
Simulation time 164322460883 ps
CPU time 117.26 seconds
Started Feb 21 12:47:22 PM PST 24
Finished Feb 21 12:49:20 PM PST 24
Peak memory 201468 kb
Host smart-ef3935d8-bb35-4039-9582-ef9c8ea84f0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466835096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3466835096
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.385372703
Short name T334
Test name
Test status
Simulation time 336743671617 ps
CPU time 775.59 seconds
Started Feb 21 12:47:23 PM PST 24
Finished Feb 21 01:00:20 PM PST 24
Peak memory 201528 kb
Host smart-4d70cdbc-3ecc-44b1-9d91-549417afa75c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385372703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.385372703
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2360221656
Short name T458
Test name
Test status
Simulation time 337652198483 ps
CPU time 780.73 seconds
Started Feb 21 12:47:35 PM PST 24
Finished Feb 21 01:00:36 PM PST 24
Peak memory 201496 kb
Host smart-d4be3d71-6516-4db7-9f2a-f6ba0f618033
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360221656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2360221656
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2502865263
Short name T572
Test name
Test status
Simulation time 65165360705 ps
CPU time 305.19 seconds
Started Feb 21 12:47:20 PM PST 24
Finished Feb 21 12:52:26 PM PST 24
Peak memory 201720 kb
Host smart-d42c798d-a3b6-4fe3-895d-631f18c66662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502865263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2502865263
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.92381038
Short name T88
Test name
Test status
Simulation time 36298583494 ps
CPU time 5.23 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:47:25 PM PST 24
Peak memory 201296 kb
Host smart-35db8e13-83fd-4f2a-89fa-6e4bc9878560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92381038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.92381038
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.617962880
Short name T672
Test name
Test status
Simulation time 4466571721 ps
CPU time 11.33 seconds
Started Feb 21 12:47:29 PM PST 24
Finished Feb 21 12:47:41 PM PST 24
Peak memory 201200 kb
Host smart-ce3cffe6-45d4-46b0-8994-5e30fdf5f99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617962880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.617962880
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2826387013
Short name T523
Test name
Test status
Simulation time 5776148434 ps
CPU time 14.78 seconds
Started Feb 21 12:47:22 PM PST 24
Finished Feb 21 12:47:38 PM PST 24
Peak memory 201240 kb
Host smart-1ef607a1-d969-4fba-a351-9696a2110032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826387013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2826387013
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.4088533445
Short name T690
Test name
Test status
Simulation time 8580452399 ps
CPU time 15.79 seconds
Started Feb 21 12:47:23 PM PST 24
Finished Feb 21 12:47:40 PM PST 24
Peak memory 201288 kb
Host smart-16303a72-8db8-4c40-b5dc-9a894707f35a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088533445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
4088533445
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3433748598
Short name T787
Test name
Test status
Simulation time 491477667 ps
CPU time 1.86 seconds
Started Feb 21 12:47:26 PM PST 24
Finished Feb 21 12:47:29 PM PST 24
Peak memory 201196 kb
Host smart-beffa883-7d52-4fa0-a4b4-5b3c6a385e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433748598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3433748598
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.186341642
Short name T178
Test name
Test status
Simulation time 170848928115 ps
CPU time 24.82 seconds
Started Feb 21 12:47:26 PM PST 24
Finished Feb 21 12:47:52 PM PST 24
Peak memory 201480 kb
Host smart-bd598846-1c85-4281-ae13-3e30ac2adb1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186341642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.186341642
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3736535300
Short name T266
Test name
Test status
Simulation time 495271242070 ps
CPU time 1107.9 seconds
Started Feb 21 12:47:29 PM PST 24
Finished Feb 21 01:05:58 PM PST 24
Peak memory 201540 kb
Host smart-aeff7d0b-07d2-4627-97e5-9101e257c845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736535300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3736535300
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1208665875
Short name T317
Test name
Test status
Simulation time 330578405554 ps
CPU time 381.7 seconds
Started Feb 21 12:47:19 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 201552 kb
Host smart-090c1542-ddbe-4784-b728-3ee12a363fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208665875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1208665875
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3127435997
Short name T392
Test name
Test status
Simulation time 164608257336 ps
CPU time 360.74 seconds
Started Feb 21 12:47:25 PM PST 24
Finished Feb 21 12:53:27 PM PST 24
Peak memory 201396 kb
Host smart-c9376882-2718-4bca-a9e5-f85e197be168
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127435997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3127435997
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.81707905
Short name T300
Test name
Test status
Simulation time 164703947421 ps
CPU time 346.86 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 201468 kb
Host smart-9adc569d-2c03-4ba5-adb1-90de94317f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81707905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.81707905
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4169923432
Short name T685
Test name
Test status
Simulation time 489448119505 ps
CPU time 1104.24 seconds
Started Feb 21 12:47:25 PM PST 24
Finished Feb 21 01:05:51 PM PST 24
Peak memory 201588 kb
Host smart-8cfc5e0b-e119-4f92-9a85-96374e40bd7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169923432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.4169923432
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.538916283
Short name T269
Test name
Test status
Simulation time 165878863897 ps
CPU time 404.29 seconds
Started Feb 21 12:47:24 PM PST 24
Finished Feb 21 12:54:10 PM PST 24
Peak memory 201604 kb
Host smart-c7fa5c5b-55ab-4174-8ad0-7cf083fbe572
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538916283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.538916283
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2869596613
Short name T490
Test name
Test status
Simulation time 488060171065 ps
CPU time 1117.34 seconds
Started Feb 21 12:47:17 PM PST 24
Finished Feb 21 01:05:55 PM PST 24
Peak memory 201424 kb
Host smart-c60801c4-ecdd-47a6-8ab4-fac78b963935
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869596613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2869596613
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3012367997
Short name T20
Test name
Test status
Simulation time 141110293191 ps
CPU time 689.52 seconds
Started Feb 21 12:47:18 PM PST 24
Finished Feb 21 12:58:48 PM PST 24
Peak memory 201816 kb
Host smart-84412abe-a5a8-481b-82ac-ab62d723af6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012367997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3012367997
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1535241221
Short name T674
Test name
Test status
Simulation time 46504212931 ps
CPU time 28.79 seconds
Started Feb 21 12:47:22 PM PST 24
Finished Feb 21 12:47:52 PM PST 24
Peak memory 201280 kb
Host smart-df740aab-d254-468b-83f6-0350a88ef4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535241221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1535241221
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4083355808
Short name T627
Test name
Test status
Simulation time 4403791043 ps
CPU time 10.87 seconds
Started Feb 21 12:47:30 PM PST 24
Finished Feb 21 12:47:42 PM PST 24
Peak memory 201340 kb
Host smart-55e99783-736a-4ba2-bf82-fa35eccb93dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083355808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4083355808
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.239750599
Short name T236
Test name
Test status
Simulation time 6060090349 ps
CPU time 15.41 seconds
Started Feb 21 12:47:16 PM PST 24
Finished Feb 21 12:47:31 PM PST 24
Peak memory 201300 kb
Host smart-461e583b-647d-468e-94ea-4e788aa3beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239750599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.239750599
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.915565387
Short name T143
Test name
Test status
Simulation time 57016961998 ps
CPU time 80.63 seconds
Started Feb 21 12:47:26 PM PST 24
Finished Feb 21 12:48:48 PM PST 24
Peak memory 210140 kb
Host smart-efe61aab-8f77-447a-b65c-239145d78047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915565387 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.915565387
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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