Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6534	1			T2	38		T4	20		T9	20
testmodes[AdcCtrlTestmodeNormal]	5017	1			T1	3		T2	52		T3	3
testmodes[AdcCtrlTestmodeLowpower]	5244	1			T2	60		T4	1		T5	13
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3589	1			T2	10		T4	19		T9	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1603	1			T2	16		T16	15		T22	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1226	1			T2	12		T4	1		T16	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1601	1			T2	16		T16	12		T22	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1813	1			T1	2		T2	15		T3	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1267	1			T2	21		T16	15		T12	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1233	1			T2	12		T16	24		T18	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1268	1			T2	20		T5	1		T16	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2505	1			T2	27		T5	12		T10	13