Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20985

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3544

1

T4

16

T5

45

T11

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18524

1

T2

153

T4

36

T5

30

auto[1]

6005

1

T1

3

T3

32

T5

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T192	2		T193	19		-	-
values[0]	53	1			T194	17		T195	12		T196	11
values[1]	722	1			T5	12		T23	26		T137	8
values[2]	676	1			T24	11		T102	10		T122	17
values[3]	796	1			T17	12		T21	1		T15	13
values[4]	748	1			T5	33		T12	5		T17	10
values[5]	573	1			T4	16		T5	16		T11	11
values[6]	664	1			T11	10		T13	1		T21	14
values[7]	686	1			T11	10		T12	25		T20	5
values[8]	635	1			T56	1		T21	8		T59	1
values[9]	3095	1			T1	3		T3	32		T6	1
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	944	1			T5	12		T23	26		T24	11
values[1]	659	1			T21	1		T15	13		T23	32
values[2]	805	1			T12	5		T17	10		T122	17
values[3]	718	1			T5	49		T17	12		T18	9
values[4]	504	1			T4	16		T11	11		T13	1
values[5]	776	1			T11	20		T20	5		T21	14
values[6]	2719	1			T1	3		T3	32		T6	1
values[7]	692	1			T56	1		T21	8		T59	1
values[8]	665	1			T17	3		T60	5		T105	9
values[9]	166	1			T153	19		T197	11		T139	7
minimum	15881	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T24	8		T137	1		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	1		T23	10		T197	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T21	1		T23	17		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	1		T125	10		T199	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	5		T17	10		T122	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T111	16		T147	12		T200	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	7		T17	12		T18	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	18		T125	15		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T25	3		T56	1		T23	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	9		T11	11		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	10		T20	5		T15	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	10		T21	7		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T1	3		T3	3		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T65	5		T114	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T21	4		T59	1		T67	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T56	1		T137	1		T103	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T17	3		T60	2		T201	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T105	9		T123	3		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T197	11		T139	7		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T153	8		T203	1		T167	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15733	1			T2	150		T4	20		T5	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T24	3		T137	7		T102	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	11		T23	16		T197	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T23	15		T121	4		T204	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	12		T199	13		T128	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T122	8		T198	11		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T111	13		T200	3		T129	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	9		T122	10		T27	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	15		T205	1		T206	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T25	2		T23	3		T207	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	7		T121	11		T51	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	5		T23	2		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T21	7		T122	4		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T3	29		T7	8		T12	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T123	5		T208	17		T112	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T21	4		T104	10		T209	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T137	7		T200	4		T210	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T60	3		T150	16		T211	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T123	5		T206	5		T212	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T213	14		T214	11		T215	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T153	11		T203	5		T216	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	3		T21	1		T15	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T192	1		T193	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T194	9		T195	1		T217	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T196	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	1		T138	15		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T23	10		T125	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T24	8		T102	1		T122	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T138	1		T128	19		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T17	12		T21	1		T23	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	1		T111	26		T147	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	5		T17	10		T27	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	18		T115	1		T205	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	7		T18	9		T25	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	9		T11	11		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	19		T137	1		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	10		T13	1		T21	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	10		T12	11		T20	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T65	5		T26	1		T123	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T21	4		T59	1		T201	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T56	1		T137	1		T103	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T1	3		T3	3		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T105	9		T123	3		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T192	1		T193	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T194	8		T195	11		T217	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T137	7		T123	2		T218	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	11		T23	16		T199	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T24	3		T102	9		T122	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T128	26		T205	13		T140	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T23	15		T198	11		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	12		T111	24		T200	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T27	2		T197	4		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	15		T205	1		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T5	9		T25	2		T23	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T4	7		T206	2		T219	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	5		T137	8		T102	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T21	7		T122	4		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	14		T60	3		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T123	5		T208	17		T112	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T21	4		T209	1		T117	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T137	7		T220	2		T200	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T3	29		T7	8		T221	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T123	5		T153	11		T206	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T24	7		T137	8		T102	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	12		T23	18		T197	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T21	1		T23	16		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T15	13		T125	1		T199	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	1		T17	1		T122	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T111	14		T147	1		T200	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	10		T17	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	17		T125	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T25	5		T56	1		T23	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	8		T11	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T20	1		T15	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	1		T21	9		T122	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T1	3		T3	32		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T65	1		T114	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T21	6		T59	1		T67	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T56	1		T137	8		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	1		T60	5		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T105	1		T123	6		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T197	1		T139	1		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T153	12		T203	6		T167	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15871	1			T2	153		T4	20		T5	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T24	4		T138	14		T218	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T23	8		T197	13		T205	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T23	16		T113	4		T222	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T125	9		T199	14		T128	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	4		T17	9		T122	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T111	15		T147	11		T200	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	6		T17	11		T18	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	16		T125	14		T103	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T23	2		T198	7		T207	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	8		T11	10		T110	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	9		T20	4		T15	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	9		T21	5		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T12	10		T19	19		T224	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T65	4		T123	4		T208	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T21	2		T104	9		T139	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T103	6		T201	6		T200	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T17	2		T201	6		T51	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T105	8		T123	2		T206	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T197	10		T139	6		T152	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T153	7		T216	4		T225	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T157	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T192	2		T193	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T194	9		T195	12		T217	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T196	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T137	8		T138	1		T123	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	12		T23	18		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T24	7		T102	10		T122	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T138	1		T128	28		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T17	1		T21	1		T23	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T15	13		T111	26		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	1		T17	1		T27	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	17		T115	1		T205	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T5	10		T18	1		T25	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	8		T11	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T15	14		T137	9		T102	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	1		T13	1		T21	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	1		T12	15		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T65	1		T26	1		T123	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T21	6		T59	1		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T56	1		T137	8		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T1	3		T3	32		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T105	1		T123	6		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T193	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T194	8		T217	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T196	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T138	14		T218	12		T226	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T23	8		T125	9		T199	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T24	4		T122	8		T153	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T128	17		T147	11		T205	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T17	11		T23	16		T198	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T111	24		T147	11		T200	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	4		T17	9		T27	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	16		T129	13		T171	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	6		T18	8		T23	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	8		T11	10		T125	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	10		T112	8		T154	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	9		T21	5		T223	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	9		T12	10		T20	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T65	4		T123	4		T208	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T21	2		T201	6		T139	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T103	6		T201	6		T200	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T17	2		T19	19		T224	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T105	8		T123	2		T153	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21218

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3311

1

T5

56

T11

20

T12

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18819

1

T2

153

T4

20

T5

46

auto[1]

5710

1

T1

3

T3

32

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T227	1		-	-		-	-
values[0]	76	1			T130	12		T228	9		T211	7
values[1]	573	1			T11	10		T12	5		T17	10
values[2]	803	1			T4	16		T5	12		T11	11
values[3]	592	1			T122	5		T112	17		T197	5
values[4]	582	1			T5	28		T56	1		T15	13
values[5]	2763	1			T1	3		T3	32		T5	5
values[6]	930	1			T20	5		T23	32		T114	1
values[7]	733	1			T12	25		T18	9		T21	14
values[8]	619	1			T5	16		T23	6		T24	11
values[9]	997	1			T11	10		T13	1		T17	15
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	803	1			T11	21		T12	5		T17	10
values[1]	688	1			T4	16		T5	12		T137	9
values[2]	601	1			T15	13		T122	18		T123	3
values[3]	2705	1			T1	3		T3	32		T5	28
values[4]	821	1			T5	5		T56	1		T21	1
values[5]	856	1			T12	25		T20	5		T23	32
values[6]	704	1			T18	9		T21	14		T23	32
values[7]	652	1			T5	16		T103	7		T60	5
values[8]	692	1			T13	1		T17	15		T21	8
values[9]	121	1			T11	10		T220	3		T119	1
minimum	15886	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	11		T56	1		T23	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	10		T12	5		T17	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	9		T115	1		T199	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T137	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T15	1		T112	5		T203	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T122	4		T123	1		T111	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T1	3		T3	3		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T5	15		T138	15		T197	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	3		T56	1		T23	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T21	1		T201	7		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T12	11		T20	5		T125	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T23	17		T114	1		T197	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T18	9		T23	3		T67	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T21	7		T23	10		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T60	2		T104	10		T198	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	7		T103	7		T128	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	12		T15	13		T24	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	1		T17	3		T21	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T119	1		T230	1		T157	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T11	10		T220	1		T152	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15740	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T211	1		T231	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T208	17		T207	1		T154	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T25	2		T137	7		T206	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	7		T199	13		T128	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	11		T137	8		T200	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T15	12		T112	12		T203	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T122	14		T123	2		T111	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T3	29		T7	8		T221	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T5	13		T197	16		T203	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	2		T23	2		T102	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T112	21		T116	2		T161	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	14		T102	9		T27	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T23	15		T197	2		T206	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T23	3		T232	15		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T21	7		T23	16		T122	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T60	3		T104	10		T198	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T5	9		T128	15		T123	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	2		T24	3		T218	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T21	4		T15	3		T118	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T157	12		T234	13		T235	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T220	2		T236	7		T237	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T211	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T227	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T228	9		T238	18		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T130	12		T211	1		T240	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T138	1		T208	13		T207	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	10		T12	5		T17	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	9		T11	11		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	1		T137	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T112	5		T202	1		T223	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T122	1		T197	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	1		T15	1		T65	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	15		T138	15		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T1	3		T3	3		T5	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T21	1		T229	1		T112	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T20	5		T125	15		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T23	17		T114	1		T201	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	11		T18	9		T125	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T21	7		T23	10		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T23	3		T24	8		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	7		T103	7		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T17	12		T15	13		T103	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T11	10		T13	1		T17	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T211	6		T240	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T208	17		T207	1		T154	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T25	2		T137	7		T206	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	7		T199	13		T128	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	11		T137	8		T122	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T112	12		T194	8		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T122	4		T197	4		T117	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T15	12		T60	2		T153	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	13		T123	2		T197	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T3	29		T5	2		T7	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T112	17		T116	2		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T102	7		T27	2		T205	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T23	15		T209	1		T112	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	14		T102	9		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T21	7		T23	16		T122	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T23	3		T24	3		T198	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	9		T60	1		T128	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	2		T60	3		T104	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T21	4		T15	3		T123	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1