Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21076

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3453

1

T5

45

T11

10

T12

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18433

1

T2

153

T4

36

T5

18

auto[1]

6096

1

T1

3

T3

32

T5

56

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T12	25		T18	9		-	-
values[0]	48	1			T23	6		T207	3		T117	13
values[1]	644	1			T11	10		T21	8		T59	1
values[2]	2791	1			T1	3		T3	32		T6	1
values[3]	657	1			T4	16		T5	28		T56	1
values[4]	682	1			T17	10		T15	9		T23	32
values[5]	612	1			T13	1		T25	5		T20	5
values[6]	538	1			T5	16		T11	21		T56	2
values[7]	825	1			T65	5		T115	1		T103	7
values[8]	833	1			T5	5		T12	5		T17	3
values[9]	1005	1			T5	12		T23	4		T114	1
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	886	1			T11	10		T17	12		T21	8
values[1]	2805	1			T1	3		T3	32		T5	28
values[2]	605	1			T4	16		T128	30		T123	8
values[3]	653	1			T13	1		T17	10		T20	5
values[4]	605	1			T11	11		T25	5		T56	1
values[5]	734	1			T5	16		T11	10		T56	1
values[6]	697	1			T15	28		T115	1		T103	7
values[7]	695	1			T12	5		T17	3		T137	8
values[8]	784	1			T5	5		T12	25		T114	1
values[9]	192	1			T5	12		T18	9		T23	4
minimum	15873	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	10		T21	4		T23	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T17	12		T59	1		T24	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T1	3		T3	3		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	15		T23	11		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	9		T123	3		T147	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T128	15		T209	1		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	1		T17	10		T20	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T56	1		T23	17		T218	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	11		T56	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T25	3		T21	1		T23	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	7		T56	1		T65	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	10		T122	1		T123	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	14		T103	7		T118	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T115	1		T138	15		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T125	15		T122	9		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	5		T17	3		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T114	1		T115	1		T122	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	3		T12	11		T208	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T18	9		T23	4		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T5	1		T297	2		T225	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T261	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T21	4		T23	3		T207	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T24	3		T137	7		T102	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T3	29		T7	8		T21	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	13		T23	2		T241	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T4	7		T123	5		T112	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T128	15		T209	1		T197	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	3		T104	10		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T23	15		T218	15		T116	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T102	7		T27	2		T262	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T25	2		T23	16		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	9		T60	2		T199	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T122	4		T123	5		T205	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	14		T118	10		T171	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T150	2		T151	24		T188	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T122	8		T60	1		T128	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T137	7		T111	11		T112	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T122	10		T60	3		T198	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	2		T12	14		T208	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T112	17		T268	12		T249	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T5	11		T263	31		T264	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T261	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T18	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T12	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T23	3		T207	2		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T311	4		T312	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	10		T21	4		T125	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T59	1		T24	8		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T1	3		T3	3		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T17	12		T203	1		T266	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	9		T123	3		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	15		T56	1		T23	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T17	10		T15	6		T104	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T23	17		T137	1		T116	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T20	5		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	3		T21	1		T23	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	7		T11	11		T56	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	10		T122	1		T201	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T65	5		T103	7		T60	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T115	1		T138	15		T123	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	1		T125	15		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	3		T12	5		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T23	4		T114	1		T60	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	1		T208	13		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T12	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T23	3		T207	1		T117	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T311	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T21	4		T111	13		T203	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T24	3		T137	7		T102	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1097	1			T3	29		T7	8		T21	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T203	5		T163	4		T149	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	7		T123	5		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	13		T23	2		T128	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	3		T104	10		T112	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T23	15		T137	8		T116	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T102	7		T27	2		T262	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T25	2		T23	16		T218	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	9		T15	2		T205	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T122	4		T243	12		T51	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T60	2		T199	13		T118	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T123	5		T205	1		T116	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	12		T122	18		T60	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	2		T137	7		T111	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T60	3		T123	2		T112	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	11		T208	17		T129	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T21	6		T23	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T17	1		T59	1		T24	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1464	1			T1	3		T3	32		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	14		T23	3		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	8		T123	6		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T128	16		T209	2		T197	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T17	1		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T56	1		T23	16		T218	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	1		T56	1		T102	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T25	5		T21	1		T23	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	10		T56	1		T65	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T122	5		T123	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	21		T103	1		T118	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T115	1		T138	1		T150	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T125	1		T122	9		T60	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	1		T17	1		T137	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T114	1		T115	1		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	3		T12	15		T208	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T18	1		T23	4		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T5	12		T297	2		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T261	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	9		T21	2		T23	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T17	11		T24	4		T113	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T19	19		T21	5		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	14		T23	10		T241	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	8		T123	2		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T128	14		T197	13		T226	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T17	9		T20	4		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T23	16		T218	12		T118	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	10		T27	3		T105	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T23	8		T269	8		T243	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	6		T65	4		T60	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	9		T123	4		T201	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	7		T103	6		T118	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T138	14		T228	5		T188	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T125	14		T122	8		T128	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	4		T17	2		T198	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T122	2		T198	13		T147	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	2		T12	10		T208	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T18	8		T112	4		T268	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T225	2		T145	2		T264	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T261	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T18	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T12	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T23	4		T207	2		T117	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T311	5		T312	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	1		T21	6		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T59	1		T24	7		T137	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T1	3		T3	32		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T17	1		T203	6		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	8		T123	6		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	14		T56	1		T23	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	1		T15	6		T104	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T23	16		T137	9		T116	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T20	1		T102	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T25	5		T21	1		T23	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	10		T11	1		T56	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T11	1		T122	5		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T65	1		T103	1		T60	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T115	1		T138	1		T123	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	13		T125	1		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T5	3		T12	1		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T23	4		T114	1		T60	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T5	12		T208	18		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T18	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T12	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T23	2		T207	1		T270	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T311	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T11	9		T21	2		T125	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T24	4		T113	4		T139	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T19	19		T21	5		T103	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T17	11		T266	13		T163	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	8		T123	2		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	14		T23	10		T128	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	9		T15	3		T104	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T23	16		T118	7		T222	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T20	4		T27	3		T105	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T23	8		T218	12		T266	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	6		T11	10		T15	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	9		T201	6		T269	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T65	4		T103	6		T60	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T138	14		T123	4		T228	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T125	14		T122	10		T198	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	2		T12	4		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T147	11		T112	4		T197	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T208	12		T223	14		T157	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28