Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20821

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3708

1

T5

33

T11

20

T12

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T2

151

T4

20

T5

18

auto[1]

6011

1

T1

3

T2

2

T3

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	601	1			T2	2		T16	3		T25	1
values[0]	77	1			T171	36		T310	19		T136	8
values[1]	710	1			T4	16		T5	16		T11	10
values[2]	2715	1			T1	3		T3	32		T6	1
values[3]	774	1			T21	14		T114	1		T103	7
values[4]	621	1			T5	28		T17	10		T67	1
values[5]	694	1			T15	9		T115	1		T60	7
values[6]	749	1			T12	25		T20	5		T15	13
values[7]	651	1			T5	5		T11	10		T21	1
values[8]	647	1			T17	15		T18	9		T59	1
values[9]	819	1			T5	12		T11	11		T12	5
minimum	15471	1			T2	151		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	610	1			T4	16		T5	16		T11	10
values[1]	2877	1			T1	3		T3	32		T6	1
values[2]	656	1			T5	28		T21	14		T114	1
values[3]	703	1			T17	10		T15	9		T67	1
values[4]	687	1			T128	30		T147	12		T284	2
values[5]	706	1			T12	25		T20	5		T15	13
values[6]	603	1			T5	5		T11	10		T17	12
values[7]	585	1			T11	11		T12	5		T13	1
values[8]	861	1			T5	12		T56	2		T21	8
values[9]	115	1			T226	32		T285	4		T189	1
minimum	16126	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	9		T5	7		T23	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	10		T23	17		T65	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T1	3		T3	3		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T25	3		T56	1		T122	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T21	7		T114	1		T103	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	15		T205	16		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T67	1		T102	1		T153	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T17	10		T15	6		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T206	7		T200	13		T287	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T128	15		T147	12		T284	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	1		T102	1		T139	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	11		T20	5		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T17	12		T21	1		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	3		T11	10		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	11		T17	3		T23	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	5		T13	1		T18	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T56	1		T199	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T56	1		T21	4		T15	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T189	1		T313	1		T290	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T226	16		T285	4		T286	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15807	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T23	11		T122	9		T200	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T4	7		T5	9		T23	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T23	15		T153	11		T209	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1079	1			T3	29		T7	8		T221	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T25	2		T122	10		T198	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T21	7		T243	12		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	13		T205	13		T203	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T102	9		T153	2		T206	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	3		T60	2		T27	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T206	5		T200	3		T287	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T128	15		T112	17		T116	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	12		T102	7		T306	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	14		T23	3		T137	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T112	4		T197	16		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T5	2		T60	1		T104	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T60	3		T241	13		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T137	7		T122	4		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	11		T199	13		T203	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T21	4		T15	2		T24	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T226	16		T286	10		T255	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T23	2		T122	8		T200	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T2	2		T16	3		T25	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T21	4		T114	1		T123	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T171	21		T310	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T136	1		T252	1		T314	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	9		T5	7		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	10		T23	28		T65	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T1	3		T3	3		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T25	3		T56	1		T122	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T21	7		T114	1		T103	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T198	14		T111	16		T205	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T67	1		T102	1		T206	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	15		T17	10		T27	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T153	4		T206	7		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	6		T115	1		T60	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	1		T102	1		T139	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T12	11		T20	5		T23	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T21	1		T115	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	3		T11	10		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T17	15		T59	1		T60	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T18	9		T137	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	1		T11	11		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	5		T13	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15333	1			T2	148		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T203	5		T308	11		T214	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T21	4		T123	5		T129	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T171	15		T310	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T136	7		T252	2		T314	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	7		T5	9		T161	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T23	17		T122	8		T208	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T3	29		T7	8		T23	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T25	2		T122	10		T128	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	7		T243	12		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T198	11		T111	13		T205	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T102	9		T206	2		T117	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	13		T27	2		T207	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T153	2		T206	5		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	3		T60	2		T128	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	12		T102	7		T200	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	14		T23	3		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T197	16		T154	12		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	2		T137	15		T104	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T60	3		T112	4		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T137	7		T122	4		T60	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	11		T199	13		T129	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	2		T24	3		T112	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	8		T5	10		T23	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	1		T23	16		T65	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T1	3		T3	32		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T25	5		T56	1		T122	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T21	9		T114	1		T103	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	14		T205	14		T203	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T67	1		T102	10		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T17	1		T15	6		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T206	6		T200	4		T287	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T128	16		T147	1		T284	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	13		T102	8		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	15		T20	1		T23	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T17	1		T21	1		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	3		T11	1		T60	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	1		T17	1		T23	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T13	1		T18	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	12		T56	1		T199	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T56	1		T21	6		T15	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T189	1		T313	1		T290	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T226	17		T285	1		T286	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15955	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T23	3		T122	9		T200	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T4	8		T5	6		T23	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	9		T23	16		T65	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T19	19		T224	19		T109	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T122	2		T198	13		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T21	5		T103	6		T198	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	14		T205	15		T228	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T153	3		T206	2		T118	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	9		T15	3		T60	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T206	6		T200	12		T289	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T128	14		T147	11		T112	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T139	8		T306	11		T121	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	10		T20	4		T23	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	11		T147	11		T112	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	2		T11	9		T104	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T11	10		T17	2		T113	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	4		T18	8		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T199	14		T138	14		T201	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T21	2		T15	7		T24	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T290	1		T315	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T226	15		T285	3		T286	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T161	3		T171	20		T211	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T23	10		T122	8		T200	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	430	1			T2	2		T16	3		T25	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T21	6		T114	1		T123	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T171	16		T310	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T136	8		T252	3		T314	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	8		T5	10		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	1		T23	19		T65	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T1	3		T3	32		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T25	5		T56	1		T122	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T21	9		T114	1		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T198	12		T111	14		T205	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T67	1		T102	10		T206	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	14		T17	1		T27	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T153	3		T206	6		T220	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T15	6		T115	1		T60	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T15	13		T102	8		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	15		T20	1		T23	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T21	1		T115	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	3		T11	1		T137	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T17	2		T59	1		T60	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T18	1		T137	8		T122	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	12		T11	1		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	1		T13	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15471	1			T2	151		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T214	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T21	2		T123	2		T139	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T171	20		T310	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T314	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T4	8		T5	6		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	9		T23	26		T65	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T19	19		T23	8		T224	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T122	2		T128	3		T216	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T21	5		T103	6		T198	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T198	13		T111	15		T205	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T206	2		T118	7		T222	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	14		T17	9		T27	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T153	3		T206	6		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T15	3		T60	3		T128	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T139	8		T200	12		T121	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	10		T20	4		T23	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T147	11		T197	13		T154	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	2		T11	9		T104	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T17	13		T112	4		T113	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T18	8		T218	12		T197	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	10		T199	14		T138	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	4		T15	7		T24	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28