Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21079

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3450

1

T4

16

T5

61

T11

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18415

1

T2

153

T4

36

T5

30

auto[1]

6114

1

T1

3

T3

32

T5

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	192	1			T206	12		T119	1		T150	18
values[0]	24	1			T196	11		T217	13		-	-
values[1]	702	1			T5	12		T23	26		T137	8
values[2]	667	1			T24	11		T102	10		T138	1
values[3]	854	1			T17	22		T21	1		T15	13
values[4]	770	1			T5	33		T12	5		T125	15
values[5]	544	1			T4	16		T5	16		T11	11
values[6]	617	1			T11	10		T13	1		T21	14
values[7]	740	1			T11	10		T12	25		T20	5
values[8]	627	1			T56	1		T21	8		T59	1
values[9]	2932	1			T1	3		T3	32		T6	1
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	737	1			T23	26		T24	11		T125	10
values[1]	632	1			T21	1		T15	13		T198	1
values[2]	888	1			T12	5		T17	22		T23	32
values[3]	688	1			T5	33		T18	9		T125	15
values[4]	482	1			T4	16		T5	16		T11	11
values[5]	817	1			T11	20		T20	5		T21	14
values[6]	2724	1			T1	3		T3	32		T6	1
values[7]	678	1			T56	1		T21	8		T59	1
values[8]	688	1			T17	3		T60	5		T105	9
values[9]	141	1			T139	7		T202	1		T150	3
minimum	16054	1			T2	153		T4	20		T5	25

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T24	8		T102	1		T138	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T23	10		T125	10		T199	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T21	1		T198	1		T229	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	1		T128	19		T147	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T12	5		T17	22		T23	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T111	10		T147	12		T200	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T18	9		T122	3		T27	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	18		T125	15		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	11		T25	3		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	9		T5	7		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	10		T20	5		T15	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	10		T21	7		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T1	3		T3	3		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	11		T65	5		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T21	4		T59	1		T104	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	1		T137	1		T103	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	3		T60	2		T201	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T105	9		T123	3		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T139	7		T202	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T167	1		T216	5		T225	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15757	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T5	1		T203	1		T248	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	3		T102	9		T218	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T23	16		T199	13		T205	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T241	13		T121	4		T204	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	12		T128	26		T162	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T23	15		T122	8		T198	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T111	11		T200	3		T129	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T122	10		T27	2		T197	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	15		T205	1		T206	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T25	2		T23	5		T207	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T4	7		T5	9		T149	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	2		T137	8		T102	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T21	7		T15	3		T122	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T3	29		T7	8		T221	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	14		T123	5		T208	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T21	4		T104	10		T209	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T137	7		T200	4		T210	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T60	3		T150	14		T51	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T123	5		T153	11		T206	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T150	2		T213	14		T316	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T216	4		T317	8		T318	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T5	11		T203	3		T248	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T119	1		T150	2		T265	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T206	7		T167	1		T216	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T217	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T196	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T137	1		T138	15		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	1		T23	10		T125	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T24	8		T102	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T138	1		T128	19		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T17	22		T21	1		T23	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	1		T111	10		T147	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	5		T27	4		T147	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	18		T125	15		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	11		T18	9		T25	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	9		T5	7		T103	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	13		T137	1		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	10		T13	1		T21	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	10		T20	5		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	11		T65	5		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	4		T59	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T56	1		T137	1		T103	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T1	3		T3	3		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T105	9		T123	3		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T150	16		T265	12		T193	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T206	5		T216	4		T192	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T217	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T137	7		T123	2		T218	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	11		T23	16		T199	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T24	3		T102	9		T197	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T128	26		T205	13		T140	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T23	15		T122	8		T198	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	12		T111	11		T200	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T27	2		T197	4		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	15		T205	1		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T25	2		T23	5		T122	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	7		T5	9		T206	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	2		T137	8		T102	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T21	7		T15	3		T122	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T60	3		T112	21		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	14		T123	5		T208	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T21	4		T209	1		T117	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T137	7		T220	2		T200	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T3	29		T7	8		T221	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T123	5		T153	11		T203	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T24	7		T102	10		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T23	18		T125	1		T199	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T21	1		T198	1		T229	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T15	13		T128	28		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	1		T17	2		T23	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T111	12		T147	1		T200	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T18	1		T122	11		T27	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	17		T125	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	1		T25	5		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	8		T5	10		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	1		T20	1		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	1		T21	9		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T1	3		T3	32		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	15		T65	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T21	6		T59	1		T104	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T56	1		T137	8		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	1		T60	5		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T105	1		T123	6		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T139	1		T202	1		T150	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T167	1		T216	5		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15900	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T5	12		T203	4		T248	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T24	4		T138	14		T218	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T23	8		T125	9		T199	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T113	4		T241	13		T222	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T128	17		T147	11		T222	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	4		T17	20		T23	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T111	9		T147	11		T200	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T18	8		T122	2		T27	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	16		T125	14		T103	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	10		T23	12		T198	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T4	8		T5	6		T110	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	9		T20	4		T15	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	9		T21	5		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T19	19		T224	19		T109	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	10		T65	4		T123	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T21	2		T104	9		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T103	6		T201	6		T200	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T17	2		T201	6		T197	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T105	8		T123	2		T153	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T139	6		T143	10		T213	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T216	4		T225	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T194	8		T152	8		T319	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T248	8		T254	9		T196	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T119	1		T150	18		T265	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T206	6		T167	1		T216	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T217	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T196	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T137	8		T138	1		T123	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	12		T23	18		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T24	7		T102	10		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T138	1		T128	28		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T17	2		T21	1		T23	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	13		T111	12		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	1		T27	3		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	17		T125	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T11	1		T18	1		T25	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	8		T5	10		T103	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	8		T137	9		T102	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T13	1		T21	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	1		T20	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	15		T65	1		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T21	6		T59	1		T209	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T56	1		T137	8		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1473	1			T1	3		T3	32		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T105	1		T123	6		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T143	10		T193	9		T217	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T206	6		T216	4		T320	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T217	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T196	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T138	14		T218	12		T226	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T23	8		T125	9		T199	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T24	4		T113	4		T197	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T128	17		T147	11		T205	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T17	20		T23	16		T122	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T111	9		T147	11		T200	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	4		T27	3		T147	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	16		T125	14		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	10		T18	8		T23	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	8		T5	6		T103	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T15	7		T154	11		T130	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	9		T21	5		T15	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	9		T20	4		T60	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	10		T65	4		T123	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T21	2		T139	10		T211	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T103	6		T201	6		T200	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T17	2		T19	19		T224	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T105	8		T123	2		T153	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28