Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21192

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3337

1

T4

16

T5

12

T11

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18995

1

T2

153

T4

36

T5

18

auto[1]

5534

1

T1

3

T3

32

T5

56

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	372	1			T11	10		T112	17		T197	11
values[0]	25	1			T125	10		T294	13		T300	2
values[1]	567	1			T5	16		T11	11		T18	9
values[2]	764	1			T12	25		T13	1		T17	3
values[3]	605	1			T5	5		T21	8		T23	6
values[4]	688	1			T4	16		T12	5		T17	10
values[5]	819	1			T5	28		T20	5		T15	15
values[6]	686	1			T25	5		T15	13		T24	11
values[7]	546	1			T21	1		T125	15		T102	8
values[8]	2648	1			T1	3		T3	32		T6	1
values[9]	949	1			T5	12		T17	12		T15	9
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	663	1			T12	25		T18	9		T23	32
values[1]	676	1			T13	1		T17	3		T56	2
values[2]	656	1			T5	5		T56	1		T21	8
values[3]	738	1			T4	16		T5	28		T12	5
values[4]	715	1			T20	5		T23	4		T114	1
values[5]	748	1			T25	5		T15	13		T24	11
values[6]	2602	1			T1	3		T3	32		T6	1
values[7]	518	1			T59	1		T65	5		T60	7
values[8]	1052	1			T5	12		T11	10		T17	12
values[9]	147	1			T139	7		T119	1		T266	3
minimum	16014	1			T2	153		T4	20		T5	29

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T18	9		T23	17		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	11		T125	10		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T17	3		T56	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	1		T56	1		T21	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	3		T137	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T56	1		T21	4		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	15		T12	5		T15	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	9		T17	10		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T114	1		T122	3		T103	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T20	5		T23	4		T197	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	1		T27	4		T105	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T25	3		T24	8		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T1	3		T3	3		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	10		T21	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T65	5		T138	1		T198	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T59	1		T60	5		T199	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T15	6		T23	11		T147	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T5	1		T11	10		T17	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T139	7		T266	3		T298	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T119	1		T295	1		T321	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15769	1			T2	150		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T11	11		T115	1		T122	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T23	15		T137	7		T60	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	14		T122	4		T128	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T197	2		T154	12		T188	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T21	7		T23	3		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	2		T137	8		T112	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T21	4		T137	7		T104	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	13		T15	2		T128	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	7		T102	9		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T122	10		T60	1		T207	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T197	16		T116	14		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	12		T27	2		T123	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T25	2		T24	3		T226	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T3	29		T7	8		T221	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T102	7		T150	6		T140	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T198	11		T206	5		T118	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T60	2		T199	13		T149	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	3		T23	2		T151	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T5	11		T23	16		T112	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T298	7		T62	2		T322	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T321	14		T299	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	3		T5	9		T21	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T122	8		T111	13		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T139	7		T151	1		T292	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T11	10		T112	5		T197	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T294	13		T300	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T125	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	7		T18	9		T129	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	11		T115	1		T122	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	3		T56	1		T23	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	11		T13	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	3		T137	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T21	4		T23	3		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	5		T26	1		T128	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	9		T17	10		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	15		T15	13		T114	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T20	5		T23	4		T198	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	1		T103	7		T27	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	3		T24	8		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T125	15		T123	5		T110	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T21	1		T102	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T1	3		T3	3		T6	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	10		T60	5		T199	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T15	6		T23	11		T65	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	1		T17	12		T23	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T151	11		T192	1		T323	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T112	12		T265	9		T256	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T300	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T5	9		T262	6		T254	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T122	12		T128	11		T111	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T23	15		T137	7		T60	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	14		T21	7		T112	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T5	2		T137	8		T197	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T21	4		T23	3		T137	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T128	15		T218	15		T112	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	7		T102	9		T123	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	13		T15	2		T122	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T197	16		T116	14		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	12		T27	2		T208	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	2		T24	3		T226	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T123	5		T206	2		T212	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T102	7		T150	6		T140	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T3	29		T7	8		T221	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T60	2		T199	13		T149	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	3		T23	2		T298	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	11		T23	16		T200	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T18	1		T23	16		T137	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	15		T125	1		T122	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T17	1		T56	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T56	1		T21	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	3		T137	9		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T56	1		T21	6		T137	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	14		T12	1		T15	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	8		T17	1		T102	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T114	1		T122	11		T103	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T20	1		T23	4		T197	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T15	13		T27	3		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T25	5		T24	7		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T1	3		T3	32		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T21	1		T102	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T65	1		T138	1		T198	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T59	1		T60	4		T199	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T15	6		T23	3		T147	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T5	12		T11	1		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T139	1		T266	1		T298	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T119	1		T295	1		T321	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15904	1			T2	153		T4	20		T5	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T11	1		T115	1		T122	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T18	8		T23	16		T129	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	10		T125	9		T128	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T17	2		T113	2		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T21	5		T23	2		T103	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	2		T112	4		T113	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T21	2		T104	9		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	14		T12	4		T15	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	8		T17	9		T138	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T122	2		T103	6		T201	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	4		T197	13		T154	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T27	3		T105	8		T123	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T24	4		T153	6		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T19	19		T125	14		T224	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T11	9		T164	3		T285	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T65	4		T198	13		T205	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T60	3		T199	14		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	3		T23	10		T147	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	9		T17	11		T23	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T139	6		T266	2		T298	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T321	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T5	6		T262	7		T294	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T11	10		T122	8		T111	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T139	1		T151	12		T292	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	1		T112	13		T197	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T294	1		T300	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T125	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	10		T18	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T115	1		T122	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T17	1		T56	1		T23	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	15		T13	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T5	3		T137	9		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T21	6		T23	4		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T26	1		T128	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	8		T17	1		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	14		T15	8		T114	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T20	1		T23	4		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	13		T103	1		T27	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T25	5		T24	7		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T125	1		T123	6		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T21	1		T102	8		T150	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T1	3		T3	32		T6	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	1		T60	4		T199	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	6		T23	3		T65	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T5	12		T17	1		T23	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T139	6		T323	3		T61	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T11	9		T112	4		T197	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T294	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T125	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	6		T18	8		T129	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T11	10		T122	8		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T17	2		T23	16		T113	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	10		T21	5		T103	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T5	2		T113	4		T154	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T21	2		T23	2		T104	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	4		T128	14		T218	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T4	8		T17	9		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	14		T15	7		T122	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T20	4		T198	7		T197	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T103	6		T27	3		T105	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T24	4		T153	6		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T125	14		T123	4		T110	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T232	13		T164	3		T285	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T19	19		T224	19		T109	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T11	9		T60	3		T199	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T15	3		T23	10		T65	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T17	11		T23	8		T113	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28