Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19364

1

T2

153

T4

36

T5

41

auto[ADC_CTRL_FILTER_COND_OUT]

5165

1

T1

3

T3

32

T5

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18927

1

T2

153

T4

20

T5

41

auto[1]

5602

1

T1

3

T3

32

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	321	1			T56	1		T59	1		T123	3
values[0]	67	1			T150	7		T210	13		T268	28
values[1]	842	1			T5	5		T23	26		T114	2
values[2]	654	1			T5	12		T56	1		T137	8
values[3]	734	1			T5	16		T21	8		T15	28
values[4]	655	1			T11	20		T25	5		T15	9
values[5]	537	1			T17	10		T21	1		T23	32
values[6]	541	1			T17	3		T20	5		T23	6
values[7]	720	1			T4	16		T11	11		T12	25
values[8]	707	1			T5	28		T12	5		T13	1
values[9]	2891	1			T1	3		T3	32		T6	1
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	865	1			T5	5		T56	1		T23	26
values[1]	2703	1			T1	3		T3	32		T5	12
values[2]	740	1			T5	16		T25	5		T21	8
values[3]	629	1			T11	20		T17	10		T65	5
values[4]	578	1			T21	1		T23	32		T114	1
values[5]	586	1			T17	3		T20	5		T23	6
values[6]	675	1			T4	16		T5	28		T11	11
values[7]	635	1			T12	5		T13	1		T17	12
values[8]	881	1			T18	9		T56	1		T59	1
values[9]	128	1			T208	30		T223	6		T140	12
minimum	16109	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T122	4		T197	14		T200	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	3		T56	1		T23	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	1		T137	2		T60	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1378	1			T1	3		T3	3		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	7		T25	3		T15	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T21	4		T15	6		T23	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	10		T65	5		T138	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	10		T17	10		T128	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T21	1		T114	1		T125	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T23	17		T104	10		T123	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T17	3		T20	5		T105	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T23	3		T27	4		T284	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	9		T12	11		T21	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	15		T11	11		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	1		T125	10		T103	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	5		T17	12		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T18	9		T56	1		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T123	1		T112	5		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T223	6		T140	1		T51	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T208	13		T285	9		T324	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15772	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T114	1		T102	1		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T122	14		T197	16		T200	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	2		T23	16		T123	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	11		T137	14		T60	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1025	1			T3	29		T7	8		T221	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	9		T25	2		T15	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T21	4		T15	3		T23	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T153	2		T117	15		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T128	11		T111	11		T116	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T102	9		T161	2		T248	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T23	15		T104	10		T123	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T112	17		T154	15		T150	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T23	3		T27	2		T112	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	7		T12	14		T21	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T5	13		T128	15		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T206	2		T129	1		T162	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T137	8		T122	8		T60	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T199	13		T111	13		T203	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T123	2		T112	4		T197	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T140	11		T51	4		T325	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T208	17		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T102	7		T153	11		T206	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T56	1		T59	1		T111	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T123	1		T200	13		T119	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T150	1		T268	16		T310	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T210	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T115	1		T122	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	3		T23	10		T114	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	1		T137	1		T122	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T56	1		T103	7		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	7		T15	14		T24	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T21	4		T23	15		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	10		T25	3		T65	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	10		T15	6		T128	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	1		T114	1		T125	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	10		T23	17		T104	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T17	3		T20	5		T105	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T23	3		T27	4		T123	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	9		T12	11		T198	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	11		T17	12		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T13	1		T21	7		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T5	15		T12	5		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T18	9		T115	1		T203	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1372	1			T1	3		T3	3		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T111	13		T121	11		T140	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T123	2		T200	3		T233	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T150	6		T268	12		T310	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T210	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T122	4		T197	16		T200	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	2		T23	16		T102	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	11		T137	7		T122	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T209	1		T220	2		T118	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	9		T15	14		T24	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T21	4		T23	2		T60	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T25	2		T153	2		T117	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	3		T128	11		T116	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T102	9		T161	2		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T23	15		T104	10		T111	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T112	17		T154	15		T150	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T23	3		T27	2		T123	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	7		T12	14		T207	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T122	8		T128	15		T30	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T21	7		T199	13		T206	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T5	13		T137	8		T60	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T203	5		T304	7		T121	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1094	1			T3	29		T7	8		T221	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T122	16		T197	17		T200	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	3		T56	1		T23	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	12		T137	16		T60	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1365	1			T1	3		T3	32		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	10		T25	5		T15	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T21	6		T15	6		T23	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T65	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	1		T17	1		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T21	1		T114	1		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T23	16		T104	11		T123	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T17	1		T20	1		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T23	4		T27	3		T284	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T4	8		T12	15		T21	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	14		T11	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T125	1		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T17	1		T137	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T18	1		T56	1		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T123	3		T112	5		T197	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T223	1		T140	12		T51	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T208	18		T285	1		T324	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15921	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T114	1		T102	8		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T122	2		T197	13		T200	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	2		T23	8		T103	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T60	3		T201	6		T147	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1038	1			T19	19		T224	19		T109	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T5	6		T15	7		T24	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T21	2		T15	3		T23	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	9		T65	4		T138	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	9		T17	9		T128	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T125	14		T110	10		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T23	16		T104	9		T123	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	2		T20	4		T105	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T23	2		T27	3		T112	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	8		T12	10		T21	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	14		T11	10		T128	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T125	9		T103	2		T206	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T12	4		T17	11		T122	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T18	8		T199	14		T111	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T112	4		T139	16		T200	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T223	5		T51	3		T325	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T208	12		T285	8		T324	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T326	5		T268	15		T320	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T153	7		T206	6		T241	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T56	1		T59	1		T111	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T123	3		T200	4		T119	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T150	7		T268	13		T310	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T210	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T115	1		T122	5		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	3		T23	18		T114	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	12		T137	8		T122	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T56	1		T103	1		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	10		T15	21		T24	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T21	6		T23	7		T60	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T25	5		T65	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	1		T15	6		T128	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	1		T114	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	1		T23	16		T104	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T17	1		T20	1		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T23	4		T27	3		T123	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	8		T12	15		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	1		T17	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T13	1		T21	9		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	14		T12	1		T137	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T18	1		T115	1		T203	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1434	1			T1	3		T3	32		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T111	15		T130	11		T121	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T200	12		T233	13		T286	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T268	15		T310	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T197	13		T200	13		T291	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	2		T23	8		T123	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T122	2		T60	3		T201	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T103	6		T129	10		T118	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	6		T15	7		T24	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T21	2		T23	10		T198	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	9		T65	4		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T11	9		T15	3		T128	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T125	14		T138	14		T161	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T17	9		T23	16		T104	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T17	2		T20	4		T105	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T23	2		T27	3		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	8		T12	10		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	10		T17	11		T122	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T21	5		T125	9		T103	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T5	14		T12	4		T153	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T18	8		T223	5		T121	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1032	1			T19	19		T224	19		T109	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28