Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21218

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3311

1

T5

56

T12

5

T17

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18683

1

T2

153

T4

20

T5

57

auto[1]

5846

1

T1

3

T3

32

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	289	1			T24	11		T118	16		T150	3
values[0]	76	1			T23	13		T155	16		T233	26
values[1]	666	1			T21	14		T23	6		T137	9
values[2]	627	1			T5	5		T11	10		T17	10
values[3]	492	1			T5	12		T12	5		T17	12
values[4]	2804	1			T1	3		T3	32		T6	1
values[5]	871	1			T4	16		T15	9		T65	5
values[6]	660	1			T11	10		T15	13		T59	1
values[7]	628	1			T5	28		T13	1		T25	5
values[8]	565	1			T5	16		T18	9		T20	5
values[9]	991	1			T11	11		T12	25		T17	3
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	631	1			T21	14		T15	15		T23	13
values[1]	632	1			T11	10		T17	22		T56	1
values[2]	550	1			T5	17		T12	5		T105	9
values[3]	2857	1			T1	3		T3	32		T6	1
values[4]	939	1			T4	16		T15	13		T59	1
values[5]	503	1			T5	28		T11	10		T25	5
values[6]	608	1			T13	1		T20	5		T23	4
values[7]	606	1			T5	16		T12	25		T17	3
values[8]	951	1			T11	11		T24	11		T115	2
values[9]	147	1			T23	26		T122	17		T304	8
minimum	16105	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	13		T23	11		T116	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T21	7		T114	1		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	10		T17	22		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T21	4		T23	17		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	3		T110	11		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T12	5		T105	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T1	3		T3	3		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T114	1		T125	10		T226	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	9		T15	1		T59	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T65	5		T125	15		T138	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	10		T25	3		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	15		T56	1		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	1		T20	5		T23	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T67	1		T102	1		T113	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	11		T137	1		T103	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	7		T17	3		T18	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T11	11		T115	2		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T24	8		T60	5		T201	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T304	1		T298	8		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T23	10		T122	9		T291	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15775	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T137	1		T28	1		T218	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	2		T23	2		T116	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T21	7		T150	14		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T104	10		T206	5		T117	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T21	4		T23	15		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T5	2		T209	1		T188	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	11		T198	11		T260	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T3	29		T7	8		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T226	16		T268	12		T156	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	7		T15	12		T206	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T153	11		T197	4		T194	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T25	2		T128	11		T123	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	13		T154	15		T129	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T102	9		T30	2		T200	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T102	7		T220	2		T211	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	14		T137	7		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T5	9		T208	17		T111	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T27	2		T128	15		T111	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	3		T60	2		T150	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T304	7		T136	2		T255	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T23	16		T122	8		T256	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T137	8		T218	15		T112	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T118	8		T150	1		T304	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T24	8		T121	12		T291	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T23	11		T263	1		T242	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T155	12		T233	14		T305	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T23	3		T122	3		T197	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T21	7		T137	1		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	3		T11	10		T17	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	4		T23	17		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	12		T56	1		T104	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	1		T12	5		T105	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T1	3		T3	3		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T114	1		T125	10		T198	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	9		T15	6		T199	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T65	5		T125	15		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	10		T15	1		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T198	8		T229	1		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T25	3		T23	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	15		T56	1		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T20	5		T103	3		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	7		T18	9		T103	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T11	11		T12	11		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T17	3		T23	10		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T118	8		T150	2		T304	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T24	3		T121	11		T256	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T23	2		T263	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T155	4		T233	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T23	3		T122	10		T197	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T21	7		T137	8		T218	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	2		T15	2		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T21	4		T23	15		T137	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T104	10		T209	1		T206	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T5	11		T260	15		T149	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T3	29		T7	8		T221	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T198	11		T268	12		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	7		T15	3		T199	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T153	11		T226	16		T194	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	12		T123	5		T117	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T197	4		T154	15		T129	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	2		T102	9		T128	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	13		T102	7		T220	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T123	2		T112	17		T205	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T5	9		T208	17		T111	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	14		T137	7		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T23	16		T122	8		T60	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	8		T23	3		T116	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T21	9		T114	1		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	1		T17	2		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T21	6		T23	16		T137	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T5	3		T110	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	12		T12	1		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T1	3		T3	32		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T114	1		T125	1		T226	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T4	8		T15	13		T59	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T65	1		T125	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	1		T25	5		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	14		T56	1		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T20	1		T23	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T67	1		T102	8		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	15		T137	8		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	10		T17	1		T18	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	1		T115	2		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T24	7		T60	4		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T304	8		T298	1		T136	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T23	18		T122	9		T291	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15912	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T137	9		T28	1		T218	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T15	7		T23	10		T306	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	5		T147	11		T222	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	9		T17	20		T104	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T21	2		T23	16		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T5	2		T110	10		T188	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	4		T105	8		T198	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T19	19		T15	3		T224	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T125	9		T226	15		T268	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	8		T206	2		T228	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T65	4		T125	14		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	9		T128	3		T123	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T5	14		T154	13		T266	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T20	4		T113	2		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T113	10		T269	8		T130	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	10		T103	2		T112	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	6		T17	2		T18	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	10		T27	3		T128	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	4		T60	3		T201	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T298	7		T255	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T23	8		T122	8		T291	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T23	2		T122	2		T197	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T218	12		T112	4		T222	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T118	9		T150	3		T304	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T24	7		T121	12		T291	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T23	3		T263	8		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T155	10		T233	13		T305	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T23	4		T122	11		T197	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T21	9		T137	9		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	3		T11	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	6		T23	16		T137	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T17	1		T56	1		T104	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	12		T12	1		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T1	3		T3	32		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T114	1		T125	1		T198	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	8		T15	6		T199	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T65	1		T125	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T15	13		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T198	1		T229	1		T197	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T25	5		T23	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	14		T56	1		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T20	1		T103	1		T123	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T5	10		T18	1		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T11	1		T12	15		T137	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T17	1		T23	18		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T118	7		T278	2		T324	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T24	4		T121	11		T291	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T23	10		T242	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T155	6		T233	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T23	2		T122	2		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T21	5		T218	12		T112	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	2		T11	9		T17	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T21	2		T23	16		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T17	11		T104	9		T110	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	4		T105	8		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T19	19		T224	19		T109	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T125	9		T198	13		T268	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	8		T15	3		T199	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T65	4		T125	14		T138	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	9		T123	4		T291	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T198	7		T154	13		T228	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T128	3		T113	2		T118	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	14		T113	10		T269	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T20	4		T103	2		T112	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T5	6		T18	8		T103	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	10		T12	10		T27	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	2		T23	8		T122	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28