Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	1		T56	1		T23	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	1		T12	1		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	8		T115	1		T199	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	12		T137	9		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	13		T112	13		T203	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T122	16		T123	3		T111	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1439	1			T1	3		T3	32		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	14		T138	1		T197	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	3		T56	1		T23	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T21	1		T201	1		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	15		T20	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T23	16		T114	1		T197	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T18	1		T23	4		T67	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T21	9		T23	18		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T60	5		T104	11		T198	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	10		T103	1		T128	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T17	1		T15	8		T24	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	1		T17	1		T21	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T119	1		T230	1		T157	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T11	1		T220	3		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15861	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T211	7		T231	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	10		T208	12		T207	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	9		T12	4		T17	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	8		T199	14		T128	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T105	8		T110	10		T113	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T112	4		T223	14		T194	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T122	2		T111	15		T222	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T19	19		T65	4		T224	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T5	14		T138	14		T197	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	2		T23	10		T123	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T201	6		T112	8		T161	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	10		T20	4		T125	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T23	16		T197	4		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T18	8		T23	2		T125	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T21	5		T23	8		T122	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T104	9		T198	13		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	6		T103	6		T128	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T17	11		T15	7		T24	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T17	2		T21	2		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T157	19		T234	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T11	9		T152	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T238	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T227	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T228	1		T238	1		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T130	1		T211	7		T240	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T138	1		T208	18		T207	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T12	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	8		T11	1		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	12		T137	9		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T112	13		T202	1		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T122	5		T197	5		T117	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T56	1		T15	13		T65	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	14		T138	1		T123	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T1	3		T3	32		T5	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T21	1		T229	1		T112	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T20	1		T125	1		T102	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T23	16		T114	1		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	15		T18	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T21	9		T23	18		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T23	4		T24	7		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	10		T103	1		T60	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T17	1		T15	8		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T11	1		T13	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T228	8		T238	17		T242	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T130	11		T240	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T208	12		T207	1		T154	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	9		T12	4		T17	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	8		T11	10		T199	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T122	2		T105	8		T110	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T112	4		T223	14		T194	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T243	12		T156	12		T244	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T65	4		T60	3		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T5	14		T138	14		T197	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T5	2		T19	19		T23	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T112	4		T161	3		T154	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T20	4		T125	14		T27	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T23	16		T201	6		T112	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	10		T18	8		T125	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T21	5		T23	8		T122	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T23	2		T24	4		T198	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T5	6		T103	6		T128	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T17	11		T15	7		T103	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	9		T17	2		T21	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28