Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20800

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3729

1

T4

16

T5

28

T11

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18873

1

T2

153

T4

20

T5

74

auto[1]

5656

1

T1

3

T3

32

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T139	7		T148	1		T245	2
values[0]	98	1			T15	15		T147	12		T227	1
values[1]	522	1			T4	16		T12	5		T20	5
values[2]	554	1			T102	8		T122	17		T113	5
values[3]	702	1			T5	16		T56	1		T15	9
values[4]	640	1			T11	10		T18	9		T56	1
values[5]	3011	1			T1	3		T3	32		T5	33
values[6]	679	1			T11	10		T17	12		T21	1
values[7]	718	1			T12	25		T21	14		T125	15
values[8]	681	1			T5	12		T13	1		T56	1
values[9]	1053	1			T17	13		T15	13		T23	26
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	769	1			T4	16		T12	5		T20	5
values[1]	647	1			T5	16		T122	17		T113	8
values[2]	571	1			T11	10		T56	2		T15	9
values[3]	2769	1			T1	3		T3	32		T5	5
values[4]	926	1			T5	28		T11	11		T17	12
values[5]	687	1			T11	10		T21	1		T114	1
values[6]	721	1			T12	25		T13	1		T21	14
values[7]	669	1			T5	12		T56	1		T23	32
values[8]	786	1			T17	10		T23	26		T24	11
values[9]	101	1			T17	3		T15	13		T137	8
minimum	15883	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	5		T23	4		T105	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T4	9		T20	5		T15	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T197	14		T30	1		T154	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	7		T122	9		T113	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T56	2		T23	11		T128	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	10		T15	6		T199	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T1	3		T3	3		T5	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T125	10		T103	7		T128	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	15		T11	11		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T17	12		T25	3		T21	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	10		T114	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T21	1		T103	3		T198	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T115	1		T122	3		T201	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	11		T13	1		T21	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T56	1		T65	5		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	1		T23	17		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T114	1		T27	4		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T17	10		T23	10		T24	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T15	1		T137	1		T139	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T17	3		T201	7		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T197	11		T246	7		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T116	2		T30	2		T203	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	7		T15	2		T102	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T197	16		T30	1		T203	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	9		T122	8		T116	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T23	2		T128	15		T117	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T15	3		T199	13		T104	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T3	29		T5	2		T7	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T128	11		T220	2		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	13		T102	9		T123	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T25	2		T21	4		T60	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T60	4		T197	2		T129	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T111	13		T206	2		T248	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T122	10		T112	12		T197	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	14		T21	7		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T118	7		T162	2		T211	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	11		T23	15		T137	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T27	2		T198	11		T226	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T23	16		T24	3		T122	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T15	12		T137	7		T249	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T250	7		T251	2		T252	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T246	2		T247	1		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T139	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T148	1		T245	2		T253	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T15	13		T147	12		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	5		T23	4		T105	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	9		T20	5		T113	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T30	1		T203	1		T232	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T102	1		T122	9		T113	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T56	1		T128	15		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	7		T15	6		T199	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T18	9		T56	1		T23	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	10		T103	7		T128	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T1	3		T3	3		T5	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T25	3		T21	4		T125	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	10		T114	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T17	12		T21	1		T60	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T115	1		T60	3		T201	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	11		T21	7		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T56	1		T122	3		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T13	1		T23	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T15	1		T65	5		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T17	13		T23	10		T24	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T15	2		T254	12		T255	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T116	2		T30	2		T203	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	7		T205	13		T194	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T30	1		T203	3		T232	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T102	7		T122	8		T116	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T128	15		T197	16		T117	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	9		T15	3		T199	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T23	5		T209	1		T112	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T128	11		T220	2		T161	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T3	29		T5	15		T7	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T25	2		T21	4		T123	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T197	2		T129	2		T150	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T60	2		T206	2		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T60	4		T112	12		T197	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	14		T21	7		T111	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T122	10		T118	7		T162	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	11		T23	15		T137	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	12		T137	7		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T23	16		T24	3		T122	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T23	4		T105	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T4	8		T20	1		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T197	17		T30	2		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	10		T122	9		T113	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T56	2		T23	3		T128	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	1		T15	6		T199	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T1	3		T3	32		T5	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T125	1		T103	1		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T5	14		T11	1		T102	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T17	1		T25	5		T21	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T114	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T21	1		T103	1		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T115	1		T122	11		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T12	15		T13	1		T21	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T56	1		T65	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	12		T23	16		T137	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T114	1		T27	3		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T17	1		T23	18		T24	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T15	13		T137	8		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T17	1		T201	1		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T197	1		T246	3		T247	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	4		T105	8		T30	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	8		T20	4		T15	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T197	13		T154	11		T121	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T5	6		T122	8		T113	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T23	10		T128	14		T51	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	9		T15	3		T199	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T5	2		T18	8		T19	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T125	9		T103	6		T128	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	14		T11	10		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T17	11		T21	2		T60	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	9		T197	4		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T103	2		T198	7		T111	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T122	2		T201	6		T112	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	10		T21	5		T125	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T65	4		T118	8		T222	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T23	16		T206	6		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T27	3		T198	13		T110	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T17	9		T23	8		T24	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T139	6		T222	2		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T17	2		T201	6		T250	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T197	10		T246	6		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T139	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T148	1		T245	2		T253	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T15	8		T147	1		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T12	1		T23	4		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	8		T20	1		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T30	2		T203	4		T232	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T102	8		T122	9		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T56	1		T128	16		T197	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	10		T15	6		T199	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T18	1		T56	1		T23	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	1		T103	1		T128	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1473	1			T1	3		T3	32		T5	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T25	5		T21	6		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T114	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T17	1		T21	1		T60	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T115	1		T60	7		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	15		T21	9		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T56	1		T122	11		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T5	12		T13	1		T23	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T15	13		T65	1		T137	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T17	2		T23	18		T24	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T139	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T15	7		T147	11		T254	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	4		T105	8		T30	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	8		T20	4		T113	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T232	14		T256	7		T257	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T122	8		T113	4		T118	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T128	14		T197	13		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T5	6		T15	3		T199	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T18	8		T23	12		T153	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	9		T103	6		T128	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T5	16		T11	10		T19	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T21	2		T125	9		T123	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	9		T197	4		T129	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	11		T60	3		T113	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T201	6		T112	4		T216	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	10		T21	5		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T122	2		T118	8		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T23	16		T138	14		T111	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T65	4		T27	3		T198	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T17	11		T23	8		T24	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28