Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21064

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3465

1

T5

45

T11

10

T12

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18445

1

T2

153

T4

36

T5

18

auto[1]

6084

1

T1

3

T3

32

T5

56

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	245	1			T5	12		T12	25		T23	4
values[0]	7	1			T258	7		-	-		-	-
values[1]	742	1			T11	10		T21	8		T23	6
values[2]	2769	1			T1	3		T3	32		T6	1
values[3]	624	1			T4	16		T5	28		T56	1
values[4]	663	1			T17	10		T23	32		T104	20
values[5]	651	1			T11	11		T13	1		T25	5
values[6]	486	1			T5	16		T56	2		T122	5
values[7]	893	1			T11	10		T15	28		T65	5
values[8]	728	1			T12	5		T17	3		T137	8
values[9]	861	1			T5	5		T18	9		T114	1
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	721	1			T11	10		T17	12		T23	6
values[1]	2722	1			T1	3		T3	32		T5	28
values[2]	706	1			T4	16		T23	13		T128	30
values[3]	582	1			T13	1		T17	10		T20	5
values[4]	681	1			T11	11		T25	5		T56	1
values[5]	697	1			T5	16		T56	1		T65	5
values[6]	698	1			T11	10		T12	5		T15	28
values[7]	698	1			T17	3		T137	8		T125	15
values[8]	881	1			T5	17		T12	25		T114	1
values[9]	106	1			T18	9		T23	4		T229	1
minimum	16037	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	10		T23	3		T114	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T17	12		T59	1		T24	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T1	3		T3	3		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	15		T114	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T4	9		T123	3		T147	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T23	11		T128	15		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	1		T17	10		T20	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	1		T23	17		T218	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	11		T56	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T25	3		T21	1		T23	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	7		T56	1		T65	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T122	1		T123	5		T201	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	14		T103	7		T60	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	10		T12	5		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T125	15		T122	12		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T17	3		T137	1		T198	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T114	1		T115	1		T60	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	4		T12	11		T208	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T18	9		T23	4		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T254	10		T259	3		T225	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15759	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T222	3		T260	11		T261	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T23	3		T111	13		T117	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T24	3		T137	7		T102	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1102	1			T3	29		T7	8		T21	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	13		T163	4		T149	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T4	7		T123	5		T112	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T23	2		T128	15		T209	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T15	3		T104	10		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T23	15		T218	15		T116	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T102	7		T27	2		T262	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T25	2		T23	16		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	9		T199	13		T205	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T122	4		T123	5		T205	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T15	14		T60	2		T118	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T150	2		T151	24		T188	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T122	18		T60	1		T128	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T137	7		T111	11		T112	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T60	3		T198	11		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	13		T12	14		T208	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T112	17		T249	8		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T254	2		T263	16		T264	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	3		T21	5		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T260	15		T261	4		T250	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T23	4		T60	2		T229	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T5	1		T12	11		T265	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	10		T21	4		T23	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T59	1		T24	8		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T1	3		T3	3		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T17	12		T120	1		T266	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	9		T123	3		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	15		T56	1		T23	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T17	10		T104	10		T153	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T23	17		T116	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	11		T13	1		T20	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T25	3		T21	1		T23	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	7		T56	2		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T122	1		T201	7		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	14		T65	5		T103	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	10		T115	1		T138	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T125	15		T122	12		T60	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	5		T17	3		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T18	9		T114	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	3		T208	13		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T60	3		T249	8		T267	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T5	11		T12	14		T254	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T258	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T21	4		T23	3		T207	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T24	3		T137	7		T102	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T3	29		T7	8		T21	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T163	4		T149	13		T268	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	7		T123	5		T161	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	13		T23	2		T128	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T104	10		T112	4		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T23	15		T116	2		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	3		T102	7		T27	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	2		T23	16		T137	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	9		T199	13		T205	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T122	4		T205	1		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	14		T60	2		T118	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T123	5		T150	2		T151	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T122	18		T60	1		T128	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T137	7		T111	11		T112	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T198	11		T112	17		T197	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	2		T208	17		T129	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	1		T23	4		T114	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T17	1		T59	1		T24	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T1	3		T3	32		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	14		T114	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	8		T123	6		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T23	3		T128	16		T209	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	1		T17	1		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T56	1		T23	16		T218	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	1		T56	1		T102	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T25	5		T21	1		T23	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	10		T56	1		T65	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T122	5		T123	6		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T15	21		T103	1		T60	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	1		T12	1		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T125	1		T122	20		T60	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T17	1		T137	8		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T114	1		T115	1		T60	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	15		T12	15		T208	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T18	1		T23	4		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T254	3		T259	1		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15905	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T222	1		T260	16		T261	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	9		T23	2		T125	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T17	11		T24	4		T113	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T19	19		T21	5		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	14		T163	6		T149	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	8		T123	2		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T23	10		T128	14		T197	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T17	9		T20	4		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T23	16		T218	12		T118	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	10		T27	3		T105	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T23	8		T269	8		T243	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	6		T65	4		T199	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T123	4		T201	6		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	7		T103	6		T60	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	9		T12	4		T138	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T125	14		T122	10		T128	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	2		T198	7		T111	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T198	13		T147	11		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	2		T12	10		T208	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T18	8		T112	4		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T254	9		T259	2		T225	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T21	2		T207	1		T270	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T222	2		T260	10		T261	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T23	4		T60	5		T229	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T5	12		T12	15		T265	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T258	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	1		T21	6		T23	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T59	1		T24	7		T137	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T1	3		T3	32		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	1		T120	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	8		T123	6		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	14		T56	1		T23	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	1		T104	11		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T23	16		T116	3		T220	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	1		T13	1		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	5		T21	1		T23	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	10		T56	2		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T122	5		T201	1		T205	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	21		T65	1		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T11	1		T115	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T125	1		T122	20		T60	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	1		T17	1		T137	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T18	1		T114	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	3		T208	18		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T270	11		T249	11		T267	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T12	10		T254	9		T259	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	9		T21	2		T23	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T24	4		T113	4		T139	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T19	19		T21	5		T103	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T17	11		T266	13		T163	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T4	8		T123	2		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	14		T23	10		T128	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	9		T104	9		T153	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T23	16		T118	7		T222	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	10		T20	4		T15	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T23	8		T218	12		T266	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	6		T199	14		T147	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T201	6		T269	8		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	7		T65	4		T103	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	9		T138	14		T123	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T125	14		T122	10		T128	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	4		T17	2		T198	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T18	8		T198	13		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	2		T208	12		T223	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28