Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21250

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3279

1

T4

16

T5

56

T11

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18790

1

T2

153

T4

20

T5

46

auto[1]

5739

1

T1

3

T3

32

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	171	1			T103	3		T150	3		T260	26
values[0]	32	1			T130	12		T211	7		T239	1
values[1]	614	1			T11	21		T12	5		T17	10
values[2]	790	1			T4	16		T56	1		T23	4
values[3]	540	1			T5	12		T122	18		T123	3
values[4]	621	1			T5	28		T56	1		T15	13
values[5]	2809	1			T1	3		T3	32		T5	5
values[6]	932	1			T12	25		T20	5		T23	32
values[7]	674	1			T18	9		T21	14		T23	26
values[8]	656	1			T5	16		T23	6		T24	11
values[9]	830	1			T11	10		T13	1		T17	15
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	615	1			T11	21		T12	5		T25	5
values[1]	690	1			T4	16		T5	12		T23	4
values[2]	625	1			T15	13		T122	18		T60	7
values[3]	2718	1			T1	3		T3	32		T5	28
values[4]	780	1			T5	5		T56	1		T21	1
values[5]	779	1			T12	25		T20	5		T23	32
values[6]	779	1			T5	16		T18	9		T21	14
values[7]	636	1			T23	6		T122	17		T103	7
values[8]	713	1			T13	1		T17	15		T21	8
values[9]	123	1			T11	10		T220	3		T154	12
minimum	16071	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	11		T56	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	10		T12	5		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T23	4		T114	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	9		T5	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	1		T60	5		T112	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T122	4		T123	1		T111	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T1	3		T3	3		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	15		T138	15		T197	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	3		T56	1		T23	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T21	1		T201	7		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	11		T125	15		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T20	5		T23	17		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T18	9		T67	1		T125	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	7		T21	7		T23	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T23	3		T103	7		T60	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T122	9		T128	15		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T17	12		T24	8		T103	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	1		T17	3		T21	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T154	12		T271	1		T157	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T11	10		T220	1		T152	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15777	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T17	10		T137	1		T198	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T208	17		T207	1		T216	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T25	2		T206	2		T226	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T199	13		T128	11		T200	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	7		T5	11		T137	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T15	12		T60	2		T112	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T122	14		T123	2		T111	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T3	29		T7	8		T221	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	13		T197	16		T203	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T23	2		T102	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T112	21		T197	2		T161	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	14		T102	9		T27	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T23	15		T209	1		T206	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T195	15		T232	26		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	9		T21	7		T23	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T23	3		T60	3		T104	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T122	8		T128	15		T205	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T24	3		T111	11		T218	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T21	4		T15	5		T123	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T157	2		T236	7		T235	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T220	2		T157	10		T192	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T137	7		T211	6		T263	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T103	3		T260	11		T228	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T150	1		T157	11		T192	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T130	12		T211	1		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	11		T138	1		T207	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	10		T12	5		T17	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T56	1		T23	4		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	9		T137	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T112	5		T202	1		T223	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T122	4		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T56	1		T15	1		T65	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	15		T138	15		T197	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T1	3		T3	3		T5	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T21	1		T229	1		T112	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	11		T125	15		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T20	5		T23	17		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T18	9		T125	10		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T21	7		T23	10		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T23	3		T24	8		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	7		T122	9		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T17	12		T60	2		T111	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T11	10		T13	1		T17	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T260	15		T249	8		T272	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T150	2		T157	10		T192	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T211	6		T273	7		T274	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T207	1		T154	15		T216	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	2		T137	7		T206	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T199	13		T128	11		T208	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T4	7		T137	8		T121	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T112	12		T38	1		T275	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	11		T122	14		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	12		T137	7		T60	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	13		T197	16		T150	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T3	29		T5	2		T7	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T112	17		T161	2		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	14		T102	7		T27	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T23	15		T209	1		T112	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T102	9		T241	13		T150	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T21	7		T23	16		T129	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T23	3		T24	3		T104	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	9		T122	8		T60	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T60	3		T111	11		T218	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T21	4		T15	5		T123	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	1		T56	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	1		T12	1		T25	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T23	4		T114	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	8		T5	12		T137	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	13		T60	4		T112	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T122	16		T123	3		T111	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T1	3		T3	32		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	14		T138	1		T197	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	3		T56	1		T23	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T21	1		T201	1		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	15		T125	1		T102	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T20	1		T23	16		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T18	1		T67	1		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	10		T21	9		T23	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T23	4		T103	1		T60	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T122	9		T128	16		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T17	1		T24	7		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	1		T17	1		T21	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T154	1		T271	1		T157	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T11	1		T220	3		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15916	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T17	1		T137	8		T198	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	10		T208	12		T207	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	9		T12	4		T201	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T199	14		T128	3		T200	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	8		T105	8		T110	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T60	3		T112	4		T118	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T122	2		T111	15		T243	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T19	19		T65	4		T224	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T5	14		T138	14		T197	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	2		T23	10		T123	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T201	6		T112	8		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	10		T125	14		T27	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T20	4		T23	16		T147	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T18	8		T125	9		T113	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	6		T21	5		T23	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T23	2		T103	6		T104	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T122	8		T128	14		T262	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T17	11		T24	4		T103	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	2		T21	2		T15	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T154	11		T157	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T11	9		T152	8		T157	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T154	13		T254	9		T238	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T17	9		T130	11		T240	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T103	1		T260	16		T228	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T150	3		T157	11		T192	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T130	1		T211	7		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	1		T138	1		T207	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	1		T12	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T56	1		T23	4		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	8		T137	9		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T112	13		T202	1		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	12		T122	16		T123	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T56	1		T15	13		T65	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	14		T138	1		T197	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T1	3		T3	32		T5	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T21	1		T229	1		T112	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T12	15		T125	1		T102	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T20	1		T23	16		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T18	1		T125	1		T102	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T21	9		T23	18		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T23	4		T24	7		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	10		T122	9		T60	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	1		T60	5		T111	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	1		T13	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T103	2		T260	10		T228	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T157	10		T192	11		T276	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T130	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	10		T207	1		T154	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	9		T12	4		T17	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T199	14		T128	3		T208	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	8		T105	8		T110	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T112	4		T223	14		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T122	2		T111	15		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T65	4		T60	3		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T5	14		T138	14		T197	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T5	2		T19	19		T23	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T112	4		T161	3		T154	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	10		T125	14		T27	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T20	4		T23	16		T201	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	8		T125	9		T113	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T21	5		T23	8		T153	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T23	2		T24	4		T103	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T5	6		T122	8		T128	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	11		T111	9		T218	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	9		T17	2		T21	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28