Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20801

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3728

1

T4

16

T5

28

T11

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18866

1

T2

153

T4

20

T5

74

auto[1]

5663

1

T1

3

T3

32

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	190	1			T17	3		T15	13		T67	1
values[0]	23	1			T277	23		-	-		-	-
values[1]	619	1			T4	16		T12	5		T20	5
values[2]	496	1			T102	8		T122	17		T113	5
values[3]	755	1			T5	16		T11	10		T56	1
values[4]	638	1			T18	9		T56	1		T23	19
values[5]	3006	1			T1	3		T3	32		T5	33
values[6]	651	1			T11	10		T17	12		T21	1
values[7]	797	1			T12	25		T21	14		T125	15
values[8]	632	1			T5	12		T13	1		T56	1
values[9]	862	1			T17	10		T23	26		T24	11
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	551	1			T12	5		T20	5		T15	15
values[1]	604	1			T5	16		T122	17		T113	5
values[2]	641	1			T11	10		T56	2		T15	9
values[3]	2835	1			T1	3		T3	32		T5	5
values[4]	831	1			T5	28		T11	11		T17	12
values[5]	664	1			T11	10		T21	1		T114	1
values[6]	734	1			T12	25		T13	1		T21	14
values[7]	667	1			T5	12		T56	1		T23	32
values[8]	816	1			T17	10		T23	26		T24	11
values[9]	66	1			T17	3		T15	13		T137	8
minimum	16120	1			T2	153		T4	36		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	5		T23	4		T105	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T20	5		T15	13		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T30	1		T154	12		T203	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	7		T122	9		T113	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T56	2		T23	11		T128	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	10		T15	6		T199	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T1	3		T3	3		T5	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T21	4		T125	10		T103	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	15		T11	11		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	12		T25	3		T123	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	10		T114	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T21	1		T103	3		T60	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T115	1		T122	3		T60	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	11		T13	1		T21	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T56	1		T65	5		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T23	17		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T114	1		T27	4		T198	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T17	10		T23	10		T24	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T15	1		T137	1		T139	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T17	3		T201	7		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15760	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T4	9		T147	12		T197	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T116	2		T30	2		T232	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	2		T102	7		T194	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T30	1		T203	3		T150	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	9		T122	8		T116	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T23	2		T128	15		T197	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	3		T199	13		T104	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T3	29		T5	2		T7	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T21	4		T128	11		T220	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	13		T102	9		T123	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T25	2		T123	5		T153	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T60	1		T197	2		T129	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T60	2		T111	13		T206	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T122	10		T60	3		T112	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	14		T21	7		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T118	7		T162	2		T211	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	11		T23	15		T137	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T27	2		T198	11		T226	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T23	16		T24	3		T122	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T15	12		T137	7		T278	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T251	2		T252	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T4	7		T205	13		T195	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T15	1		T198	14		T110	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T17	3		T67	1		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T277	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	5		T23	4		T105	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	9		T20	5		T15	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T30	1		T203	1		T279	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T102	1		T122	9		T113	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T56	1		T128	15		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	7		T11	10		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T18	9		T56	1		T23	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T103	7		T128	4		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1418	1			T1	3		T3	3		T5	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T25	3		T21	4		T125	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	10		T114	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	12		T21	1		T60	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T115	1		T122	3		T60	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	11		T21	7		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T56	1		T198	1		T118	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	1		T13	1		T23	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T65	5		T137	1		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T17	10		T23	10		T24	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T15	12		T198	11		T226	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T122	4		T250	7		T280	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T277	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T116	2		T30	2		T203	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	7		T15	2		T205	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T30	1		T203	3		T256	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T102	7		T122	8		T116	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T128	15		T197	16		T117	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	9		T15	3		T199	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T23	5		T209	1		T112	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T128	11		T220	2		T161	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T3	29		T5	15		T7	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T25	2		T21	4		T123	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T197	2		T129	2		T133	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T60	2		T111	13		T206	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T122	10		T60	4		T112	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	14		T21	7		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T118	7		T162	2		T211	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	11		T23	15		T111	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T137	7		T27	2		T212	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T23	16		T24	3		T137	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	1		T23	4		T105	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T20	1		T15	8		T102	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	2		T154	1		T203	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	10		T122	9		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T56	2		T23	3		T128	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	1		T15	6		T199	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T1	3		T3	32		T5	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T21	6		T125	1		T103	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	14		T11	1		T102	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	1		T25	5		T123	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	1		T114	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T21	1		T103	1		T60	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T115	1		T122	11		T60	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	15		T13	1		T21	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T56	1		T65	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	12		T23	16		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T114	1		T27	3		T198	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T17	1		T23	18		T24	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T15	13		T137	8		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T17	1		T201	1		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15910	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T4	8		T147	1		T197	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T12	4		T105	8		T30	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	4		T15	7		T113	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T154	11		T121	11		T232	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	6		T122	8		T113	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T23	10		T128	14		T197	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	9		T15	3		T199	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T5	2		T18	8		T19	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T21	2		T125	9		T103	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	14		T11	10		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	11		T123	4		T153	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	9		T113	10		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T103	2		T60	3		T198	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T122	2		T201	6		T112	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	10		T21	5		T125	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T65	4		T118	8		T222	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T23	16		T111	9		T206	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T27	3		T198	13		T110	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T17	9		T23	8		T24	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T139	6		T222	2		T281	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T17	2		T201	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T223	9		T233	8		T282	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T4	8		T147	11		T197	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T15	13		T198	12		T110	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T17	1		T67	1		T122	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T277	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	1		T23	4		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	8		T20	1		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T30	2		T203	4		T279	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T102	8		T122	9		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T56	1		T128	16		T197	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	10		T11	1		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T18	1		T56	1		T23	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T103	1		T128	12		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T1	3		T3	32		T5	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T25	5		T21	6		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	1		T114	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T17	1		T21	1		T60	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T115	1		T122	11		T60	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T12	15		T21	9		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T56	1		T198	1		T118	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	12		T13	1		T23	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T65	1		T137	8		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T17	1		T23	18		T24	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T198	13		T110	10		T139	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T17	2		T201	6		T250	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T277	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	4		T105	8		T30	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	8		T20	4		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T256	7		T283	8		T225	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T122	8		T113	4		T118	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T128	14		T197	13		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T5	6		T11	9		T15	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T18	8		T23	12		T153	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T103	6		T128	3		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T5	16		T11	10		T19	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T21	2		T125	9		T123	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	9		T113	10		T197	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T17	11		T60	3		T111	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T122	2		T201	6		T112	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	10		T21	5		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T118	8		T222	13		T130	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T23	16		T111	9		T206	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T65	4		T27	3		T222	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T17	9		T23	8		T24	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28