Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20956

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3573

1

T5

33

T11

10

T12

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18408

1

T2

151

T4

20

T5

30

auto[1]

6121

1

T1

3

T2

2

T3

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	405	1			T2	2		T16	3		T25	1
values[0]	82	1			T5	16		T23	13		T161	9
values[1]	697	1			T4	16		T11	10		T23	32
values[2]	2779	1			T1	3		T3	32		T6	1
values[3]	721	1			T5	28		T21	14		T114	1
values[4]	654	1			T17	10		T67	1		T102	10
values[5]	654	1			T15	9		T115	1		T60	7
values[6]	731	1			T20	5		T15	13		T23	6
values[7]	665	1			T12	25		T21	1		T59	1
values[8]	660	1			T5	5		T11	10		T17	15
values[9]	1010	1			T5	12		T11	11		T12	5
minimum	15471	1			T2	151		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	840	1			T4	16		T5	16		T11	10
values[1]	2871	1			T1	3		T3	32		T6	1
values[2]	686	1			T5	28		T21	14		T114	1
values[3]	691	1			T17	10		T15	9		T67	1
values[4]	687	1			T128	30		T147	12		T284	1
values[5]	685	1			T12	25		T20	5		T15	13
values[6]	628	1			T5	5		T11	10		T17	12
values[7]	573	1			T11	11		T12	5		T13	1
values[8]	785	1			T5	12		T56	1		T21	8
values[9]	180	1			T56	1		T197	11		T226	32
minimum	15903	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T4	9		T5	7		T11	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T65	5		T125	10		T122	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T1	3		T3	3		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	3		T56	1		T122	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	7		T114	1		T103	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	15		T198	8		T205	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T67	1		T27	4		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T17	10		T15	6		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T139	11		T200	13		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T128	15		T147	12		T284	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	1		T137	1		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	11		T20	5		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T17	12		T115	1		T104	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	3		T11	10		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T11	11		T17	3		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	5		T13	1		T18	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T199	15		T138	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T56	1		T21	4		T15	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T56	1		T197	11		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T226	16		T285	4		T286	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15733	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T149	13		T136	1		T245	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	7		T5	9		T23	33
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T122	8		T153	11		T161	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T3	29		T7	8		T221	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T25	2		T122	10		T198	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T21	7		T203	9		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	13		T205	14		T188	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T27	2		T220	2		T118	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T15	3		T102	9		T60	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T200	3		T150	14		T287	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T128	15		T112	17		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	12		T137	8		T102	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	14		T23	3		T137	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T104	10		T112	4		T197	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T5	2		T60	1		T218	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T60	3		T197	2		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T137	7		T122	4		T129	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	11		T199	13		T123	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T21	4		T15	2		T24	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T129	1		T195	11		T288	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T226	16		T286	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T149	7		T136	7		T245	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T2	2		T16	3		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T5	7		T23	11		T171	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T161	7		T136	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	9		T11	10		T23	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T65	5		T125	10		T122	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T1	3		T3	3		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T25	3		T56	1		T122	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T21	7		T114	1		T103	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	15		T198	22		T205	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T67	1		T27	4		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T17	10		T102	1		T207	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T220	1		T150	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	6		T115	1		T60	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	1		T102	1		T110	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T20	5		T23	3		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T59	1		T137	1		T104	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	11		T21	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	15		T115	1		T60	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	3		T11	10		T18	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T5	1		T11	11		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T12	5		T13	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15333	1			T2	148		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T214	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T5	9		T23	2		T171	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T161	2		T136	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	7		T23	15		T200	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T122	8		T208	17		T118	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T3	29		T7	8		T23	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	2		T122	10		T128	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T21	7		T154	15		T243	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	13		T198	11		T205	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	2		T203	9		T118	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T102	9		T207	1		T111	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T220	2		T150	14		T287	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	3		T60	2		T128	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	12		T102	7		T200	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T23	3		T123	2		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T137	8		T104	10		T197	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	14		T137	7		T116	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	3		T112	4		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	2		T24	3		T137	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	11		T199	13		T123	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T21	4		T15	2		T226	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T4	8		T5	10		T11	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T65	1		T125	1		T122	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T1	3		T3	32		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T25	5		T56	1		T122	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	9		T114	1		T103	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	14		T198	1		T205	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T67	1		T27	3		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T17	1		T15	6		T102	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T139	1		T200	4		T150	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T128	16		T147	1		T284	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	13		T137	9		T102	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	15		T20	1		T23	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T17	1		T115	1		T104	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	3		T11	1		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	1		T17	1		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T13	1		T18	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	12		T199	14		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T56	1		T21	6		T15	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T56	1		T197	1		T129	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T226	17		T285	1		T286	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15863	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T149	8		T136	8		T245	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	8		T5	6		T11	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T65	4		T125	9		T122	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T19	19		T224	19		T109	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T122	2		T198	13		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T21	5		T103	6		T222	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	14		T198	7		T205	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T27	3		T118	7		T157	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	9		T15	3		T60	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T139	10		T200	12		T289	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T128	14		T147	11		T112	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T110	10		T113	4		T194	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	10		T20	4		T23	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T17	11		T104	9		T147	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	2		T11	9		T218	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T11	10		T17	2		T113	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	4		T18	8		T129	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T199	14		T138	14		T123	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T21	2		T15	7		T24	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T197	10		T244	12		T290	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T226	15		T285	3		T286	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T152	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T149	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T2	2		T16	3		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T5	10		T23	3		T171	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T161	6		T136	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	8		T11	1		T23	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T65	1		T125	1		T122	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T1	3		T3	32		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T25	5		T56	1		T122	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	9		T114	1		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	14		T198	13		T205	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T67	1		T27	3		T203	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T17	1		T102	10		T207	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T220	3		T150	15		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T15	6		T115	1		T60	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	13		T102	8		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T20	1		T23	4		T123	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T59	1		T137	9		T104	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	15		T21	1		T137	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T17	2		T115	1		T60	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	3		T11	1		T18	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T5	12		T11	1		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	1		T13	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15471	1			T2	151		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T214	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T5	6		T23	10		T171	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T161	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	8		T11	9		T23	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T65	4		T125	9		T122	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T19	19		T23	8		T224	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T122	2		T128	3		T111	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T21	5		T103	6		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	14		T198	20		T205	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T27	3		T118	7		T222	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	9		T207	1		T111	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T228	10		T162	4		T291	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	3		T60	3		T128	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T110	10		T113	4		T139	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T20	4		T23	2		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T104	9		T147	11		T197	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	10		T113	10		T266	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T17	13		T112	4		T113	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	2		T11	9		T18	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	10		T199	14		T138	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T12	4		T21	2		T15	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28