Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21164

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3365

1

T4

16

T5

45

T11

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19057

1

T2

153

T4

36

T5

46

auto[1]

5472

1

T1

3

T3

32

T5

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	54	1			T112	17		T292	1		T293	1
values[0]	33	1			T125	10		T294	13		T295	1
values[1]	537	1			T5	16		T11	11		T12	25
values[2]	814	1			T13	1		T17	3		T56	1
values[3]	568	1			T5	5		T56	1		T23	6
values[4]	750	1			T4	16		T5	28		T12	5
values[5]	754	1			T20	5		T15	15		T23	4
values[6]	704	1			T25	5		T15	13		T24	11
values[7]	515	1			T21	1		T125	15		T102	8
values[8]	2690	1			T1	3		T3	32		T6	1
values[9]	1250	1			T5	12		T11	10		T17	12
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	826	1			T5	16		T11	11		T12	25
values[1]	621	1			T17	3		T56	2		T21	22
values[2]	683	1			T5	5		T56	1		T137	17
values[3]	633	1			T4	16		T12	5		T17	10
values[4]	805	1			T5	28		T20	5		T23	4
values[5]	782	1			T25	5		T15	13		T24	11
values[6]	2592	1			T1	3		T3	32		T6	1
values[7]	485	1			T59	1		T65	5		T60	7
values[8]	1044	1			T5	12		T11	10		T17	12
values[9]	181	1			T147	12		T139	7		T119	1
minimum	15877	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	7		T18	9		T23	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	11		T12	11		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T17	3		T56	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T56	1		T21	11		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T137	1		T115	1		T112	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	3		T56	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	5		T15	13		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	9		T17	10		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T114	1		T122	3		T103	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	15		T20	5		T23	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T27	4		T105	9		T123	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T25	3		T15	1		T24	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T1	3		T3	3		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	10		T21	1		T296	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T65	5		T138	1		T198	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T59	1		T60	5		T199	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T15	6		T23	21		T147	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	1		T11	10		T17	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T147	12		T139	7		T266	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T119	1		T120	1		T297	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T122	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	9		T23	15		T205	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	14		T137	7		T122	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T153	11		T197	2		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T21	11		T23	3		T112	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T137	8		T112	4		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	2		T137	7		T104	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	2		T128	15		T123	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	7		T102	9		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T122	10		T60	1		T207	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	13		T197	16		T116	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T27	2		T123	5		T208	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T25	2		T15	12		T24	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T3	29		T7	8		T221	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T150	6		T140	24		T164	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T198	11		T206	5		T200	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T60	2		T199	13		T149	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T15	3		T23	18		T162	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	11		T112	12		T200	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T298	7		T286	10		T62	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T299	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T122	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T292	1		T293	1		T252	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T112	5		T299	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T294	13		T295	1		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T125	10		T301	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	7		T18	9		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	11		T12	11		T122	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T17	3		T23	17		T113	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	1		T56	1		T21	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T56	1		T137	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	3		T23	3		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	5		T26	1		T128	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	9		T5	15		T17	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	13		T114	1		T122	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T20	5		T23	4		T198	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T103	7		T27	4		T105	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T25	3		T15	1		T24	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T125	15		T110	11		T205	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T21	1		T102	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T1	3		T3	3		T6	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	10		T199	15		T296	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T15	6		T23	21		T65	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T5	1		T11	10		T17	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T252	9		T302	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T112	12		T299	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T300	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T5	9		T262	6		T254	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	14		T122	12		T128	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T23	15		T197	2		T205	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	11		T137	7		T60	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T137	8		T153	11		T197	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	2		T23	3		T137	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T128	15		T218	15		T112	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	7		T5	13		T102	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	2		T122	10		T60	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T197	16		T116	14		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T27	2		T123	5		T208	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T25	2		T15	12		T24	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T206	2		T200	4		T212	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T102	7		T140	24		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T3	29		T7	8		T221	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T199	13		T150	6		T149	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T15	3		T23	18		T206	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T5	11		T60	2		T200	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	10		T18	1		T23	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T11	1		T12	15		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T17	1		T56	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T56	1		T21	15		T23	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T137	9		T115	1		T112	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	3		T56	1		T137	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T15	8		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	8		T17	1		T102	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T114	1		T122	11		T103	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	14		T20	1		T23	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T27	3		T105	1		T123	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T25	5		T15	13		T24	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T1	3		T3	32		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	1		T21	1		T296	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T65	1		T138	1		T198	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T59	1		T60	4		T199	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T15	6		T23	21		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T5	12		T11	1		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T147	1		T139	1		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T119	1		T120	1		T297	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T122	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	6		T18	8		T23	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	10		T12	10		T125	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T17	2		T153	7		T113	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T21	7		T23	2		T103	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T112	4		T113	4		T222	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	2		T104	9		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	4		T15	7		T128	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T4	8		T17	9		T138	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T122	2		T103	6		T201	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	14		T20	4		T198	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T27	3		T105	8		T123	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T24	4		T139	8		T226	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T19	19		T125	14		T224	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T11	9		T164	3		T285	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T65	4		T198	13		T205	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T60	3		T199	14		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	3		T23	18		T147	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	9		T17	11		T112	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T147	11		T139	6		T266	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T122	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T292	1		T293	1		T252	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T112	13		T299	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T294	1		T295	1		T300	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T125	1		T301	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T5	10		T18	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	1		T12	15		T122	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T17	1		T23	16		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	1		T56	1		T21	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T56	1		T137	9		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	3		T23	4		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T26	1		T128	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	8		T5	14		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T15	8		T114	1		T122	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	1		T23	4		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T103	1		T27	3		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T25	5		T15	13		T24	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T125	1		T110	1		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T21	1		T102	8		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T1	3		T3	32		T6	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	1		T199	14		T296	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T15	6		T23	21		T65	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T5	12		T11	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T112	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T294	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T125	9		T301	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	6		T18	8		T129	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	10		T12	10		T122	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	2		T23	16		T113	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T21	7		T103	2		T112	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T153	7		T113	4		T266	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	2		T23	2		T104	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	4		T128	14		T218	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	8		T5	14		T17	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	7		T122	2		T123	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T20	4		T198	7		T197	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T103	6		T27	3		T105	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T24	4		T153	6		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T125	14		T110	10		T205	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T232	13		T164	3		T285	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T19	19		T224	19		T109	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	9		T199	14		T222	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T15	3		T23	18		T65	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	9		T17	11		T60	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28