Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24529

1

T1

3

T2

153

T3

32

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21237

1

T1

3

T2

153

T3

32

auto[ADC_CTRL_FILTER_COND_OUT]

3292

1

T5

56

T12

5

T17

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18683

1

T2

153

T4

20

T5

57

auto[1]

5846

1

T1

3

T3

32

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20515

1

T1

3

T2

150

T3

3

auto[1]

4014

1

T2

3

T3

29

T4

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	29	1			T130	12		T148	1		T256	5
values[0]	152	1			T21	14		T23	13		T223	10
values[1]	605	1			T23	6		T137	9		T122	13
values[2]	663	1			T5	5		T11	10		T17	10
values[3]	449	1			T5	12		T12	5		T17	12
values[4]	2777	1			T1	3		T3	32		T6	1
values[5]	889	1			T4	16		T56	1		T15	22
values[6]	702	1			T11	10		T59	1		T198	8
values[7]	531	1			T5	28		T13	1		T25	5
values[8]	652	1			T5	16		T20	5		T102	10
values[9]	1220	1			T11	11		T12	25		T17	3
minimum	15860	1			T2	153		T4	20		T5	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	879	1			T21	14		T15	15		T23	19
values[1]	616	1			T11	10		T17	10		T56	1
values[2]	551	1			T5	17		T12	5		T17	12
values[3]	2849	1			T1	3		T3	32		T6	1
values[4]	932	1			T4	16		T15	13		T59	1
values[5]	515	1			T5	28		T11	10		T25	5
values[6]	641	1			T13	1		T20	5		T67	1
values[7]	566	1			T5	16		T12	25		T17	3
values[8]	908	1			T11	11		T23	26		T24	11
values[9]	211	1			T122	17		T27	6		T128	30
minimum	15861	1			T2	153		T4	20		T5	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

3720

1

T4

8

T5

22

T11

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	13		T23	14		T122	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T21	7		T137	1		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	10		T17	10		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T21	4		T23	17		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	3		T17	12		T110	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T12	5		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T1	3		T3	3		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T138	15		T226	16		T303	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	9		T15	1		T59	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T65	5		T125	25		T198	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	10		T25	3		T23	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	15		T56	1		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	1		T20	5		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T67	1		T102	1		T208	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	11		T137	1		T103	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	7		T17	3		T18	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T11	11		T115	2		T111	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T23	10		T24	8		T60	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T27	4		T128	15		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T122	9		T303	1		T171	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T305	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	2		T23	5		T122	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	7		T137	8		T218	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T104	10		T206	5		T306	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T21	4		T23	15		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	2		T209	1		T188	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	11		T198	11		T260	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T3	29		T7	8		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T226	16		T268	12		T156	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	7		T15	12		T206	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T153	11		T197	4		T194	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T25	2		T128	11		T123	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	13		T154	15		T129	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T102	9		T30	2		T200	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T102	7		T208	17		T220	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	14		T137	7		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T5	9		T111	11		T153	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T111	13		T205	1		T154	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T23	16		T24	3		T60	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T27	2		T128	15		T304	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T122	8		T171	15		T298	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T130	12		T148	1		T278	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T256	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T23	11		T223	10		T157	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T21	7		T155	12		T233	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T23	3		T122	3		T197	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T137	1		T26	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	3		T11	10		T17	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T21	4		T23	17		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T17	12		T56	1		T104	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	1		T12	5		T105	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T1	3		T3	3		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T114	1		T125	10		T138	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T4	9		T56	1		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T65	5		T125	15		T201	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	10		T59	1		T123	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T198	8		T229	1		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	1		T25	3		T23	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	15		T56	1		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T20	5		T102	1		T103	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	7		T103	7		T208	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T11	11		T12	11		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T17	3		T18	9		T23	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15722	1			T2	150		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T278	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T256	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T23	2		T157	9		T213	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T21	7		T155	4		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T23	3		T122	10		T197	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T137	8		T218	15		T112	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	2		T15	2		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T21	4		T23	15		T137	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T104	10		T209	1		T206	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T5	11		T260	15		T149	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1133	1			T3	29		T7	8		T221	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T198	11		T268	12		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	7		T15	15		T199	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T153	11		T226	16		T194	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T123	5		T117	15		T203	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T197	4		T154	15		T129	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T25	2		T128	11		T203	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	13		T102	7		T220	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T102	9		T123	2		T112	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	9		T208	17		T111	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	14		T137	7		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T23	16		T24	3		T122	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	3		T21	1		T15	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T15	8		T23	7		T122	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T21	9		T137	9		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T17	1		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T21	6		T23	16		T137	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	3		T17	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	12		T12	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T1	3		T3	32		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	1		T226	17		T303	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	8		T15	13		T59	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T65	1		T125	2		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T25	5		T23	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	14		T56	1		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	1		T20	1		T102	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T67	1		T102	8		T208	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	15		T137	8		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	10		T17	1		T18	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	1		T115	2		T111	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T23	18		T24	7		T60	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T27	3		T128	16		T304	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T122	9		T303	1		T171	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T305	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	7		T23	12		T122	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T21	5		T147	11		T218	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	9		T17	9		T104	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T21	2		T23	16		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T5	2		T17	11		T110	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	4		T105	8		T198	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T19	19		T15	3		T224	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T138	14		T226	15		T268	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	8		T206	2		T228	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T65	4		T125	23		T198	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	9		T128	3		T123	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T5	14		T154	13		T228	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T20	4		T113	2		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T208	12		T113	10		T269	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	10		T103	2		T112	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	6		T17	2		T18	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	10		T111	15		T153	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T23	8		T24	4		T60	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T27	3		T128	14		T298	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T122	8		T171	20		T291	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T130	1		T148	1		T278	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T256	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T23	3		T223	1		T157	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T21	9		T155	10		T233	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T23	4		T122	11		T197	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T137	9		T26	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	3		T11	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T21	6		T23	16		T137	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T17	1		T56	1		T104	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T5	12		T12	1		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1475	1			T1	3		T3	32		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T114	1		T125	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	8		T56	1		T15	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T65	1		T125	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	1		T59	1		T123	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T198	1		T229	1		T197	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	1		T25	5		T23	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	14		T56	1		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	1		T102	10		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	10		T103	1		T208	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T11	1		T12	15		T137	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T17	1		T18	1		T23	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15860	1			T2	153		T4	20		T5	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T130	11		T278	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T23	10		T223	9		T157	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T21	5		T155	6		T233	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T23	2		T122	2		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T218	12		T112	4		T222	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T11	9		T17	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T21	2		T23	16		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T17	11		T104	9		T139	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T12	4		T105	8		T266	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T19	19		T224	19		T109	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T125	9		T138	14		T198	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	8		T15	3		T199	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T65	4		T125	14		T201	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	9		T123	4		T270	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T198	7		T154	13		T228	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T128	3		T113	2		T118	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T5	14		T113	10		T269	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T20	4		T103	2		T153	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T5	6		T103	6		T208	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	10		T12	10		T27	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T17	2		T18	8		T23	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20809

1

T1

3

T2

153

T3

32

auto[1]

auto[0]

3720

1

T4

8

T5

22

T11

28