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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.58 98.98 95.69 100.00 100.00 98.18 98.64 91.54


Total test records in report: 910
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T791 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3739466096 Feb 28 04:18:01 PM PST 24 Feb 28 04:18:07 PM PST 24 545152963 ps
T74 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2654882055 Feb 28 04:17:49 PM PST 24 Feb 28 04:17:51 PM PST 24 478485510 ps
T792 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3324135075 Feb 28 04:17:40 PM PST 24 Feb 28 04:17:42 PM PST 24 349709569 ps
T34 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3580583064 Feb 28 04:17:37 PM PST 24 Feb 28 04:17:43 PM PST 24 4702069380 ps
T793 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.211903518 Feb 28 04:17:41 PM PST 24 Feb 28 04:17:42 PM PST 24 316819681 ps
T75 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1563191035 Feb 28 04:17:50 PM PST 24 Feb 28 04:17:52 PM PST 24 419312295 ps
T76 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1521174857 Feb 28 04:17:38 PM PST 24 Feb 28 04:17:41 PM PST 24 1145043194 ps
T36 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3294139788 Feb 28 04:18:00 PM PST 24 Feb 28 04:18:12 PM PST 24 4469946690 ps
T37 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3992384353 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:34 PM PST 24 4566276231 ps
T55 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1488338394 Feb 28 04:17:40 PM PST 24 Feb 28 04:17:42 PM PST 24 440223036 ps
T794 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3825800146 Feb 28 04:19:04 PM PST 24 Feb 28 04:19:05 PM PST 24 501756184 ps
T77 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1161914 Feb 28 04:17:34 PM PST 24 Feb 28 04:17:36 PM PST 24 1084116519 ps
T95 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2596369122 Feb 28 04:17:45 PM PST 24 Feb 28 04:18:12 PM PST 24 25319359426 ps
T96 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2097640772 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:19 PM PST 24 736661828 ps
T795 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2632981172 Feb 28 04:17:58 PM PST 24 Feb 28 04:17:59 PM PST 24 410249071 ps
T90 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1369860459 Feb 28 04:18:01 PM PST 24 Feb 28 04:18:03 PM PST 24 375023451 ps
T796 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.318954435 Feb 28 04:17:50 PM PST 24 Feb 28 04:17:52 PM PST 24 383258830 ps
T40 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.859497095 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:43 PM PST 24 4589881583 ps
T41 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.270976134 Feb 28 04:17:34 PM PST 24 Feb 28 04:17:37 PM PST 24 482388286 ps
T797 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.581083464 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:32 PM PST 24 485458578 ps
T798 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.434179256 Feb 28 04:17:49 PM PST 24 Feb 28 04:17:52 PM PST 24 473808273 ps
T100 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1277185594 Feb 28 04:17:44 PM PST 24 Feb 28 04:17:48 PM PST 24 4194526314 ps
T69 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4178013148 Feb 28 04:17:50 PM PST 24 Feb 28 04:18:12 PM PST 24 7627092014 ps
T799 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3858982434 Feb 28 04:17:56 PM PST 24 Feb 28 04:17:57 PM PST 24 374977647 ps
T70 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1860250050 Feb 28 04:17:48 PM PST 24 Feb 28 04:17:51 PM PST 24 1116890257 ps
T91 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1939741813 Feb 28 04:17:53 PM PST 24 Feb 28 04:17:55 PM PST 24 2781791015 ps
T71 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3221238279 Feb 28 04:17:41 PM PST 24 Feb 28 04:17:43 PM PST 24 735118569 ps
T92 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2755004949 Feb 28 04:17:38 PM PST 24 Feb 28 04:17:42 PM PST 24 4490368150 ps
T800 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2537202354 Feb 28 04:17:26 PM PST 24 Feb 28 04:17:28 PM PST 24 1238613709 ps
T801 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1172345600 Feb 28 04:17:40 PM PST 24 Feb 28 04:17:43 PM PST 24 575681030 ps
T93 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1714267222 Feb 28 04:17:57 PM PST 24 Feb 28 04:18:03 PM PST 24 2434109553 ps
T802 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1835590161 Feb 28 04:17:47 PM PST 24 Feb 28 04:18:00 PM PST 24 637664463 ps
T803 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3209039029 Feb 28 04:17:27 PM PST 24 Feb 28 04:17:30 PM PST 24 1507004322 ps
T328 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2984749384 Feb 28 04:17:43 PM PST 24 Feb 28 04:17:47 PM PST 24 4457966989 ps
T804 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.857455985 Feb 28 04:18:03 PM PST 24 Feb 28 04:18:04 PM PST 24 412007334 ps
T805 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3204675696 Feb 28 04:17:25 PM PST 24 Feb 28 04:17:26 PM PST 24 597859233 ps
T97 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3925708816 Feb 28 04:17:40 PM PST 24 Feb 28 04:17:43 PM PST 24 457708113 ps
T806 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3113187701 Feb 28 04:17:57 PM PST 24 Feb 28 04:17:58 PM PST 24 352052693 ps
T807 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1134357483 Feb 28 04:17:34 PM PST 24 Feb 28 04:17:36 PM PST 24 502786136 ps
T808 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.767406298 Feb 28 04:17:47 PM PST 24 Feb 28 04:17:54 PM PST 24 9032469742 ps
T78 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4203373361 Feb 28 04:17:39 PM PST 24 Feb 28 04:17:40 PM PST 24 595361067 ps
T94 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3912035234 Feb 28 04:17:55 PM PST 24 Feb 28 04:18:07 PM PST 24 4923011398 ps
T809 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1586205690 Feb 28 04:17:43 PM PST 24 Feb 28 04:17:45 PM PST 24 3988754313 ps
T79 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1694569589 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:18 PM PST 24 609837226 ps
T80 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1220410296 Feb 28 04:19:03 PM PST 24 Feb 28 04:19:04 PM PST 24 395779125 ps
T810 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3294868908 Feb 28 04:19:07 PM PST 24 Feb 28 04:19:26 PM PST 24 4930492622 ps
T811 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1965887991 Feb 28 04:17:45 PM PST 24 Feb 28 04:17:47 PM PST 24 447098261 ps
T98 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2833140432 Feb 28 04:17:25 PM PST 24 Feb 28 04:17:28 PM PST 24 457813120 ps
T812 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2117706712 Feb 28 04:17:39 PM PST 24 Feb 28 04:17:42 PM PST 24 522610119 ps
T813 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2595448673 Feb 28 04:17:40 PM PST 24 Feb 28 04:17:42 PM PST 24 434597519 ps
T81 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4033748070 Feb 28 04:18:15 PM PST 24 Feb 28 04:18:17 PM PST 24 438570560 ps
T327 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.486339518 Feb 28 04:19:03 PM PST 24 Feb 28 04:19:15 PM PST 24 4467169931 ps
T814 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2622736795 Feb 28 04:17:24 PM PST 24 Feb 28 04:17:25 PM PST 24 521186109 ps
T815 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2319924098 Feb 28 04:18:22 PM PST 24 Feb 28 04:18:23 PM PST 24 587818711 ps
T816 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3564366094 Feb 28 04:17:46 PM PST 24 Feb 28 04:17:49 PM PST 24 550466996 ps
T817 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.28787207 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:40 PM PST 24 2282570061 ps
T818 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3395253207 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:32 PM PST 24 406871866 ps
T819 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1442160301 Feb 28 04:17:55 PM PST 24 Feb 28 04:17:57 PM PST 24 380061052 ps
T82 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2554703946 Feb 28 04:17:39 PM PST 24 Feb 28 04:17:40 PM PST 24 479641596 ps
T99 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.660589960 Feb 28 04:17:41 PM PST 24 Feb 28 04:17:44 PM PST 24 590155079 ps
T820 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.616877553 Feb 28 04:18:18 PM PST 24 Feb 28 04:18:20 PM PST 24 527220138 ps
T821 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2725914015 Feb 28 04:18:04 PM PST 24 Feb 28 04:18:05 PM PST 24 575180393 ps
T822 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1544101236 Feb 28 04:17:42 PM PST 24 Feb 28 04:17:48 PM PST 24 4069039680 ps
T83 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2954534719 Feb 28 04:18:43 PM PST 24 Feb 28 04:18:50 PM PST 24 590026831 ps
T823 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.921728595 Feb 28 04:17:56 PM PST 24 Feb 28 04:17:57 PM PST 24 444999403 ps
T824 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1713022837 Feb 28 04:18:07 PM PST 24 Feb 28 04:18:09 PM PST 24 426515990 ps
T825 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2036950227 Feb 28 04:17:23 PM PST 24 Feb 28 04:17:25 PM PST 24 2397533324 ps
T826 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2972577685 Feb 28 04:17:47 PM PST 24 Feb 28 04:17:50 PM PST 24 397350993 ps
T827 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3159138231 Feb 28 04:17:33 PM PST 24 Feb 28 04:17:36 PM PST 24 1975421624 ps
T828 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3683411536 Feb 28 04:17:58 PM PST 24 Feb 28 04:18:01 PM PST 24 590900644 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3041393893 Feb 28 04:17:59 PM PST 24 Feb 28 04:18:00 PM PST 24 586180829 ps
T830 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2038382525 Feb 28 04:17:49 PM PST 24 Feb 28 04:17:54 PM PST 24 744652249 ps
T831 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3148443515 Feb 28 04:17:28 PM PST 24 Feb 28 04:17:30 PM PST 24 440974481 ps
T832 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1382325590 Feb 28 04:17:58 PM PST 24 Feb 28 04:18:00 PM PST 24 528366157 ps
T833 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2408255605 Feb 28 04:17:54 PM PST 24 Feb 28 04:17:55 PM PST 24 395126882 ps
T834 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1260822528 Feb 28 04:17:46 PM PST 24 Feb 28 04:17:48 PM PST 24 525958857 ps
T835 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2836995436 Feb 28 04:17:32 PM PST 24 Feb 28 04:17:33 PM PST 24 385856673 ps
T836 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.751303141 Feb 28 04:18:06 PM PST 24 Feb 28 04:18:08 PM PST 24 428773794 ps
T837 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.129597151 Feb 28 04:18:04 PM PST 24 Feb 28 04:18:06 PM PST 24 417066707 ps
T838 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.224731360 Feb 28 04:17:31 PM PST 24 Feb 28 04:17:38 PM PST 24 4620799851 ps
T839 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3442375585 Feb 28 04:17:54 PM PST 24 Feb 28 04:17:55 PM PST 24 348880125 ps
T840 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3939582627 Feb 28 04:17:48 PM PST 24 Feb 28 04:17:52 PM PST 24 455395020 ps
T841 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4196033083 Feb 28 04:17:48 PM PST 24 Feb 28 04:17:49 PM PST 24 539796826 ps
T842 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1282550645 Feb 28 04:17:19 PM PST 24 Feb 28 04:17:24 PM PST 24 2070688951 ps
T843 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4058984881 Feb 28 04:17:33 PM PST 24 Feb 28 04:17:34 PM PST 24 560500262 ps
T844 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3411174202 Feb 28 04:17:37 PM PST 24 Feb 28 04:17:38 PM PST 24 523475861 ps
T845 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3932469558 Feb 28 04:18:10 PM PST 24 Feb 28 04:18:11 PM PST 24 394431745 ps
T846 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4212384697 Feb 28 04:17:19 PM PST 24 Feb 28 04:18:24 PM PST 24 27025533714 ps
T847 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.730218623 Feb 28 04:17:47 PM PST 24 Feb 28 04:17:49 PM PST 24 448548825 ps
T84 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2785538251 Feb 28 04:17:19 PM PST 24 Feb 28 04:18:07 PM PST 24 26362073790 ps
T848 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.61380247 Feb 28 04:17:29 PM PST 24 Feb 28 04:17:32 PM PST 24 522683103 ps
T849 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4057949651 Feb 28 04:17:35 PM PST 24 Feb 28 04:17:37 PM PST 24 332923227 ps
T850 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2536028711 Feb 28 04:17:29 PM PST 24 Feb 28 04:17:31 PM PST 24 291232363 ps
T851 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1844992853 Feb 28 04:18:09 PM PST 24 Feb 28 04:18:11 PM PST 24 410325701 ps
T852 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1209846638 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:32 PM PST 24 467316703 ps
T87 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.443957340 Feb 28 04:19:07 PM PST 24 Feb 28 04:19:09 PM PST 24 542735089 ps
T853 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2792136563 Feb 28 04:17:47 PM PST 24 Feb 28 04:17:49 PM PST 24 395228990 ps
T854 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4278062946 Feb 28 04:18:05 PM PST 24 Feb 28 04:18:07 PM PST 24 843229551 ps
T855 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.908745243 Feb 28 04:18:11 PM PST 24 Feb 28 04:18:12 PM PST 24 513232455 ps
T856 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1847171203 Feb 28 04:17:50 PM PST 24 Feb 28 04:18:02 PM PST 24 4859892049 ps
T857 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.67376099 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:19 PM PST 24 1224348474 ps
T858 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3402714317 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:20 PM PST 24 4404155541 ps
T859 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2461160039 Feb 28 04:17:54 PM PST 24 Feb 28 04:17:56 PM PST 24 423477808 ps
T329 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.162109515 Feb 28 04:17:27 PM PST 24 Feb 28 04:17:31 PM PST 24 4553405060 ps
T860 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.77712624 Feb 28 04:17:38 PM PST 24 Feb 28 04:17:40 PM PST 24 356895913 ps
T861 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2786330675 Feb 28 04:17:53 PM PST 24 Feb 28 04:17:54 PM PST 24 425537554 ps
T862 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4120909630 Feb 28 04:17:32 PM PST 24 Feb 28 04:17:34 PM PST 24 442709147 ps
T863 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.414469433 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:32 PM PST 24 532598045 ps
T85 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.154622602 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:32 PM PST 24 734752164 ps
T864 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2645305906 Feb 28 04:17:59 PM PST 24 Feb 28 04:18:00 PM PST 24 365370813 ps
T865 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.762887260 Feb 28 04:18:12 PM PST 24 Feb 28 04:18:13 PM PST 24 463119345 ps
T866 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1787426851 Feb 28 04:17:37 PM PST 24 Feb 28 04:17:40 PM PST 24 3581674780 ps
T867 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2650937535 Feb 28 04:17:40 PM PST 24 Feb 28 04:17:44 PM PST 24 4660821087 ps
T868 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2216548541 Feb 28 04:17:50 PM PST 24 Feb 28 04:17:58 PM PST 24 2033105687 ps
T869 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3067821985 Feb 28 04:17:36 PM PST 24 Feb 28 04:17:38 PM PST 24 721365023 ps
T870 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4065573035 Feb 28 04:17:54 PM PST 24 Feb 28 04:17:55 PM PST 24 428946012 ps
T871 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.309046720 Feb 28 04:17:40 PM PST 24 Feb 28 04:17:52 PM PST 24 8375875495 ps
T872 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2026512374 Feb 28 04:17:52 PM PST 24 Feb 28 04:17:54 PM PST 24 494248127 ps
T873 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1151818000 Feb 28 04:17:37 PM PST 24 Feb 28 04:17:40 PM PST 24 1005804688 ps
T874 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3086852829 Feb 28 04:18:10 PM PST 24 Feb 28 04:18:12 PM PST 24 497003639 ps
T86 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.918552809 Feb 28 04:17:41 PM PST 24 Feb 28 04:17:43 PM PST 24 486176489 ps
T875 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1315418313 Feb 28 04:17:49 PM PST 24 Feb 28 04:17:52 PM PST 24 410716970 ps
T876 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1327289681 Feb 28 04:19:04 PM PST 24 Feb 28 04:19:05 PM PST 24 545053795 ps
T88 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2512842458 Feb 28 04:17:50 PM PST 24 Feb 28 04:17:52 PM PST 24 339381531 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3297589403 Feb 28 04:17:38 PM PST 24 Feb 28 04:17:40 PM PST 24 536740274 ps
T878 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1239024311 Feb 28 04:17:48 PM PST 24 Feb 28 04:17:49 PM PST 24 493366085 ps
T89 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3002115578 Feb 28 04:17:22 PM PST 24 Feb 28 04:17:26 PM PST 24 1457649108 ps
T879 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3320111447 Feb 28 04:17:50 PM PST 24 Feb 28 04:18:01 PM PST 24 3852933821 ps
T880 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.205949314 Feb 28 04:18:02 PM PST 24 Feb 28 04:18:05 PM PST 24 472244395 ps
T881 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3766265657 Feb 28 04:17:33 PM PST 24 Feb 28 04:17:34 PM PST 24 572485434 ps
T882 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3679119035 Feb 28 04:18:03 PM PST 24 Feb 28 04:18:04 PM PST 24 430736181 ps
T330 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3665095661 Feb 28 04:17:34 PM PST 24 Feb 28 04:18:00 PM PST 24 8253737043 ps
T883 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1750311524 Feb 28 04:17:51 PM PST 24 Feb 28 04:17:57 PM PST 24 4420204205 ps
T884 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1712374677 Feb 28 04:17:53 PM PST 24 Feb 28 04:17:55 PM PST 24 374979276 ps
T885 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2342676305 Feb 28 04:17:37 PM PST 24 Feb 28 04:17:42 PM PST 24 2476620552 ps
T886 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3361183284 Feb 28 04:17:48 PM PST 24 Feb 28 04:17:49 PM PST 24 297885616 ps
T887 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2943399679 Feb 28 04:17:42 PM PST 24 Feb 28 04:17:43 PM PST 24 331994846 ps
T888 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.914140242 Feb 28 04:17:55 PM PST 24 Feb 28 04:17:56 PM PST 24 322947708 ps
T889 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.855355178 Feb 28 04:17:58 PM PST 24 Feb 28 04:18:00 PM PST 24 656465112 ps
T890 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4260819643 Feb 28 04:18:29 PM PST 24 Feb 28 04:18:30 PM PST 24 404413256 ps
T891 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3234257001 Feb 28 04:17:50 PM PST 24 Feb 28 04:17:52 PM PST 24 497341996 ps
T892 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3056106283 Feb 28 04:18:07 PM PST 24 Feb 28 04:18:08 PM PST 24 384037882 ps
T893 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3322697148 Feb 28 04:17:58 PM PST 24 Feb 28 04:18:00 PM PST 24 394296188 ps
T894 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2025633380 Feb 28 04:18:02 PM PST 24 Feb 28 04:18:13 PM PST 24 2101471438 ps
T895 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2157368252 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:54 PM PST 24 8152056356 ps
T896 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2950514396 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:32 PM PST 24 525988269 ps
T897 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2040313513 Feb 28 04:17:48 PM PST 24 Feb 28 04:18:02 PM PST 24 4483139306 ps
T898 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4125748216 Feb 28 04:18:04 PM PST 24 Feb 28 04:18:07 PM PST 24 476342227 ps
T899 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4291635103 Feb 28 04:17:29 PM PST 24 Feb 28 04:17:30 PM PST 24 468846332 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4033660144 Feb 28 04:17:29 PM PST 24 Feb 28 04:17:31 PM PST 24 354013349 ps
T901 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2114773360 Feb 28 04:17:48 PM PST 24 Feb 28 04:17:52 PM PST 24 5267183117 ps
T902 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.395975547 Feb 28 04:17:35 PM PST 24 Feb 28 04:17:41 PM PST 24 1315141303 ps
T903 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4126885387 Feb 28 04:17:21 PM PST 24 Feb 28 04:17:23 PM PST 24 1097241565 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2966865807 Feb 28 04:18:04 PM PST 24 Feb 28 04:18:05 PM PST 24 479349620 ps
T905 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.799087188 Feb 28 04:17:44 PM PST 24 Feb 28 04:17:46 PM PST 24 413817758 ps
T906 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3526420043 Feb 28 04:17:54 PM PST 24 Feb 28 04:17:56 PM PST 24 289779015 ps
T907 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4156939674 Feb 28 04:17:29 PM PST 24 Feb 28 04:17:42 PM PST 24 8795142717 ps
T908 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3691420379 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:28 PM PST 24 16898673861 ps
T909 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.177927210 Feb 28 04:18:23 PM PST 24 Feb 28 04:18:25 PM PST 24 319032527 ps
T910 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3539606948 Feb 28 04:17:21 PM PST 24 Feb 28 04:17:25 PM PST 24 4280208959 ps

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3803372858
Short name T5
Test name
Test status
Simulation time 699695337613 ps
CPU time 381.25 seconds
Started Feb 28 04:24:37 PM PST 24
Finished Feb 28 04:30:59 PM PST 24
Peak memory 201360 kb
Host smart-20e7ff84-427e-4cec-967d-387801319997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803372858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3803372858
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3908866393
Short name T15
Test name
Test status
Simulation time 893781889910 ps
CPU time 643.74 seconds
Started Feb 28 04:24:55 PM PST 24
Finished Feb 28 04:35:39 PM PST 24
Peak memory 210120 kb
Host smart-25d05e03-934a-4d43-96b7-e43d3d6c6a36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908866393 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3908866393
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1095950909
Short name T23
Test name
Test status
Simulation time 1041116949260 ps
CPU time 477.61 seconds
Started Feb 28 04:25:45 PM PST 24
Finished Feb 28 04:33:42 PM PST 24
Peak memory 210076 kb
Host smart-4f081d8f-bfee-42f8-9946-6a7bf925d140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095950909 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1095950909
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3289931388
Short name T21
Test name
Test status
Simulation time 175331573606 ps
CPU time 249.8 seconds
Started Feb 28 04:25:46 PM PST 24
Finished Feb 28 04:29:56 PM PST 24
Peak memory 217400 kb
Host smart-ba4cae43-9d90-478a-8c74-2cdd782533f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289931388 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3289931388
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2004177857
Short name T17
Test name
Test status
Simulation time 507501945299 ps
CPU time 295.59 seconds
Started Feb 28 04:25:19 PM PST 24
Finished Feb 28 04:30:15 PM PST 24
Peak memory 201396 kb
Host smart-bc846939-e9ea-473c-80a5-9026b40ead68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004177857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2004177857
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.665016502
Short name T27
Test name
Test status
Simulation time 985410060532 ps
CPU time 497.37 seconds
Started Feb 28 04:26:11 PM PST 24
Finished Feb 28 04:34:28 PM PST 24
Peak memory 211988 kb
Host smart-1c3a2f4a-4ccb-44c8-b153-57398dc1e170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665016502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
665016502
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1034148242
Short name T197
Test name
Test status
Simulation time 656010778641 ps
CPU time 775.81 seconds
Started Feb 28 04:24:49 PM PST 24
Finished Feb 28 04:37:45 PM PST 24
Peak memory 201476 kb
Host smart-5c183c20-41b5-47c2-947f-5d98ac673033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034148242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1034148242
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1630448840
Short name T123
Test name
Test status
Simulation time 496744949783 ps
CPU time 350.3 seconds
Started Feb 28 04:26:12 PM PST 24
Finished Feb 28 04:32:03 PM PST 24
Peak memory 201464 kb
Host smart-562dc20c-93c9-4ebf-b357-b4c5b5169954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630448840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1630448840
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3954013489
Short name T122
Test name
Test status
Simulation time 497187287645 ps
CPU time 308.22 seconds
Started Feb 28 04:24:52 PM PST 24
Finished Feb 28 04:30:01 PM PST 24
Peak memory 201428 kb
Host smart-c33d6f9e-5290-4701-bed5-b6d5019f4aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954013489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3954013489
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3619463769
Short name T47
Test name
Test status
Simulation time 7816966398 ps
CPU time 5.26 seconds
Started Feb 28 04:24:36 PM PST 24
Finished Feb 28 04:24:42 PM PST 24
Peak memory 217336 kb
Host smart-7d040e19-97c8-4f58-9d66-d430e77bed70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619463769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3619463769
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4040860474
Short name T139
Test name
Test status
Simulation time 493886235432 ps
CPU time 278.91 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:29:51 PM PST 24
Peak memory 201540 kb
Host smart-f0b5f880-aba5-4c40-a0f4-9972dcab2555
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040860474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4040860474
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1717232962
Short name T118
Test name
Test status
Simulation time 498776382598 ps
CPU time 116.59 seconds
Started Feb 28 04:25:34 PM PST 24
Finished Feb 28 04:27:30 PM PST 24
Peak memory 201424 kb
Host smart-bb11e2d9-3764-4f08-98d5-0b54c78e05d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717232962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1717232962
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1860250050
Short name T70
Test name
Test status
Simulation time 1116890257 ps
CPU time 2.42 seconds
Started Feb 28 04:17:48 PM PST 24
Finished Feb 28 04:17:51 PM PST 24
Peak memory 209344 kb
Host smart-ad844600-c753-4af7-b085-6a0babc3a66b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860250050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1860250050
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2694167540
Short name T222
Test name
Test status
Simulation time 498027472413 ps
CPU time 561.12 seconds
Started Feb 28 04:26:04 PM PST 24
Finished Feb 28 04:35:26 PM PST 24
Peak memory 201400 kb
Host smart-6778b4af-69d2-4e87-9f4f-5c8b250c201e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694167540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2694167540
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.4067527554
Short name T268
Test name
Test status
Simulation time 331261514941 ps
CPU time 389.72 seconds
Started Feb 28 04:25:45 PM PST 24
Finished Feb 28 04:32:15 PM PST 24
Peak memory 201400 kb
Host smart-068e98a3-8377-4ddc-aa71-adaebae810fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067527554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.4067527554
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1563191035
Short name T75
Test name
Test status
Simulation time 419312295 ps
CPU time 1.07 seconds
Started Feb 28 04:17:50 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 200368 kb
Host smart-bd75ab95-060f-4c4d-9fd4-e96ac3ffaf86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563191035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1563191035
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3592258099
Short name T121
Test name
Test status
Simulation time 329223087037 ps
CPU time 97.02 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 201536 kb
Host smart-3eec38ef-2323-4ffc-abe6-2e3a9b63d767
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592258099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3592258099
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3992417645
Short name T3
Test name
Test status
Simulation time 490030478649 ps
CPU time 292.43 seconds
Started Feb 28 04:24:44 PM PST 24
Finished Feb 28 04:29:37 PM PST 24
Peak memory 201412 kb
Host smart-bf6d9002-8bcd-4442-abba-d6a82cdf4824
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992417645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3992417645
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3549438663
Short name T149
Test name
Test status
Simulation time 492169575889 ps
CPU time 284.87 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:30:44 PM PST 24
Peak memory 201412 kb
Host smart-80d76537-3957-4d9a-96e3-3e1c60e5524c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549438663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3549438663
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.902153741
Short name T157
Test name
Test status
Simulation time 495287507929 ps
CPU time 618.59 seconds
Started Feb 28 04:24:52 PM PST 24
Finished Feb 28 04:35:11 PM PST 24
Peak memory 201396 kb
Host smart-1c3805e9-81a5-4b97-b8d2-88d95219ffbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902153741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.902153741
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3992664914
Short name T228
Test name
Test status
Simulation time 502911188275 ps
CPU time 1134.34 seconds
Started Feb 28 04:26:27 PM PST 24
Finished Feb 28 04:45:22 PM PST 24
Peak memory 201468 kb
Host smart-74b68fd2-955b-49b0-b5b0-e8d8b0da8b83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992664914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3992664914
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2907713851
Short name T211
Test name
Test status
Simulation time 484130024194 ps
CPU time 1140.44 seconds
Started Feb 28 04:25:01 PM PST 24
Finished Feb 28 04:44:02 PM PST 24
Peak memory 201464 kb
Host smart-4116e41d-8fbf-47c0-a8cf-6bfe28837266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907713851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2907713851
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2175775733
Short name T286
Test name
Test status
Simulation time 492463884678 ps
CPU time 574.28 seconds
Started Feb 28 04:35:28 PM PST 24
Finished Feb 28 04:45:03 PM PST 24
Peak memory 199800 kb
Host smart-5ddb1280-f421-4d07-8d21-09f034704b13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175775733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2175775733
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.193253467
Short name T129
Test name
Test status
Simulation time 494926139431 ps
CPU time 796.97 seconds
Started Feb 28 04:25:46 PM PST 24
Finished Feb 28 04:39:03 PM PST 24
Peak memory 201520 kb
Host smart-fc9104b8-81e7-4965-8f8a-04a2624affcd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193253467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.193253467
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.322753912
Short name T112
Test name
Test status
Simulation time 517180407910 ps
CPU time 416.41 seconds
Started Feb 28 04:26:12 PM PST 24
Finished Feb 28 04:33:09 PM PST 24
Peak memory 201456 kb
Host smart-18bb094e-6e82-44d0-9aab-b7b6bcede014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322753912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.322753912
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.377608303
Short name T125
Test name
Test status
Simulation time 331449702730 ps
CPU time 397.94 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:33:04 PM PST 24
Peak memory 201416 kb
Host smart-6bf40a43-20fa-461e-9f25-3fd255ded9a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377608303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.377608303
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3012836574
Short name T136
Test name
Test status
Simulation time 493560542696 ps
CPU time 286.89 seconds
Started Feb 28 04:26:14 PM PST 24
Finished Feb 28 04:31:01 PM PST 24
Peak memory 201380 kb
Host smart-afc6d065-2c06-424b-8c9e-03314386c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012836574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3012836574
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3022625831
Short name T352
Test name
Test status
Simulation time 315847614 ps
CPU time 0.8 seconds
Started Feb 28 04:25:15 PM PST 24
Finished Feb 28 04:25:15 PM PST 24
Peak memory 201076 kb
Host smart-c9312252-1650-49e0-8e3b-181e05e380b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022625831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3022625831
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2755004949
Short name T92
Test name
Test status
Simulation time 4490368150 ps
CPU time 3.7 seconds
Started Feb 28 04:17:38 PM PST 24
Finished Feb 28 04:17:42 PM PST 24
Peak memory 201056 kb
Host smart-e4161fd1-f9e1-4719-bf52-a6584aef1048
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755004949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2755004949
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3294139788
Short name T36
Test name
Test status
Simulation time 4469946690 ps
CPU time 10.76 seconds
Started Feb 28 04:18:00 PM PST 24
Finished Feb 28 04:18:12 PM PST 24
Peak memory 201060 kb
Host smart-3b660fef-e654-4e35-b202-17f11b6c8d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294139788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3294139788
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.254288711
Short name T51
Test name
Test status
Simulation time 612016455171 ps
CPU time 662.58 seconds
Started Feb 28 04:25:02 PM PST 24
Finished Feb 28 04:36:05 PM PST 24
Peak memory 210004 kb
Host smart-4718cf19-4224-4ff8-88f2-f5701b99fe14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254288711 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.254288711
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3636179279
Short name T217
Test name
Test status
Simulation time 495596345140 ps
CPU time 527.27 seconds
Started Feb 28 04:24:50 PM PST 24
Finished Feb 28 04:33:38 PM PST 24
Peak memory 201492 kb
Host smart-5596a9b4-cb25-4d5e-ba54-57af811a2c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636179279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3636179279
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1897174710
Short name T225
Test name
Test status
Simulation time 373127620094 ps
CPU time 884.18 seconds
Started Feb 28 04:26:08 PM PST 24
Finished Feb 28 04:40:53 PM PST 24
Peak memory 201396 kb
Host smart-cc98552a-e59d-4b88-b630-00e4a717aeaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897174710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1897174710
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.810297193
Short name T206
Test name
Test status
Simulation time 329130230261 ps
CPU time 186.84 seconds
Started Feb 28 04:24:41 PM PST 24
Finished Feb 28 04:27:49 PM PST 24
Peak memory 201472 kb
Host smart-918f92e4-a75c-48a4-b0b7-416fb675dc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810297193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.810297193
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3609162316
Short name T278
Test name
Test status
Simulation time 490296808744 ps
CPU time 872.04 seconds
Started Feb 28 04:26:25 PM PST 24
Finished Feb 28 04:40:58 PM PST 24
Peak memory 201376 kb
Host smart-f75856b3-1ac3-450a-a73d-f05ec4d4c54f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609162316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3609162316
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2626702480
Short name T256
Test name
Test status
Simulation time 331474752859 ps
CPU time 136.28 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:27:38 PM PST 24
Peak memory 201424 kb
Host smart-353cd207-05a8-43d6-9146-17dba4045c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626702480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2626702480
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.19774876
Short name T153
Test name
Test status
Simulation time 493952874392 ps
CPU time 245.98 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:29:03 PM PST 24
Peak memory 201260 kb
Host smart-37776bfb-bdd9-44ee-bb2f-22c3ff04f3f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19774876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating
.19774876
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3708571204
Short name T171
Test name
Test status
Simulation time 270118891237 ps
CPU time 963.38 seconds
Started Feb 28 04:25:47 PM PST 24
Finished Feb 28 04:41:50 PM PST 24
Peak memory 209980 kb
Host smart-0fccc7f3-d4ae-426c-aa58-61be66a2216d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708571204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3708571204
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1559590801
Short name T214
Test name
Test status
Simulation time 496780878459 ps
CPU time 508.61 seconds
Started Feb 28 04:26:12 PM PST 24
Finished Feb 28 04:34:41 PM PST 24
Peak memory 201396 kb
Host smart-a5405963-7b19-43f0-b7f3-9de332ebe173
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559590801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1559590801
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1254615527
Short name T233
Test name
Test status
Simulation time 339621194989 ps
CPU time 166.32 seconds
Started Feb 28 04:25:30 PM PST 24
Finished Feb 28 04:28:17 PM PST 24
Peak memory 201444 kb
Host smart-cf8663af-5ef5-436c-841c-e7a6f3f3b09a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254615527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1254615527
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3329135633
Short name T196
Test name
Test status
Simulation time 336726105191 ps
CPU time 375.98 seconds
Started Feb 28 04:24:52 PM PST 24
Finished Feb 28 04:31:09 PM PST 24
Peak memory 201464 kb
Host smart-3b0253ea-9651-46e6-b0c0-6c2597be7a12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329135633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3329135633
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1488338394
Short name T55
Test name
Test status
Simulation time 440223036 ps
CPU time 2.19 seconds
Started Feb 28 04:17:40 PM PST 24
Finished Feb 28 04:17:42 PM PST 24
Peak memory 217400 kb
Host smart-0c3eceaa-f41d-4eaa-bd48-32a96cfd6534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488338394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1488338394
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2828267213
Short name T210
Test name
Test status
Simulation time 177876489695 ps
CPU time 88.91 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:26:29 PM PST 24
Peak memory 201552 kb
Host smart-c2fad848-5c72-471c-a1d1-98b679cc79e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828267213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2828267213
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3551407053
Short name T260
Test name
Test status
Simulation time 168633640676 ps
CPU time 405.47 seconds
Started Feb 28 04:24:50 PM PST 24
Finished Feb 28 04:31:36 PM PST 24
Peak memory 201480 kb
Host smart-f91c042b-037f-45fa-b57a-ac3321c727cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551407053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3551407053
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1421664073
Short name T277
Test name
Test status
Simulation time 157307635102 ps
CPU time 124 seconds
Started Feb 28 04:24:59 PM PST 24
Finished Feb 28 04:27:05 PM PST 24
Peak memory 201300 kb
Host smart-e079a5b5-8a03-4b79-b15e-a6d1841dbbc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421664073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1421664073
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3079951262
Short name T299
Test name
Test status
Simulation time 497178046931 ps
CPU time 547.64 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:34:07 PM PST 24
Peak memory 201456 kb
Host smart-98e16264-69df-413c-90a4-65ef0068916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079951262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3079951262
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.87877862
Short name T12
Test name
Test status
Simulation time 327985181414 ps
CPU time 712.01 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:37:36 PM PST 24
Peak memory 201448 kb
Host smart-f298ec6d-8888-4b62-b1eb-819a332b7cab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87877862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gatin
g.87877862
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2267974917
Short name T252
Test name
Test status
Simulation time 485868472816 ps
CPU time 1181.08 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:45:33 PM PST 24
Peak memory 201468 kb
Host smart-6a0f54dd-275a-4334-bd31-6e94a8c37973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267974917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2267974917
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.120570844
Short name T294
Test name
Test status
Simulation time 330595555927 ps
CPU time 784.81 seconds
Started Feb 28 04:26:23 PM PST 24
Finished Feb 28 04:39:28 PM PST 24
Peak memory 201368 kb
Host smart-56fecb02-0835-4ae6-bcd3-6366d07cf6cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120570844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.120570844
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.417054648
Short name T152
Test name
Test status
Simulation time 518657252424 ps
CPU time 306.27 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:30:49 PM PST 24
Peak memory 201480 kb
Host smart-23a01edb-5521-46f0-98bf-819d05068add
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417054648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.417054648
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2480235912
Short name T193
Test name
Test status
Simulation time 494078215374 ps
CPU time 792.63 seconds
Started Feb 28 04:25:50 PM PST 24
Finished Feb 28 04:39:03 PM PST 24
Peak memory 201492 kb
Host smart-af46d87e-0d7e-4468-a020-6226e0643175
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480235912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2480235912
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2423755051
Short name T208
Test name
Test status
Simulation time 172773617940 ps
CPU time 415.83 seconds
Started Feb 28 04:30:19 PM PST 24
Finished Feb 28 04:37:16 PM PST 24
Peak memory 200320 kb
Host smart-8f48c537-85f6-4f10-ba5b-220581798eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423755051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2423755051
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2874609400
Short name T176
Test name
Test status
Simulation time 119561788987 ps
CPU time 617.23 seconds
Started Feb 28 04:25:17 PM PST 24
Finished Feb 28 04:35:34 PM PST 24
Peak memory 201744 kb
Host smart-c84d807a-2803-435b-9bed-874b53dfeace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874609400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2874609400
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2062622608
Short name T261
Test name
Test status
Simulation time 161448083515 ps
CPU time 356.47 seconds
Started Feb 28 04:25:03 PM PST 24
Finished Feb 28 04:30:59 PM PST 24
Peak memory 201472 kb
Host smart-1ba6dc30-196a-44d6-9548-cba0d35f6e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062622608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2062622608
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1378492184
Short name T258
Test name
Test status
Simulation time 492731396426 ps
CPU time 1218.95 seconds
Started Feb 28 04:25:40 PM PST 24
Finished Feb 28 04:45:59 PM PST 24
Peak memory 201504 kb
Host smart-a6a1ee4e-b492-4484-8951-02cd989ee088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378492184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1378492184
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3050975589
Short name T311
Test name
Test status
Simulation time 40206701934 ps
CPU time 61.04 seconds
Started Feb 28 04:25:11 PM PST 24
Finished Feb 28 04:26:12 PM PST 24
Peak memory 201544 kb
Host smart-ca45e60f-1d80-483e-8af0-09ece62d349d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050975589 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3050975589
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.936367955
Short name T290
Test name
Test status
Simulation time 30928183204 ps
CPU time 62.99 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:26:08 PM PST 24
Peak memory 210080 kb
Host smart-7e90c6cf-fdcc-4d13-bab6-d361b39e2715
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936367955 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.936367955
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3950938781
Short name T18
Test name
Test status
Simulation time 216697023454 ps
CPU time 127.32 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:27:20 PM PST 24
Peak memory 201404 kb
Host smart-eeab24d8-f721-4760-b19a-7f6bd864e482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950938781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3950938781
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3314441316
Short name T245
Test name
Test status
Simulation time 260938537092 ps
CPU time 108.92 seconds
Started Feb 28 04:24:39 PM PST 24
Finished Feb 28 04:26:33 PM PST 24
Peak memory 209624 kb
Host smart-98b44370-ffc9-4dba-bd79-0f1830c885e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314441316 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3314441316
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3748326886
Short name T28
Test name
Test status
Simulation time 462078556652 ps
CPU time 1466.64 seconds
Started Feb 28 04:25:47 PM PST 24
Finished Feb 28 04:50:14 PM PST 24
Peak memory 201716 kb
Host smart-cd3b425a-f003-47bd-a2d9-0f1b0a2d09c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748326886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3748326886
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1673647790
Short name T244
Test name
Test status
Simulation time 332182728753 ps
CPU time 772.52 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:38:34 PM PST 24
Peak memory 201396 kb
Host smart-defd4be8-ba6e-4d8c-8ecb-1a0473594c0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673647790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1673647790
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3784347908
Short name T227
Test name
Test status
Simulation time 498581171053 ps
CPU time 130.15 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:28:17 PM PST 24
Peak memory 201404 kb
Host smart-e97b4824-d4ad-4f66-87cc-18fa7075fa46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784347908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3784347908
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.486339518
Short name T327
Test name
Test status
Simulation time 4467169931 ps
CPU time 12.04 seconds
Started Feb 28 04:19:03 PM PST 24
Finished Feb 28 04:19:15 PM PST 24
Peak memory 201132 kb
Host smart-edd16e07-1779-48d1-8af3-39891a3dbacf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486339518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.486339518
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1544449557
Short name T236
Test name
Test status
Simulation time 322643158748 ps
CPU time 414.28 seconds
Started Feb 28 04:24:56 PM PST 24
Finished Feb 28 04:31:50 PM PST 24
Peak memory 201324 kb
Host smart-327e3361-7dbe-432a-b112-bc2fd96daf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544449557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1544449557
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2051610973
Short name T4
Test name
Test status
Simulation time 180593788273 ps
CPU time 92.07 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:26:32 PM PST 24
Peak memory 201320 kb
Host smart-0c9a707b-cf0f-46a5-8d5f-dd3056d7a55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051610973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2051610973
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1574972154
Short name T305
Test name
Test status
Simulation time 321699464802 ps
CPU time 764.01 seconds
Started Feb 28 04:25:03 PM PST 24
Finished Feb 28 04:37:47 PM PST 24
Peak memory 201416 kb
Host smart-27bad78f-5d49-4c14-aa95-5c77f095548e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574972154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1574972154
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3901956571
Short name T130
Test name
Test status
Simulation time 336275480601 ps
CPU time 50.98 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:25:51 PM PST 24
Peak memory 201344 kb
Host smart-5900624e-9a9a-49e9-953e-a76e99cc2e49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901956571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3901956571
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3022994002
Short name T178
Test name
Test status
Simulation time 116976755590 ps
CPU time 646.87 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:35:32 PM PST 24
Peak memory 201652 kb
Host smart-c4110cfd-c87f-4b4c-a2f4-4ead0aae4877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022994002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3022994002
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.510776483
Short name T238
Test name
Test status
Simulation time 500382531341 ps
CPU time 303.52 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:30:46 PM PST 24
Peak memory 201404 kb
Host smart-14b45dd1-323e-4b3a-b1bf-447f5983cb21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510776483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.510776483
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3073049786
Short name T298
Test name
Test status
Simulation time 324006833658 ps
CPU time 734.45 seconds
Started Feb 28 04:26:02 PM PST 24
Finished Feb 28 04:38:17 PM PST 24
Peak memory 201492 kb
Host smart-768bfcd1-772c-40b4-a00b-8d7771313937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073049786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3073049786
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.276452606
Short name T300
Test name
Test status
Simulation time 254588345885 ps
CPU time 127.09 seconds
Started Feb 28 04:24:56 PM PST 24
Finished Feb 28 04:27:03 PM PST 24
Peak memory 209568 kb
Host smart-362ef7b3-e949-4e08-9793-15d5ab7f89f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276452606 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.276452606
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1329576832
Short name T350
Test name
Test status
Simulation time 499468677095 ps
CPU time 1114.09 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:43:31 PM PST 24
Peak memory 201384 kb
Host smart-e76c5c76-5fb4-46fc-b47f-913777c43356
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329576832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1329576832
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2206247967
Short name T263
Test name
Test status
Simulation time 490366396090 ps
CPU time 585.01 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:34:45 PM PST 24
Peak memory 201308 kb
Host smart-eb2534d5-8889-4fc4-a3fe-c7760910b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206247967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2206247967
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1553377037
Short name T168
Test name
Test status
Simulation time 75140238485 ps
CPU time 266.82 seconds
Started Feb 28 04:24:58 PM PST 24
Finished Feb 28 04:29:25 PM PST 24
Peak memory 201772 kb
Host smart-80c81299-c87a-4af3-8c13-f1673b793598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553377037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1553377037
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2997362701
Short name T216
Test name
Test status
Simulation time 327707400702 ps
CPU time 147.54 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:27:33 PM PST 24
Peak memory 201364 kb
Host smart-d34ef0ae-e82f-4e56-b75b-2eb32694dd23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997362701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2997362701
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2858405171
Short name T177
Test name
Test status
Simulation time 134244187393 ps
CPU time 700.08 seconds
Started Feb 28 04:25:16 PM PST 24
Finished Feb 28 04:36:57 PM PST 24
Peak memory 201760 kb
Host smart-55056fd5-7468-4540-bdbf-2bd117ac8287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858405171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2858405171
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.169326505
Short name T247
Test name
Test status
Simulation time 164113135553 ps
CPU time 12.24 seconds
Started Feb 28 04:25:09 PM PST 24
Finished Feb 28 04:25:21 PM PST 24
Peak memory 201304 kb
Host smart-1d991c67-6caf-4742-94a8-f1d15f87df08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169326505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.169326505
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.532583171
Short name T180
Test name
Test status
Simulation time 123530401977 ps
CPU time 542.73 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:34:21 PM PST 24
Peak memory 201728 kb
Host smart-39dae89b-43b2-4ff5-8cd0-0940b7cba60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532583171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.532583171
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.946607676
Short name T321
Test name
Test status
Simulation time 506400591899 ps
CPU time 1054.07 seconds
Started Feb 28 04:25:39 PM PST 24
Finished Feb 28 04:43:13 PM PST 24
Peak memory 201476 kb
Host smart-610d7b64-d90f-49f6-a969-b537dd63246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946607676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.946607676
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1316642248
Short name T314
Test name
Test status
Simulation time 489336277852 ps
CPU time 320.24 seconds
Started Feb 28 04:25:49 PM PST 24
Finished Feb 28 04:31:10 PM PST 24
Peak memory 201388 kb
Host smart-8342c4e1-e7d2-4410-9fdb-67410d60b0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316642248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1316642248
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3181816691
Short name T161
Test name
Test status
Simulation time 105311246512 ps
CPU time 87.14 seconds
Started Feb 28 04:26:08 PM PST 24
Finished Feb 28 04:27:35 PM PST 24
Peak memory 209704 kb
Host smart-0a6b2e54-c303-4cb2-963c-926dca585de3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181816691 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3181816691
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1341734286
Short name T190
Test name
Test status
Simulation time 80040934752 ps
CPU time 374.81 seconds
Started Feb 28 04:26:09 PM PST 24
Finished Feb 28 04:32:24 PM PST 24
Peak memory 201576 kb
Host smart-afd59266-40dd-4bf4-891f-0ade2befdd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341734286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1341734286
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.154622602
Short name T85
Test name
Test status
Simulation time 734752164 ps
CPU time 1.64 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:32 PM PST 24
Peak memory 201008 kb
Host smart-060ad416-b626-42c8-a779-752883474e3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154622602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.154622602
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3002115578
Short name T89
Test name
Test status
Simulation time 1457649108 ps
CPU time 3.93 seconds
Started Feb 28 04:17:22 PM PST 24
Finished Feb 28 04:17:26 PM PST 24
Peak memory 201064 kb
Host smart-1f8ba217-8f53-4053-9b8a-53bbde38dbfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002115578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3002115578
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2097640772
Short name T96
Test name
Test status
Simulation time 736661828 ps
CPU time 1.21 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:19 PM PST 24
Peak memory 200776 kb
Host smart-bf237d8c-2aae-4446-b6b2-70d294342bf9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097640772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2097640772
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4291635103
Short name T899
Test name
Test status
Simulation time 468846332 ps
CPU time 1.07 seconds
Started Feb 28 04:17:29 PM PST 24
Finished Feb 28 04:17:30 PM PST 24
Peak memory 200820 kb
Host smart-86c515a0-02a9-470a-9fb0-8ed2f55ff4d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291635103 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.4291635103
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1694569589
Short name T79
Test name
Test status
Simulation time 609837226 ps
CPU time 1.14 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 200776 kb
Host smart-aea90099-812e-4386-a1e2-150a4d95c250
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694569589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1694569589
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4033660144
Short name T900
Test name
Test status
Simulation time 354013349 ps
CPU time 1.46 seconds
Started Feb 28 04:17:29 PM PST 24
Finished Feb 28 04:17:31 PM PST 24
Peak memory 200488 kb
Host smart-6bf326a5-f9a1-45d4-bc15-676feec9bc70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033660144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4033660144
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2036950227
Short name T825
Test name
Test status
Simulation time 2397533324 ps
CPU time 1.63 seconds
Started Feb 28 04:17:23 PM PST 24
Finished Feb 28 04:17:25 PM PST 24
Peak memory 200852 kb
Host smart-c9f8a57e-6057-4b56-9f91-83c0a1760dfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036950227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2036950227
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2622736795
Short name T814
Test name
Test status
Simulation time 521186109 ps
CPU time 1.63 seconds
Started Feb 28 04:17:24 PM PST 24
Finished Feb 28 04:17:25 PM PST 24
Peak memory 201092 kb
Host smart-ae0312a7-2efb-4d13-a0e2-50502b8f22e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622736795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2622736795
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3539606948
Short name T910
Test name
Test status
Simulation time 4280208959 ps
CPU time 3.61 seconds
Started Feb 28 04:17:21 PM PST 24
Finished Feb 28 04:17:25 PM PST 24
Peak memory 201012 kb
Host smart-8591cc6b-8ad1-40ac-9254-0e13a2003af1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539606948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3539606948
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3209039029
Short name T803
Test name
Test status
Simulation time 1507004322 ps
CPU time 3.19 seconds
Started Feb 28 04:17:27 PM PST 24
Finished Feb 28 04:17:30 PM PST 24
Peak memory 200988 kb
Host smart-338c0f45-28ba-429b-be7b-455f0d6966de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209039029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3209039029
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2785538251
Short name T84
Test name
Test status
Simulation time 26362073790 ps
CPU time 47.95 seconds
Started Feb 28 04:17:19 PM PST 24
Finished Feb 28 04:18:07 PM PST 24
Peak memory 201160 kb
Host smart-8867ae88-15d5-4d7e-9098-c5506e356a9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785538251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2785538251
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4126885387
Short name T903
Test name
Test status
Simulation time 1097241565 ps
CPU time 2.05 seconds
Started Feb 28 04:17:21 PM PST 24
Finished Feb 28 04:17:23 PM PST 24
Peak memory 200832 kb
Host smart-a83b1237-4b47-46f7-b1dd-04aeb8d0c09b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126885387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.4126885387
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4057949651
Short name T849
Test name
Test status
Simulation time 332923227 ps
CPU time 1.6 seconds
Started Feb 28 04:17:35 PM PST 24
Finished Feb 28 04:17:37 PM PST 24
Peak memory 200804 kb
Host smart-831a9775-0135-474b-bac9-e79b65592dc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057949651 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4057949651
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3204675696
Short name T805
Test name
Test status
Simulation time 597859233 ps
CPU time 0.89 seconds
Started Feb 28 04:17:25 PM PST 24
Finished Feb 28 04:17:26 PM PST 24
Peak memory 200780 kb
Host smart-a51f744d-08c3-4b62-8374-395ff01dd8ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204675696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3204675696
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2595448673
Short name T813
Test name
Test status
Simulation time 434597519 ps
CPU time 1.67 seconds
Started Feb 28 04:17:40 PM PST 24
Finished Feb 28 04:17:42 PM PST 24
Peak memory 200608 kb
Host smart-fb0fde44-5422-4e7a-9224-e7d5fa58b7fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595448673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2595448673
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1282550645
Short name T842
Test name
Test status
Simulation time 2070688951 ps
CPU time 5.47 seconds
Started Feb 28 04:17:19 PM PST 24
Finished Feb 28 04:17:24 PM PST 24
Peak memory 200764 kb
Host smart-3e3c037c-6c45-4edb-b079-ee0721b8b480
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282550645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1282550645
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2117706712
Short name T812
Test name
Test status
Simulation time 522610119 ps
CPU time 2.71 seconds
Started Feb 28 04:17:39 PM PST 24
Finished Feb 28 04:17:42 PM PST 24
Peak memory 201172 kb
Host smart-4ea614ba-3603-455e-8cda-68e951e39ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117706712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2117706712
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3402714317
Short name T858
Test name
Test status
Simulation time 4404155541 ps
CPU time 4.2 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:20 PM PST 24
Peak memory 201120 kb
Host smart-8dd9ea17-d263-477e-982f-7c165375a83a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402714317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3402714317
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2972577685
Short name T826
Test name
Test status
Simulation time 397350993 ps
CPU time 1.77 seconds
Started Feb 28 04:17:47 PM PST 24
Finished Feb 28 04:17:50 PM PST 24
Peak memory 200836 kb
Host smart-c26ecf1d-761c-4ac1-90f3-f6d2b79305e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972577685 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2972577685
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4203373361
Short name T78
Test name
Test status
Simulation time 595361067 ps
CPU time 1.14 seconds
Started Feb 28 04:17:39 PM PST 24
Finished Feb 28 04:17:40 PM PST 24
Peak memory 200788 kb
Host smart-6753ea0f-af00-4077-a688-91ad6d2399fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203373361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.4203373361
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2536028711
Short name T850
Test name
Test status
Simulation time 291232363 ps
CPU time 1.25 seconds
Started Feb 28 04:17:29 PM PST 24
Finished Feb 28 04:17:31 PM PST 24
Peak memory 200380 kb
Host smart-030edb5d-54cc-4ab8-97a4-ce76c233d2f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536028711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2536028711
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1209846638
Short name T852
Test name
Test status
Simulation time 467316703 ps
CPU time 1.74 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:32 PM PST 24
Peak memory 201048 kb
Host smart-56fcf188-c833-4060-9626-058fc42c792a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209846638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1209846638
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.309046720
Short name T871
Test name
Test status
Simulation time 8375875495 ps
CPU time 11.42 seconds
Started Feb 28 04:17:40 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 200928 kb
Host smart-110fd151-6259-4f6a-8aa9-77f0ff67b245
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309046720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.309046720
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3221238279
Short name T71
Test name
Test status
Simulation time 735118569 ps
CPU time 1.22 seconds
Started Feb 28 04:17:41 PM PST 24
Finished Feb 28 04:17:43 PM PST 24
Peak memory 200852 kb
Host smart-b733de9d-1b56-463f-bb25-00cab073a37d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221238279 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3221238279
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1327289681
Short name T876
Test name
Test status
Simulation time 545053795 ps
CPU time 1.06 seconds
Started Feb 28 04:19:04 PM PST 24
Finished Feb 28 04:19:05 PM PST 24
Peak memory 199996 kb
Host smart-f07fa912-4c73-4a5d-974b-242ba6e06f20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327289681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1327289681
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.730218623
Short name T847
Test name
Test status
Simulation time 448548825 ps
CPU time 1.16 seconds
Started Feb 28 04:17:47 PM PST 24
Finished Feb 28 04:17:49 PM PST 24
Peak memory 200712 kb
Host smart-e32fc079-eaeb-4370-8c58-c9c31dce3514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730218623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.730218623
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2085644678
Short name T32
Test name
Test status
Simulation time 4621793028 ps
CPU time 3.33 seconds
Started Feb 28 04:17:41 PM PST 24
Finished Feb 28 04:17:45 PM PST 24
Peak memory 201084 kb
Host smart-51cbf229-ed35-451c-8cf9-681790a09939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085644678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2085644678
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.10528715
Short name T35
Test name
Test status
Simulation time 853015960 ps
CPU time 1.84 seconds
Started Feb 28 04:17:32 PM PST 24
Finished Feb 28 04:17:34 PM PST 24
Peak memory 201108 kb
Host smart-e5d2f343-7fc5-4247-9834-ce86929a0fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10528715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.10528715
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3320111447
Short name T879
Test name
Test status
Simulation time 3852933821 ps
CPU time 10.05 seconds
Started Feb 28 04:17:50 PM PST 24
Finished Feb 28 04:18:01 PM PST 24
Peak memory 201052 kb
Host smart-b1f10324-59b8-4adb-8e14-3bcffe9720eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320111447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3320111447
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3067821985
Short name T869
Test name
Test status
Simulation time 721365023 ps
CPU time 1.47 seconds
Started Feb 28 04:17:36 PM PST 24
Finished Feb 28 04:17:38 PM PST 24
Peak memory 209308 kb
Host smart-8c526558-2847-45ea-9123-ea00155fc8d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067821985 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3067821985
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4065573035
Short name T870
Test name
Test status
Simulation time 428946012 ps
CPU time 1.07 seconds
Started Feb 28 04:17:54 PM PST 24
Finished Feb 28 04:17:55 PM PST 24
Peak memory 200796 kb
Host smart-95862a6c-29f3-499e-8e0f-55ab7e82665a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065573035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4065573035
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3113187701
Short name T806
Test name
Test status
Simulation time 352052693 ps
CPU time 0.87 seconds
Started Feb 28 04:17:57 PM PST 24
Finished Feb 28 04:17:58 PM PST 24
Peak memory 200716 kb
Host smart-8d4cd85a-3b23-4af7-b3a9-be83e19b793d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113187701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3113187701
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1787426851
Short name T866
Test name
Test status
Simulation time 3581674780 ps
CPU time 3.27 seconds
Started Feb 28 04:17:37 PM PST 24
Finished Feb 28 04:17:40 PM PST 24
Peak memory 201196 kb
Host smart-4101bd7c-272a-4472-9787-e2aa9dd82418
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787426851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1787426851
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2038382525
Short name T830
Test name
Test status
Simulation time 744652249 ps
CPU time 3.7 seconds
Started Feb 28 04:17:49 PM PST 24
Finished Feb 28 04:17:54 PM PST 24
Peak memory 201092 kb
Host smart-3e6bbc55-fcbf-4b6b-8736-605b9d2a4408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038382525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2038382525
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1544101236
Short name T822
Test name
Test status
Simulation time 4069039680 ps
CPU time 6.3 seconds
Started Feb 28 04:17:42 PM PST 24
Finished Feb 28 04:17:48 PM PST 24
Peak memory 201076 kb
Host smart-0d3f2239-f201-42c1-8bec-324cde0922b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544101236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1544101236
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1835590161
Short name T802
Test name
Test status
Simulation time 637664463 ps
CPU time 2.28 seconds
Started Feb 28 04:17:47 PM PST 24
Finished Feb 28 04:18:00 PM PST 24
Peak memory 200996 kb
Host smart-707ad5bc-3495-4c46-b1f2-de9e3f873917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835590161 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1835590161
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3766265657
Short name T881
Test name
Test status
Simulation time 572485434 ps
CPU time 1.23 seconds
Started Feb 28 04:17:33 PM PST 24
Finished Feb 28 04:17:34 PM PST 24
Peak memory 200772 kb
Host smart-13abaefa-1bac-4152-8064-bfbd52dae0e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766265657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3766265657
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3442375585
Short name T839
Test name
Test status
Simulation time 348880125 ps
CPU time 1 seconds
Started Feb 28 04:17:54 PM PST 24
Finished Feb 28 04:17:55 PM PST 24
Peak memory 200644 kb
Host smart-1b2f8652-2ea1-42d8-a276-1a977a366a92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442375585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3442375585
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3580583064
Short name T34
Test name
Test status
Simulation time 4702069380 ps
CPU time 6 seconds
Started Feb 28 04:17:37 PM PST 24
Finished Feb 28 04:17:43 PM PST 24
Peak memory 201296 kb
Host smart-06731c78-90aa-4b7c-95fc-193e3fb3d170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580583064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3580583064
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.61380247
Short name T848
Test name
Test status
Simulation time 522683103 ps
CPU time 2.47 seconds
Started Feb 28 04:17:29 PM PST 24
Finished Feb 28 04:17:32 PM PST 24
Peak memory 208824 kb
Host smart-4172ba9d-500e-42b7-93ae-c1abdff85387
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61380247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.61380247
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4196033083
Short name T841
Test name
Test status
Simulation time 539796826 ps
CPU time 1.16 seconds
Started Feb 28 04:17:48 PM PST 24
Finished Feb 28 04:17:49 PM PST 24
Peak memory 200744 kb
Host smart-0fa6869a-bfc0-444c-b3bc-e45deb507bbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196033083 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4196033083
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2554703946
Short name T82
Test name
Test status
Simulation time 479641596 ps
CPU time 1 seconds
Started Feb 28 04:17:39 PM PST 24
Finished Feb 28 04:17:40 PM PST 24
Peak memory 200812 kb
Host smart-d9a5f4e2-1c79-4745-9686-87b8fba11543
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554703946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2554703946
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1965887991
Short name T811
Test name
Test status
Simulation time 447098261 ps
CPU time 1.22 seconds
Started Feb 28 04:17:45 PM PST 24
Finished Feb 28 04:17:47 PM PST 24
Peak memory 200752 kb
Host smart-dbe07196-251d-4d1f-94d1-0f31eebf58af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965887991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1965887991
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2650937535
Short name T867
Test name
Test status
Simulation time 4660821087 ps
CPU time 3.94 seconds
Started Feb 28 04:17:40 PM PST 24
Finished Feb 28 04:17:44 PM PST 24
Peak memory 201100 kb
Host smart-475900e7-5c11-4586-bef3-a8c94ef3253a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650937535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2650937535
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3925708816
Short name T97
Test name
Test status
Simulation time 457708113 ps
CPU time 2.78 seconds
Started Feb 28 04:17:40 PM PST 24
Finished Feb 28 04:17:43 PM PST 24
Peak memory 201252 kb
Host smart-1a5bfe47-51ab-4298-8add-ffdc46d8c679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925708816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3925708816
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2157368252
Short name T895
Test name
Test status
Simulation time 8152056356 ps
CPU time 23.89 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:54 PM PST 24
Peak memory 201236 kb
Host smart-4acdc68e-5810-4d1f-af44-250cbac3f0bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157368252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2157368252
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3234257001
Short name T891
Test name
Test status
Simulation time 497341996 ps
CPU time 1.55 seconds
Started Feb 28 04:17:50 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 200888 kb
Host smart-d04b7d5d-9563-4f36-8dd4-85ffc67a3761
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234257001 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3234257001
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2943399679
Short name T887
Test name
Test status
Simulation time 331994846 ps
CPU time 1.15 seconds
Started Feb 28 04:17:42 PM PST 24
Finished Feb 28 04:17:43 PM PST 24
Peak memory 200788 kb
Host smart-93cb95eb-4f8e-445c-b684-de9291c2875f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943399679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2943399679
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.77712624
Short name T860
Test name
Test status
Simulation time 356895913 ps
CPU time 1.44 seconds
Started Feb 28 04:17:38 PM PST 24
Finished Feb 28 04:17:40 PM PST 24
Peak memory 200668 kb
Host smart-70b352b8-5775-4859-9b28-98024ca27706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77712624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.77712624
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2025633380
Short name T894
Test name
Test status
Simulation time 2101471438 ps
CPU time 10.53 seconds
Started Feb 28 04:18:02 PM PST 24
Finished Feb 28 04:18:13 PM PST 24
Peak memory 200820 kb
Host smart-43725129-bd63-4b9f-8f50-4699deba55d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025633380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2025633380
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.660589960
Short name T99
Test name
Test status
Simulation time 590155079 ps
CPU time 2.74 seconds
Started Feb 28 04:17:41 PM PST 24
Finished Feb 28 04:17:44 PM PST 24
Peak memory 217468 kb
Host smart-3ae545f5-7e47-49ef-a2e5-f9f1b6e9bfac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660589960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.660589960
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4178013148
Short name T69
Test name
Test status
Simulation time 7627092014 ps
CPU time 21.44 seconds
Started Feb 28 04:17:50 PM PST 24
Finished Feb 28 04:18:12 PM PST 24
Peak memory 200784 kb
Host smart-b6bc3e30-925e-4033-abaa-e5f9bfe8d0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178013148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4178013148
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.855355178
Short name T889
Test name
Test status
Simulation time 656465112 ps
CPU time 1.79 seconds
Started Feb 28 04:17:58 PM PST 24
Finished Feb 28 04:18:00 PM PST 24
Peak memory 200820 kb
Host smart-f04a4aa0-0313-4a83-a76a-78629fb34d9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855355178 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.855355178
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2966865807
Short name T904
Test name
Test status
Simulation time 479349620 ps
CPU time 0.93 seconds
Started Feb 28 04:18:04 PM PST 24
Finished Feb 28 04:18:05 PM PST 24
Peak memory 200716 kb
Host smart-45aa2fb0-67ac-439a-a294-4fda712ad498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966865807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2966865807
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1939741813
Short name T91
Test name
Test status
Simulation time 2781791015 ps
CPU time 2.22 seconds
Started Feb 28 04:17:53 PM PST 24
Finished Feb 28 04:17:55 PM PST 24
Peak memory 200840 kb
Host smart-315213f7-dc7e-4577-bc8a-205b6dd796c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939741813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1939741813
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.767406298
Short name T808
Test name
Test status
Simulation time 9032469742 ps
CPU time 7.17 seconds
Started Feb 28 04:17:47 PM PST 24
Finished Feb 28 04:17:54 PM PST 24
Peak memory 201144 kb
Host smart-a184678d-6432-42bb-a718-46f0bd7abf70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767406298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.767406298
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3086852829
Short name T874
Test name
Test status
Simulation time 497003639 ps
CPU time 1.31 seconds
Started Feb 28 04:18:10 PM PST 24
Finished Feb 28 04:18:12 PM PST 24
Peak memory 200920 kb
Host smart-c5c9ec02-e7cf-4a65-ae7c-de6a0418b8a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086852829 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3086852829
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4033748070
Short name T81
Test name
Test status
Simulation time 438570560 ps
CPU time 1.2 seconds
Started Feb 28 04:18:15 PM PST 24
Finished Feb 28 04:18:17 PM PST 24
Peak memory 200772 kb
Host smart-e10831ab-8093-47d9-afc7-521b9bea5939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033748070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.4033748070
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2792136563
Short name T853
Test name
Test status
Simulation time 395228990 ps
CPU time 0.95 seconds
Started Feb 28 04:17:47 PM PST 24
Finished Feb 28 04:17:49 PM PST 24
Peak memory 200668 kb
Host smart-78d6dfad-942b-4909-a809-3bf644745651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792136563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2792136563
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1714267222
Short name T93
Test name
Test status
Simulation time 2434109553 ps
CPU time 5.44 seconds
Started Feb 28 04:17:57 PM PST 24
Finished Feb 28 04:18:03 PM PST 24
Peak memory 200812 kb
Host smart-705df9ef-1ee0-45d4-85e4-5fccac849c8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714267222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1714267222
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3683411536
Short name T828
Test name
Test status
Simulation time 590900644 ps
CPU time 3.02 seconds
Started Feb 28 04:17:58 PM PST 24
Finished Feb 28 04:18:01 PM PST 24
Peak memory 217068 kb
Host smart-8d110852-5ffc-4bee-a34f-6bdf42fd8f79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683411536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3683411536
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1277185594
Short name T100
Test name
Test status
Simulation time 4194526314 ps
CPU time 3.88 seconds
Started Feb 28 04:17:44 PM PST 24
Finished Feb 28 04:17:48 PM PST 24
Peak memory 201048 kb
Host smart-141bae09-21c4-454d-8083-1b248cead4db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277185594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1277185594
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1713022837
Short name T824
Test name
Test status
Simulation time 426515990 ps
CPU time 1.92 seconds
Started Feb 28 04:18:07 PM PST 24
Finished Feb 28 04:18:09 PM PST 24
Peak memory 200936 kb
Host smart-b6d4ce19-afe8-4cae-afea-6d226c9a6bca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713022837 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1713022837
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3361183284
Short name T886
Test name
Test status
Simulation time 297885616 ps
CPU time 1.44 seconds
Started Feb 28 04:17:48 PM PST 24
Finished Feb 28 04:17:49 PM PST 24
Peak memory 200928 kb
Host smart-06d0f08c-5d48-47b1-920f-4211d75904f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361183284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3361183284
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1712374677
Short name T884
Test name
Test status
Simulation time 374979276 ps
CPU time 1.57 seconds
Started Feb 28 04:17:53 PM PST 24
Finished Feb 28 04:17:55 PM PST 24
Peak memory 200492 kb
Host smart-8a4b1437-9de4-47fd-bfae-0baf73b97d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712374677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1712374677
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1847171203
Short name T856
Test name
Test status
Simulation time 4859892049 ps
CPU time 11.63 seconds
Started Feb 28 04:17:50 PM PST 24
Finished Feb 28 04:18:02 PM PST 24
Peak memory 201020 kb
Host smart-d8214c5c-9062-43c3-90c1-3f93c72e17fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847171203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1847171203
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4125748216
Short name T898
Test name
Test status
Simulation time 476342227 ps
CPU time 2.3 seconds
Started Feb 28 04:18:04 PM PST 24
Finished Feb 28 04:18:07 PM PST 24
Peak memory 201100 kb
Host smart-d4f0d283-aa6e-4459-9b87-5c5187bab913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125748216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4125748216
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2040313513
Short name T897
Test name
Test status
Simulation time 4483139306 ps
CPU time 11.87 seconds
Started Feb 28 04:17:48 PM PST 24
Finished Feb 28 04:18:02 PM PST 24
Peak memory 201080 kb
Host smart-a48c4580-6bb0-4443-9094-a4b2ed9673cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040313513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2040313513
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3041393893
Short name T829
Test name
Test status
Simulation time 586180829 ps
CPU time 1.19 seconds
Started Feb 28 04:17:59 PM PST 24
Finished Feb 28 04:18:00 PM PST 24
Peak memory 200868 kb
Host smart-8be4e90c-a843-474a-b50e-a18f9f24158b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041393893 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3041393893
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1844992853
Short name T851
Test name
Test status
Simulation time 410325701 ps
CPU time 1.78 seconds
Started Feb 28 04:18:09 PM PST 24
Finished Feb 28 04:18:11 PM PST 24
Peak memory 200792 kb
Host smart-b85afafd-3042-4595-a3df-1a6f340b9549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844992853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1844992853
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2026512374
Short name T872
Test name
Test status
Simulation time 494248127 ps
CPU time 1.8 seconds
Started Feb 28 04:17:52 PM PST 24
Finished Feb 28 04:17:54 PM PST 24
Peak memory 200804 kb
Host smart-64fb902e-c6a8-4f6d-a02a-27d5aaef213a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026512374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2026512374
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2216548541
Short name T868
Test name
Test status
Simulation time 2033105687 ps
CPU time 7.1 seconds
Started Feb 28 04:17:50 PM PST 24
Finished Feb 28 04:17:58 PM PST 24
Peak memory 200828 kb
Host smart-4477384f-85d2-4236-95b1-caac1b514a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216548541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2216548541
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3939582627
Short name T840
Test name
Test status
Simulation time 455395020 ps
CPU time 1.69 seconds
Started Feb 28 04:17:48 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 201028 kb
Host smart-eb88f4a6-f18b-4461-9c05-9218e315e759
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939582627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3939582627
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1750311524
Short name T883
Test name
Test status
Simulation time 4420204205 ps
CPU time 6.63 seconds
Started Feb 28 04:17:51 PM PST 24
Finished Feb 28 04:17:57 PM PST 24
Peak memory 201068 kb
Host smart-6696cc6d-584b-4a5d-a590-684cc96ccfc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750311524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1750311524
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1521174857
Short name T76
Test name
Test status
Simulation time 1145043194 ps
CPU time 3.15 seconds
Started Feb 28 04:17:38 PM PST 24
Finished Feb 28 04:17:41 PM PST 24
Peak memory 201132 kb
Host smart-25a2e88a-540d-4e4c-9d3f-0f0da7d20573
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521174857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1521174857
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4212384697
Short name T846
Test name
Test status
Simulation time 27025533714 ps
CPU time 65.45 seconds
Started Feb 28 04:17:19 PM PST 24
Finished Feb 28 04:18:24 PM PST 24
Peak memory 201132 kb
Host smart-d978605e-bd2a-4d78-86d0-af057f9e3010
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212384697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.4212384697
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.67376099
Short name T857
Test name
Test status
Simulation time 1224348474 ps
CPU time 3.65 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:19 PM PST 24
Peak memory 200772 kb
Host smart-35041026-6fa7-4d10-8118-27157491f59e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67376099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_res
et.67376099
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3120530371
Short name T54
Test name
Test status
Simulation time 481084388 ps
CPU time 1.54 seconds
Started Feb 28 04:17:34 PM PST 24
Finished Feb 28 04:17:37 PM PST 24
Peak memory 200856 kb
Host smart-e95c8cef-7bfb-4246-a42e-630af84ba315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120530371 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3120530371
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3395253207
Short name T818
Test name
Test status
Simulation time 406871866 ps
CPU time 1.73 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:32 PM PST 24
Peak memory 200768 kb
Host smart-9a8ed813-92ab-48d7-840a-323a803e3ab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395253207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3395253207
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3825800146
Short name T794
Test name
Test status
Simulation time 501756184 ps
CPU time 0.88 seconds
Started Feb 28 04:19:04 PM PST 24
Finished Feb 28 04:19:05 PM PST 24
Peak memory 200720 kb
Host smart-6deec550-bc06-49b5-9424-957b27da672e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825800146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3825800146
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3294868908
Short name T810
Test name
Test status
Simulation time 4930492622 ps
CPU time 19.24 seconds
Started Feb 28 04:19:07 PM PST 24
Finished Feb 28 04:19:26 PM PST 24
Peak memory 201128 kb
Host smart-af4890c4-fea6-486d-b01f-9786bb9dd528
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294868908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3294868908
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4278062946
Short name T854
Test name
Test status
Simulation time 843229551 ps
CPU time 2.23 seconds
Started Feb 28 04:18:05 PM PST 24
Finished Feb 28 04:18:07 PM PST 24
Peak memory 201092 kb
Host smart-865c52ae-0362-4a6e-bca8-604a5823e7c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278062946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4278062946
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4156939674
Short name T907
Test name
Test status
Simulation time 8795142717 ps
CPU time 7.04 seconds
Started Feb 28 04:17:29 PM PST 24
Finished Feb 28 04:17:42 PM PST 24
Peak memory 201116 kb
Host smart-5cb208db-c5ea-412f-8b80-3cc2985a27d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156939674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.4156939674
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3526420043
Short name T906
Test name
Test status
Simulation time 289779015 ps
CPU time 0.9 seconds
Started Feb 28 04:17:54 PM PST 24
Finished Feb 28 04:17:56 PM PST 24
Peak memory 200576 kb
Host smart-3cd629e6-8ff1-467b-8b94-46e1e342d2ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526420043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3526420043
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3322697148
Short name T893
Test name
Test status
Simulation time 394296188 ps
CPU time 1.59 seconds
Started Feb 28 04:17:58 PM PST 24
Finished Feb 28 04:18:00 PM PST 24
Peak memory 200700 kb
Host smart-1b4afa78-1f11-4536-8e66-1f72bc5a046e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322697148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3322697148
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.434179256
Short name T798
Test name
Test status
Simulation time 473808273 ps
CPU time 1.48 seconds
Started Feb 28 04:17:49 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 200880 kb
Host smart-263d14ab-d7ba-4869-9c1a-50407bf131a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434179256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.434179256
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1315418313
Short name T875
Test name
Test status
Simulation time 410716970 ps
CPU time 1.25 seconds
Started Feb 28 04:17:49 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 200600 kb
Host smart-d7e5da83-d8b6-483d-bda0-7b451bea91df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315418313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1315418313
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3932469558
Short name T845
Test name
Test status
Simulation time 394431745 ps
CPU time 0.88 seconds
Started Feb 28 04:18:10 PM PST 24
Finished Feb 28 04:18:11 PM PST 24
Peak memory 200560 kb
Host smart-53390ecc-3fbc-409c-bc2b-7bdf331340de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932469558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3932469558
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.205949314
Short name T880
Test name
Test status
Simulation time 472244395 ps
CPU time 1.72 seconds
Started Feb 28 04:18:02 PM PST 24
Finished Feb 28 04:18:05 PM PST 24
Peak memory 200588 kb
Host smart-cb1b0e7f-cf67-4fc5-b712-9fb797e6832b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205949314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.205949314
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.318954435
Short name T796
Test name
Test status
Simulation time 383258830 ps
CPU time 1.43 seconds
Started Feb 28 04:17:50 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 200720 kb
Host smart-74051560-ffd2-4830-ac46-d1f7860bdfaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318954435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.318954435
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2786330675
Short name T861
Test name
Test status
Simulation time 425537554 ps
CPU time 0.89 seconds
Started Feb 28 04:17:53 PM PST 24
Finished Feb 28 04:17:54 PM PST 24
Peak memory 200568 kb
Host smart-6196fb77-640a-4c72-a278-7b3445233170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786330675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2786330675
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3056106283
Short name T892
Test name
Test status
Simulation time 384037882 ps
CPU time 1.1 seconds
Started Feb 28 04:18:07 PM PST 24
Finished Feb 28 04:18:08 PM PST 24
Peak memory 200860 kb
Host smart-f2bf6204-6095-4c98-b80b-b314250cc23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056106283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3056106283
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2319924098
Short name T815
Test name
Test status
Simulation time 587818711 ps
CPU time 0.82 seconds
Started Feb 28 04:18:22 PM PST 24
Finished Feb 28 04:18:23 PM PST 24
Peak memory 200640 kb
Host smart-a928af68-1429-4274-b6ac-a1f585cd372b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319924098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2319924098
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2954534719
Short name T83
Test name
Test status
Simulation time 590026831 ps
CPU time 2.09 seconds
Started Feb 28 04:18:43 PM PST 24
Finished Feb 28 04:18:50 PM PST 24
Peak memory 200580 kb
Host smart-c44fd5a9-e8cf-4469-9089-5c831dee49a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954534719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2954534719
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2596369122
Short name T95
Test name
Test status
Simulation time 25319359426 ps
CPU time 26.22 seconds
Started Feb 28 04:17:45 PM PST 24
Finished Feb 28 04:18:12 PM PST 24
Peak memory 201160 kb
Host smart-095fe3dc-5a44-4891-8ec8-6e5b0d846c1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596369122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2596369122
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2537202354
Short name T800
Test name
Test status
Simulation time 1238613709 ps
CPU time 1.79 seconds
Started Feb 28 04:17:26 PM PST 24
Finished Feb 28 04:17:28 PM PST 24
Peak memory 200800 kb
Host smart-048dc119-585e-4aba-a94c-3b4db050ba75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537202354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2537202354
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3297589403
Short name T877
Test name
Test status
Simulation time 536740274 ps
CPU time 1.97 seconds
Started Feb 28 04:17:38 PM PST 24
Finished Feb 28 04:17:40 PM PST 24
Peak memory 200852 kb
Host smart-613935c3-7353-4649-9220-3406a3729349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297589403 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3297589403
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.443957340
Short name T87
Test name
Test status
Simulation time 542735089 ps
CPU time 1 seconds
Started Feb 28 04:19:07 PM PST 24
Finished Feb 28 04:19:09 PM PST 24
Peak memory 200812 kb
Host smart-b8fca309-3610-4568-bcb6-45521fdfdb36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443957340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.443957340
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.211903518
Short name T793
Test name
Test status
Simulation time 316819681 ps
CPU time 0.76 seconds
Started Feb 28 04:17:41 PM PST 24
Finished Feb 28 04:17:42 PM PST 24
Peak memory 200572 kb
Host smart-f3793d22-0dbf-438c-ae1b-05ca8ae16445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211903518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.211903518
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2342676305
Short name T885
Test name
Test status
Simulation time 2476620552 ps
CPU time 4.84 seconds
Started Feb 28 04:17:37 PM PST 24
Finished Feb 28 04:17:42 PM PST 24
Peak memory 200852 kb
Host smart-255e3619-6fbd-45a3-888e-d5e369dd2e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342676305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2342676305
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2833140432
Short name T98
Test name
Test status
Simulation time 457813120 ps
CPU time 2.59 seconds
Started Feb 28 04:17:25 PM PST 24
Finished Feb 28 04:17:28 PM PST 24
Peak memory 201136 kb
Host smart-cf254416-ce2a-413d-91c5-86ef9a2ec348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833140432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2833140432
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3665095661
Short name T330
Test name
Test status
Simulation time 8253737043 ps
CPU time 24.97 seconds
Started Feb 28 04:17:34 PM PST 24
Finished Feb 28 04:18:00 PM PST 24
Peak memory 201140 kb
Host smart-bbf9a408-14ec-4111-b166-4be4a8ac2805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665095661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3665095661
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1442160301
Short name T819
Test name
Test status
Simulation time 380061052 ps
CPU time 1.68 seconds
Started Feb 28 04:17:55 PM PST 24
Finished Feb 28 04:17:57 PM PST 24
Peak memory 200556 kb
Host smart-3b5029f5-50cd-4363-b7e5-695e120c32d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442160301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1442160301
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2408255605
Short name T833
Test name
Test status
Simulation time 395126882 ps
CPU time 1.12 seconds
Started Feb 28 04:17:54 PM PST 24
Finished Feb 28 04:17:55 PM PST 24
Peak memory 200588 kb
Host smart-655fa7a8-8f3f-4c0f-9eaa-125d02d2e720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408255605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2408255605
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.177927210
Short name T909
Test name
Test status
Simulation time 319032527 ps
CPU time 0.91 seconds
Started Feb 28 04:18:23 PM PST 24
Finished Feb 28 04:18:25 PM PST 24
Peak memory 200596 kb
Host smart-798598de-28af-4a5c-aa02-eedbcf1ee91e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177927210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.177927210
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1239024311
Short name T878
Test name
Test status
Simulation time 493366085 ps
CPU time 1.24 seconds
Started Feb 28 04:17:48 PM PST 24
Finished Feb 28 04:17:49 PM PST 24
Peak memory 200596 kb
Host smart-3eabed86-e5c1-406a-8da5-5edd1305ce7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239024311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1239024311
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3679119035
Short name T882
Test name
Test status
Simulation time 430736181 ps
CPU time 0.72 seconds
Started Feb 28 04:18:03 PM PST 24
Finished Feb 28 04:18:04 PM PST 24
Peak memory 200524 kb
Host smart-b5506861-d197-4f37-82be-47281dc1e6d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679119035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3679119035
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3739466096
Short name T791
Test name
Test status
Simulation time 545152963 ps
CPU time 1.04 seconds
Started Feb 28 04:18:01 PM PST 24
Finished Feb 28 04:18:07 PM PST 24
Peak memory 200548 kb
Host smart-ef303de5-74c2-4475-bfdf-4ee9d704bea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739466096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3739466096
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2461160039
Short name T859
Test name
Test status
Simulation time 423477808 ps
CPU time 1.51 seconds
Started Feb 28 04:17:54 PM PST 24
Finished Feb 28 04:17:56 PM PST 24
Peak memory 200572 kb
Host smart-f638a8fa-9a3d-4fef-8965-55a7291afe14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461160039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2461160039
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2632981172
Short name T795
Test name
Test status
Simulation time 410249071 ps
CPU time 0.83 seconds
Started Feb 28 04:17:58 PM PST 24
Finished Feb 28 04:17:59 PM PST 24
Peak memory 200848 kb
Host smart-014b5280-c135-4595-a57b-7fd9865e1f28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632981172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2632981172
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.857455985
Short name T804
Test name
Test status
Simulation time 412007334 ps
CPU time 1.01 seconds
Started Feb 28 04:18:03 PM PST 24
Finished Feb 28 04:18:04 PM PST 24
Peak memory 200888 kb
Host smart-c58b247a-fcd8-40d8-a296-5d170eccafac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857455985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.857455985
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2725914015
Short name T821
Test name
Test status
Simulation time 575180393 ps
CPU time 0.67 seconds
Started Feb 28 04:18:04 PM PST 24
Finished Feb 28 04:18:05 PM PST 24
Peak memory 200544 kb
Host smart-d0294bce-77ed-4568-979c-a66945130eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725914015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2725914015
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.395975547
Short name T902
Test name
Test status
Simulation time 1315141303 ps
CPU time 6.14 seconds
Started Feb 28 04:17:35 PM PST 24
Finished Feb 28 04:17:41 PM PST 24
Peak memory 201024 kb
Host smart-870e8fa0-8332-4714-966f-7c46f45235bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395975547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.395975547
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3691420379
Short name T908
Test name
Test status
Simulation time 16898673861 ps
CPU time 12.92 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:28 PM PST 24
Peak memory 201088 kb
Host smart-97eb5756-7fa5-4429-a956-75d5c00c56b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691420379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3691420379
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1161914
Short name T77
Test name
Test status
Simulation time 1084116519 ps
CPU time 1.33 seconds
Started Feb 28 04:17:34 PM PST 24
Finished Feb 28 04:17:36 PM PST 24
Peak memory 200788 kb
Host smart-755dded2-462b-49df-bf22-216e8fffe117
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_rese
t.1161914
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3564366094
Short name T816
Test name
Test status
Simulation time 550466996 ps
CPU time 1.91 seconds
Started Feb 28 04:17:46 PM PST 24
Finished Feb 28 04:17:49 PM PST 24
Peak memory 200836 kb
Host smart-a1a07b51-f629-419c-89d5-74edbd69c7e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564366094 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3564366094
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1220410296
Short name T80
Test name
Test status
Simulation time 395779125 ps
CPU time 0.89 seconds
Started Feb 28 04:19:03 PM PST 24
Finished Feb 28 04:19:04 PM PST 24
Peak memory 200808 kb
Host smart-61c19ed4-4bb6-428f-a8bb-20a6e673e057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220410296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1220410296
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4058984881
Short name T843
Test name
Test status
Simulation time 560500262 ps
CPU time 0.72 seconds
Started Feb 28 04:17:33 PM PST 24
Finished Feb 28 04:17:34 PM PST 24
Peak memory 200740 kb
Host smart-0b6b94b8-8e8d-49c3-91c0-561a0bdc80dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058984881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4058984881
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1586205690
Short name T809
Test name
Test status
Simulation time 3988754313 ps
CPU time 1.59 seconds
Started Feb 28 04:17:43 PM PST 24
Finished Feb 28 04:17:45 PM PST 24
Peak memory 201100 kb
Host smart-1d8c9394-5120-4d15-85ea-b54b29adc9b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586205690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1586205690
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1151818000
Short name T873
Test name
Test status
Simulation time 1005804688 ps
CPU time 3.26 seconds
Started Feb 28 04:17:37 PM PST 24
Finished Feb 28 04:17:40 PM PST 24
Peak memory 201092 kb
Host smart-fb1ab1be-9539-46c1-a833-62012dc38d82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151818000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1151818000
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.859497095
Short name T40
Test name
Test status
Simulation time 4589881583 ps
CPU time 12.68 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:43 PM PST 24
Peak memory 201272 kb
Host smart-7155fb67-af53-459e-baf1-b0ed96e9b8af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859497095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.859497095
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2645305906
Short name T864
Test name
Test status
Simulation time 365370813 ps
CPU time 1.03 seconds
Started Feb 28 04:17:59 PM PST 24
Finished Feb 28 04:18:00 PM PST 24
Peak memory 200568 kb
Host smart-b3870811-8977-431a-904d-8fe1d749ea92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645305906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2645305906
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.908745243
Short name T855
Test name
Test status
Simulation time 513232455 ps
CPU time 0.94 seconds
Started Feb 28 04:18:11 PM PST 24
Finished Feb 28 04:18:12 PM PST 24
Peak memory 200680 kb
Host smart-ac579e4d-a49f-4d15-b396-c828dc0c4e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908745243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.908745243
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.914140242
Short name T888
Test name
Test status
Simulation time 322947708 ps
CPU time 0.87 seconds
Started Feb 28 04:17:55 PM PST 24
Finished Feb 28 04:17:56 PM PST 24
Peak memory 200592 kb
Host smart-c6247d20-802c-40cd-8f2a-f8f2dc2a4d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914140242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.914140242
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.762887260
Short name T865
Test name
Test status
Simulation time 463119345 ps
CPU time 1.72 seconds
Started Feb 28 04:18:12 PM PST 24
Finished Feb 28 04:18:13 PM PST 24
Peak memory 200548 kb
Host smart-523e3870-b2fd-4bed-9f1e-82e607465ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762887260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.762887260
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3858982434
Short name T799
Test name
Test status
Simulation time 374977647 ps
CPU time 1.08 seconds
Started Feb 28 04:17:56 PM PST 24
Finished Feb 28 04:17:57 PM PST 24
Peak memory 200680 kb
Host smart-5bb8a099-cf04-4fce-94d3-d0dfcae71cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858982434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3858982434
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.921728595
Short name T823
Test name
Test status
Simulation time 444999403 ps
CPU time 1.15 seconds
Started Feb 28 04:17:56 PM PST 24
Finished Feb 28 04:17:57 PM PST 24
Peak memory 200572 kb
Host smart-f59cf2b4-c4de-44b1-bd9f-390f871b2423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921728595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.921728595
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4260819643
Short name T890
Test name
Test status
Simulation time 404413256 ps
CPU time 1.55 seconds
Started Feb 28 04:18:29 PM PST 24
Finished Feb 28 04:18:30 PM PST 24
Peak memory 200568 kb
Host smart-af4ec8b9-79e1-4fdd-867a-2c5883b5fb5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260819643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4260819643
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.129597151
Short name T837
Test name
Test status
Simulation time 417066707 ps
CPU time 1.12 seconds
Started Feb 28 04:18:04 PM PST 24
Finished Feb 28 04:18:06 PM PST 24
Peak memory 200520 kb
Host smart-ea692b6b-bf24-4616-bd94-b3afa5d16142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129597151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.129597151
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.751303141
Short name T836
Test name
Test status
Simulation time 428773794 ps
CPU time 0.88 seconds
Started Feb 28 04:18:06 PM PST 24
Finished Feb 28 04:18:08 PM PST 24
Peak memory 200676 kb
Host smart-c9eaf7d4-f396-4b5e-98d3-d10e49e91197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751303141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.751303141
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.616877553
Short name T820
Test name
Test status
Simulation time 527220138 ps
CPU time 1.23 seconds
Started Feb 28 04:18:18 PM PST 24
Finished Feb 28 04:18:20 PM PST 24
Peak memory 200560 kb
Host smart-3eac4244-1dd8-4a17-b231-4ae704db6c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616877553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.616877553
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1172345600
Short name T801
Test name
Test status
Simulation time 575681030 ps
CPU time 2.29 seconds
Started Feb 28 04:17:40 PM PST 24
Finished Feb 28 04:17:43 PM PST 24
Peak memory 200884 kb
Host smart-b20ad054-8e31-4067-8626-c59982091f41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172345600 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1172345600
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2512842458
Short name T88
Test name
Test status
Simulation time 339381531 ps
CPU time 1.62 seconds
Started Feb 28 04:17:50 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 200776 kb
Host smart-72ed65ef-80f3-45e1-ac4a-b88a6ff09672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512842458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2512842458
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3324135075
Short name T792
Test name
Test status
Simulation time 349709569 ps
CPU time 1.35 seconds
Started Feb 28 04:17:40 PM PST 24
Finished Feb 28 04:17:42 PM PST 24
Peak memory 200560 kb
Host smart-7025e2eb-7723-4e4b-8ad5-14f47389e8b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324135075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3324135075
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2256263093
Short name T33
Test name
Test status
Simulation time 3673764421 ps
CPU time 9.33 seconds
Started Feb 28 04:17:40 PM PST 24
Finished Feb 28 04:17:50 PM PST 24
Peak memory 201012 kb
Host smart-ec9ad04c-1627-41ea-b51c-a0e917ff8be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256263093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2256263093
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4120909630
Short name T862
Test name
Test status
Simulation time 442709147 ps
CPU time 1.38 seconds
Started Feb 28 04:17:32 PM PST 24
Finished Feb 28 04:17:34 PM PST 24
Peak memory 201108 kb
Host smart-fdf29f2e-8035-43ee-9112-0ccafb199c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120909630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4120909630
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2984749384
Short name T328
Test name
Test status
Simulation time 4457966989 ps
CPU time 4.03 seconds
Started Feb 28 04:17:43 PM PST 24
Finished Feb 28 04:17:47 PM PST 24
Peak memory 201056 kb
Host smart-73ad273d-7bff-4248-b0fa-f751dfdc1dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984749384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2984749384
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1382325590
Short name T832
Test name
Test status
Simulation time 528366157 ps
CPU time 1.42 seconds
Started Feb 28 04:17:58 PM PST 24
Finished Feb 28 04:18:00 PM PST 24
Peak memory 200812 kb
Host smart-c91209e2-a89c-489c-b55a-3ca204a44992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382325590 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1382325590
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.918552809
Short name T86
Test name
Test status
Simulation time 486176489 ps
CPU time 1.15 seconds
Started Feb 28 04:17:41 PM PST 24
Finished Feb 28 04:17:43 PM PST 24
Peak memory 200784 kb
Host smart-48d2f27b-c249-41d0-a6ee-12c79b97be44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918552809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.918552809
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2836995436
Short name T835
Test name
Test status
Simulation time 385856673 ps
CPU time 0.85 seconds
Started Feb 28 04:17:32 PM PST 24
Finished Feb 28 04:17:33 PM PST 24
Peak memory 200584 kb
Host smart-db77881b-788a-4974-8482-1073d370e5a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836995436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2836995436
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3159138231
Short name T827
Test name
Test status
Simulation time 1975421624 ps
CPU time 3.32 seconds
Started Feb 28 04:17:33 PM PST 24
Finished Feb 28 04:17:36 PM PST 24
Peak memory 200780 kb
Host smart-9ed8b1fa-214a-4ad0-8f35-df97dfea9d4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159138231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3159138231
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2950514396
Short name T896
Test name
Test status
Simulation time 525988269 ps
CPU time 1.77 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:32 PM PST 24
Peak memory 201100 kb
Host smart-26262411-b364-410e-82d5-2b84d56762f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950514396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2950514396
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.224731360
Short name T838
Test name
Test status
Simulation time 4620799851 ps
CPU time 7.13 seconds
Started Feb 28 04:17:31 PM PST 24
Finished Feb 28 04:17:38 PM PST 24
Peak memory 201032 kb
Host smart-074c88f7-812d-4af3-be1f-e34a352911a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224731360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.224731360
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1134357483
Short name T807
Test name
Test status
Simulation time 502786136 ps
CPU time 1.39 seconds
Started Feb 28 04:17:34 PM PST 24
Finished Feb 28 04:17:36 PM PST 24
Peak memory 200840 kb
Host smart-6927daa6-8024-40ff-8f80-913a778b0758
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134357483 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1134357483
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1369860459
Short name T90
Test name
Test status
Simulation time 375023451 ps
CPU time 1.27 seconds
Started Feb 28 04:18:01 PM PST 24
Finished Feb 28 04:18:03 PM PST 24
Peak memory 200792 kb
Host smart-c0792cdf-9696-4e08-8cfd-abffcc76d633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369860459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1369860459
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.581083464
Short name T797
Test name
Test status
Simulation time 485458578 ps
CPU time 1.67 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:32 PM PST 24
Peak memory 200716 kb
Host smart-f0b2e5dd-5d68-4681-8484-91fd0b30323a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581083464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.581083464
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.28787207
Short name T817
Test name
Test status
Simulation time 2282570061 ps
CPU time 9.9 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:40 PM PST 24
Peak memory 200924 kb
Host smart-c67e5c8a-c56b-413b-9d20-56d425383f0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28787207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctr
l_same_csr_outstanding.28787207
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.270976134
Short name T41
Test name
Test status
Simulation time 482388286 ps
CPU time 2.2 seconds
Started Feb 28 04:17:34 PM PST 24
Finished Feb 28 04:17:37 PM PST 24
Peak memory 201084 kb
Host smart-6152ad12-99d1-4ba5-872d-6682c405f6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270976134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.270976134
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.162109515
Short name T329
Test name
Test status
Simulation time 4553405060 ps
CPU time 3.88 seconds
Started Feb 28 04:17:27 PM PST 24
Finished Feb 28 04:17:31 PM PST 24
Peak memory 201044 kb
Host smart-5f43c00e-f4d9-44d0-b558-6a4a0d310cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162109515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.162109515
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.414469433
Short name T863
Test name
Test status
Simulation time 532598045 ps
CPU time 1.22 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:32 PM PST 24
Peak memory 200848 kb
Host smart-1e3cf50b-2cbd-4dff-84a5-823be3cb4b1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414469433 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.414469433
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2654882055
Short name T74
Test name
Test status
Simulation time 478485510 ps
CPU time 0.82 seconds
Started Feb 28 04:17:49 PM PST 24
Finished Feb 28 04:17:51 PM PST 24
Peak memory 200728 kb
Host smart-2c02856c-e982-4dec-b851-e8b3f1f7ce3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654882055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2654882055
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.799087188
Short name T905
Test name
Test status
Simulation time 413817758 ps
CPU time 1.65 seconds
Started Feb 28 04:17:44 PM PST 24
Finished Feb 28 04:17:46 PM PST 24
Peak memory 200636 kb
Host smart-8c214761-21df-4b60-8bd4-2099e840124e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799087188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.799087188
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3912035234
Short name T94
Test name
Test status
Simulation time 4923011398 ps
CPU time 11.86 seconds
Started Feb 28 04:17:55 PM PST 24
Finished Feb 28 04:18:07 PM PST 24
Peak memory 201036 kb
Host smart-a9b04019-0b60-45fa-ad5d-3fd6d5981f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912035234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3912035234
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1260822528
Short name T834
Test name
Test status
Simulation time 525958857 ps
CPU time 1.71 seconds
Started Feb 28 04:17:46 PM PST 24
Finished Feb 28 04:17:48 PM PST 24
Peak memory 200800 kb
Host smart-feccd252-ba20-444c-b63a-1f543f687d78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260822528 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1260822528
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3411174202
Short name T844
Test name
Test status
Simulation time 523475861 ps
CPU time 1.06 seconds
Started Feb 28 04:17:37 PM PST 24
Finished Feb 28 04:17:38 PM PST 24
Peak memory 200784 kb
Host smart-37ef580b-2b1c-46fc-8532-731ee0a5b296
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411174202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3411174202
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.230573437
Short name T790
Test name
Test status
Simulation time 359583660 ps
CPU time 1.03 seconds
Started Feb 28 04:17:36 PM PST 24
Finished Feb 28 04:17:38 PM PST 24
Peak memory 200684 kb
Host smart-3768f655-c36a-4d57-a420-df9dc9cb2d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230573437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.230573437
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2114773360
Short name T901
Test name
Test status
Simulation time 5267183117 ps
CPU time 2.5 seconds
Started Feb 28 04:17:48 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 201036 kb
Host smart-fa337e61-ef3a-4caf-8c0a-ea597781808a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114773360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2114773360
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3148443515
Short name T831
Test name
Test status
Simulation time 440974481 ps
CPU time 1.57 seconds
Started Feb 28 04:17:28 PM PST 24
Finished Feb 28 04:17:30 PM PST 24
Peak memory 201092 kb
Host smart-84f5e9a0-d16c-4432-98b2-f819696e3635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148443515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3148443515
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3992384353
Short name T37
Test name
Test status
Simulation time 4566276231 ps
CPU time 3.51 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:34 PM PST 24
Peak memory 201276 kb
Host smart-bb5e7d84-4ef7-4aa8-8621-34b04b57dcd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992384353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3992384353
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.966867064
Short name T445
Test name
Test status
Simulation time 488472665 ps
CPU time 1.69 seconds
Started Feb 28 04:24:47 PM PST 24
Finished Feb 28 04:24:49 PM PST 24
Peak memory 201056 kb
Host smart-f4855ce8-9708-46b9-827a-acef14538513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966867064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.966867064
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1240341263
Short name T250
Test name
Test status
Simulation time 332405600080 ps
CPU time 367.29 seconds
Started Feb 28 04:24:27 PM PST 24
Finished Feb 28 04:30:35 PM PST 24
Peak memory 201404 kb
Host smart-b34aface-d6e8-4e77-9773-923847097f1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240341263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1240341263
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1064818538
Short name T262
Test name
Test status
Simulation time 173890441005 ps
CPU time 224.56 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:28:45 PM PST 24
Peak memory 201352 kb
Host smart-bc9d5b77-f68a-4e47-ac65-6c974690f95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064818538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1064818538
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3653869845
Short name T304
Test name
Test status
Simulation time 161453923706 ps
CPU time 26.93 seconds
Started Feb 28 04:24:56 PM PST 24
Finished Feb 28 04:25:23 PM PST 24
Peak memory 201372 kb
Host smart-15617461-1c14-4102-ac55-7aebf76d7cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653869845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3653869845
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3436988270
Short name T603
Test name
Test status
Simulation time 497120257948 ps
CPU time 347.51 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:30:45 PM PST 24
Peak memory 201312 kb
Host smart-3f9094cc-7e7a-407b-9d9a-b5f03049c814
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436988270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3436988270
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3683460252
Short name T644
Test name
Test status
Simulation time 328047035726 ps
CPU time 197.85 seconds
Started Feb 28 04:25:02 PM PST 24
Finished Feb 28 04:28:20 PM PST 24
Peak memory 201340 kb
Host smart-445b24d5-2772-4ad5-ad69-f6bb6bc65eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683460252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3683460252
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1699505963
Short name T476
Test name
Test status
Simulation time 331714347201 ps
CPU time 212.22 seconds
Started Feb 28 04:24:43 PM PST 24
Finished Feb 28 04:28:16 PM PST 24
Peak memory 201376 kb
Host smart-c5c0a281-d043-49db-96a7-cd20e2d42a73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699505963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1699505963
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1624016133
Short name T283
Test name
Test status
Simulation time 167451148911 ps
CPU time 362.44 seconds
Started Feb 28 04:25:08 PM PST 24
Finished Feb 28 04:31:11 PM PST 24
Peak memory 201360 kb
Host smart-e3bbaffa-16dc-4c28-9e1f-5b127f60e1c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624016133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1624016133
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.41343801
Short name T413
Test name
Test status
Simulation time 333727966283 ps
CPU time 198.05 seconds
Started Feb 28 04:24:31 PM PST 24
Finished Feb 28 04:27:50 PM PST 24
Peak memory 201408 kb
Host smart-5abdfbeb-6d68-4a8b-bbc2-9ad6cfa08071
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41343801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ad
c_ctrl_filters_wakeup_fixed.41343801
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1374217585
Short name T698
Test name
Test status
Simulation time 117936899333 ps
CPU time 345.07 seconds
Started Feb 28 04:24:29 PM PST 24
Finished Feb 28 04:30:14 PM PST 24
Peak memory 201676 kb
Host smart-45bbaf84-f39f-46c8-bedc-32c17a76a2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374217585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1374217585
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3622236594
Short name T700
Test name
Test status
Simulation time 39041226358 ps
CPU time 59.7 seconds
Started Feb 28 04:24:31 PM PST 24
Finished Feb 28 04:25:32 PM PST 24
Peak memory 201224 kb
Host smart-e63038d6-2f82-4b33-840c-60c71147a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622236594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3622236594
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.140901342
Short name T598
Test name
Test status
Simulation time 4602847924 ps
CPU time 3.1 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:24:48 PM PST 24
Peak memory 201204 kb
Host smart-59d33c67-508b-417d-acea-e8e2d2c0e91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140901342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.140901342
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.781615792
Short name T725
Test name
Test status
Simulation time 5884670976 ps
CPU time 7.34 seconds
Started Feb 28 04:24:49 PM PST 24
Finished Feb 28 04:24:57 PM PST 24
Peak memory 201092 kb
Host smart-5f371423-eabc-46a4-a062-b4634ea30945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781615792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.781615792
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3261621630
Short name T53
Test name
Test status
Simulation time 182219838759 ps
CPU time 112.92 seconds
Started Feb 28 04:24:36 PM PST 24
Finished Feb 28 04:26:30 PM PST 24
Peak memory 209792 kb
Host smart-66ef8d88-1511-43ed-92da-ef5f6f3f6d6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261621630 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3261621630
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.265254109
Short name T617
Test name
Test status
Simulation time 160855023617 ps
CPU time 87.1 seconds
Started Feb 28 04:24:34 PM PST 24
Finished Feb 28 04:26:01 PM PST 24
Peak memory 201416 kb
Host smart-6e5a60df-3783-478f-9afe-88040de56552
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265254109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.265254109
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1080857936
Short name T618
Test name
Test status
Simulation time 489480522213 ps
CPU time 1218.01 seconds
Started Feb 28 04:24:32 PM PST 24
Finished Feb 28 04:44:50 PM PST 24
Peak memory 201452 kb
Host smart-a8dcc3df-7ceb-45db-8c39-2f699cb620da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080857936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1080857936
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4142401223
Short name T293
Test name
Test status
Simulation time 164675680341 ps
CPU time 217.55 seconds
Started Feb 28 04:24:42 PM PST 24
Finished Feb 28 04:28:20 PM PST 24
Peak memory 201476 kb
Host smart-0e2225e0-49b4-4e32-accd-7bd437db68e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142401223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4142401223
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2810796940
Short name T639
Test name
Test status
Simulation time 335012890639 ps
CPU time 199.39 seconds
Started Feb 28 04:24:47 PM PST 24
Finished Feb 28 04:28:07 PM PST 24
Peak memory 201464 kb
Host smart-7897a69d-542f-420d-aaa8-0cd4bfe738f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810796940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2810796940
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2650554171
Short name T607
Test name
Test status
Simulation time 165636887822 ps
CPU time 179.65 seconds
Started Feb 28 04:24:35 PM PST 24
Finished Feb 28 04:27:35 PM PST 24
Peak memory 201404 kb
Host smart-fc28b770-ce81-45c0-9a78-987b166666d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650554171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2650554171
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1455624185
Short name T175
Test name
Test status
Simulation time 76719558955 ps
CPU time 419.37 seconds
Started Feb 28 04:24:52 PM PST 24
Finished Feb 28 04:31:51 PM PST 24
Peak memory 201720 kb
Host smart-e4b1424f-78ef-4d88-a0d4-05c632edccd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455624185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1455624185
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.83332796
Short name T544
Test name
Test status
Simulation time 42578758705 ps
CPU time 25.16 seconds
Started Feb 28 04:24:30 PM PST 24
Finished Feb 28 04:24:55 PM PST 24
Peak memory 201196 kb
Host smart-1c769c1b-6108-47d0-b824-bfe679f33da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83332796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.83332796
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2787874404
Short name T127
Test name
Test status
Simulation time 2906921610 ps
CPU time 2.83 seconds
Started Feb 28 04:24:49 PM PST 24
Finished Feb 28 04:24:52 PM PST 24
Peak memory 201280 kb
Host smart-bd81652f-2c66-42da-b06e-680773f378cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787874404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2787874404
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3042435950
Short name T48
Test name
Test status
Simulation time 4306356633 ps
CPU time 5.5 seconds
Started Feb 28 04:24:49 PM PST 24
Finished Feb 28 04:24:55 PM PST 24
Peak memory 216352 kb
Host smart-489f500f-4958-42c4-8e28-b989b3266d31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042435950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3042435950
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.594177440
Short name T58
Test name
Test status
Simulation time 5741370924 ps
CPU time 3.35 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:24:49 PM PST 24
Peak memory 201196 kb
Host smart-df67bd0d-05ec-4589-b11c-bc4440d5fcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594177440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.594177440
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1621715118
Short name T64
Test name
Test status
Simulation time 587728045686 ps
CPU time 416.44 seconds
Started Feb 28 04:24:39 PM PST 24
Finished Feb 28 04:31:36 PM PST 24
Peak memory 210116 kb
Host smart-135ef00c-8ee1-4f76-9520-c2331d7f9dca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621715118 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1621715118
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3692433415
Short name T736
Test name
Test status
Simulation time 405546915 ps
CPU time 0.92 seconds
Started Feb 28 04:26:34 PM PST 24
Finished Feb 28 04:26:37 PM PST 24
Peak memory 201064 kb
Host smart-aea8d400-e155-4907-a948-9ab9341549f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692433415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3692433415
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2980389925
Short name T194
Test name
Test status
Simulation time 164448963266 ps
CPU time 307.49 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:30:20 PM PST 24
Peak memory 201492 kb
Host smart-f108501a-daee-427f-b196-edcc3d2d1369
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980389925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2980389925
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3287328998
Short name T324
Test name
Test status
Simulation time 482989434363 ps
CPU time 593.25 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:35:12 PM PST 24
Peak memory 201232 kb
Host smart-59298f21-a20d-4898-a55a-53537f4c057e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287328998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3287328998
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3794526514
Short name T496
Test name
Test status
Simulation time 327773415806 ps
CPU time 72.16 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:26:25 PM PST 24
Peak memory 201444 kb
Host smart-364a2f70-b1b1-4e9e-af12-d9ae4f459c96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794526514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3794526514
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.886045994
Short name T229
Test name
Test status
Simulation time 488016567365 ps
CPU time 1161.64 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:44:23 PM PST 24
Peak memory 201400 kb
Host smart-17ebec99-1bc0-49d0-b495-0958f4b04364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886045994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.886045994
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.790790749
Short name T437
Test name
Test status
Simulation time 161952669361 ps
CPU time 72.55 seconds
Started Feb 28 04:25:03 PM PST 24
Finished Feb 28 04:26:20 PM PST 24
Peak memory 201304 kb
Host smart-75c4ec2f-ad00-45cc-b376-e044c7d3e4db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=790790749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.790790749
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3940093705
Short name T20
Test name
Test status
Simulation time 172672034489 ps
CPU time 203.55 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:28:36 PM PST 24
Peak memory 201356 kb
Host smart-5e00d2ce-6d33-42e8-811d-c659b4ea859f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940093705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3940093705
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.905916796
Short name T421
Test name
Test status
Simulation time 495927637017 ps
CPU time 567.62 seconds
Started Feb 28 04:26:34 PM PST 24
Finished Feb 28 04:36:03 PM PST 24
Peak memory 201296 kb
Host smart-d9586983-5f38-4f2e-ac12-7fd4c2efd89c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905916796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.905916796
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.4119271730
Short name T381
Test name
Test status
Simulation time 32382755836 ps
CPU time 65.72 seconds
Started Feb 28 04:24:56 PM PST 24
Finished Feb 28 04:26:02 PM PST 24
Peak memory 201088 kb
Host smart-48bf6b91-8e53-4939-b808-106a0c2c4269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119271730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.4119271730
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2979333921
Short name T616
Test name
Test status
Simulation time 3569929206 ps
CPU time 9.29 seconds
Started Feb 28 04:24:58 PM PST 24
Finished Feb 28 04:25:07 PM PST 24
Peak memory 201128 kb
Host smart-7f2ab1ac-1a96-44b6-8442-d1c87d75045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979333921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2979333921
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3344354272
Short name T363
Test name
Test status
Simulation time 5740282978 ps
CPU time 4.15 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:25:26 PM PST 24
Peak memory 201116 kb
Host smart-6f2bd228-66f8-40ef-81d9-d24e8dd84175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344354272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3344354272
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1785933790
Short name T165
Test name
Test status
Simulation time 15384868021 ps
CPU time 39.09 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:25:52 PM PST 24
Peak memory 209780 kb
Host smart-3cde0bb6-cc0d-4543-a0ff-4d86d249bac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785933790 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1785933790
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3589679893
Short name T474
Test name
Test status
Simulation time 361450186 ps
CPU time 1.43 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:25:07 PM PST 24
Peak memory 201020 kb
Host smart-5a73c8f9-20a1-4025-913d-8ff3afb0a85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589679893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3589679893
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3191661626
Short name T590
Test name
Test status
Simulation time 492961438961 ps
CPU time 137.74 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:27:23 PM PST 24
Peak memory 201444 kb
Host smart-4c28d9e3-d602-45a4-92be-a7908bcfc040
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191661626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3191661626
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.282767859
Short name T255
Test name
Test status
Simulation time 495097901191 ps
CPU time 320.67 seconds
Started Feb 28 04:24:56 PM PST 24
Finished Feb 28 04:30:17 PM PST 24
Peak memory 201388 kb
Host smart-add09ca4-3849-48b1-8dd3-cde08ce8e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282767859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.282767859
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3526460569
Short name T296
Test name
Test status
Simulation time 161167744749 ps
CPU time 344.78 seconds
Started Feb 28 04:25:22 PM PST 24
Finished Feb 28 04:31:07 PM PST 24
Peak memory 201368 kb
Host smart-b44495dd-6504-45a8-ba67-0e4cf56a90be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526460569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3526460569
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3181100888
Short name T400
Test name
Test status
Simulation time 159397218118 ps
CPU time 181.93 seconds
Started Feb 28 04:25:01 PM PST 24
Finished Feb 28 04:28:03 PM PST 24
Peak memory 201380 kb
Host smart-d0ac8ed2-366d-4c7b-8b79-aad9d7e02be6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181100888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3181100888
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3966105470
Short name T142
Test name
Test status
Simulation time 504248973910 ps
CPU time 226.29 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:28:59 PM PST 24
Peak memory 201244 kb
Host smart-0c149583-6e6c-41cf-8eef-6559dfb67675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966105470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3966105470
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1523216625
Short name T528
Test name
Test status
Simulation time 493786128301 ps
CPU time 1109.86 seconds
Started Feb 28 04:25:04 PM PST 24
Finished Feb 28 04:43:35 PM PST 24
Peak memory 201380 kb
Host smart-5fa60ca6-859d-4698-ae8f-967c17283178
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523216625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1523216625
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1140368727
Short name T201
Test name
Test status
Simulation time 327600702105 ps
CPU time 200.67 seconds
Started Feb 28 04:25:03 PM PST 24
Finished Feb 28 04:28:23 PM PST 24
Peak memory 201320 kb
Host smart-4ac5aa67-feac-4d53-a311-abe1b7b87ec9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140368727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1140368727
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1188780368
Short name T361
Test name
Test status
Simulation time 324129250355 ps
CPU time 330.65 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:30:43 PM PST 24
Peak memory 201272 kb
Host smart-7887451f-9e4b-4e92-86a5-bc6d11699958
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188780368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1188780368
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4090474597
Short name T31
Test name
Test status
Simulation time 120129182628 ps
CPU time 508.92 seconds
Started Feb 28 04:24:58 PM PST 24
Finished Feb 28 04:33:27 PM PST 24
Peak memory 201668 kb
Host smart-af392436-91a6-4aad-b905-3dfab30a3987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090474597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4090474597
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3630854388
Short name T507
Test name
Test status
Simulation time 35500105838 ps
CPU time 66.04 seconds
Started Feb 28 04:24:59 PM PST 24
Finished Feb 28 04:26:05 PM PST 24
Peak memory 201156 kb
Host smart-fc6018e1-a28a-4611-8687-9af2fd0412c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630854388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3630854388
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2667084563
Short name T375
Test name
Test status
Simulation time 4972955218 ps
CPU time 6.26 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:25:07 PM PST 24
Peak memory 201088 kb
Host smart-4abbc8b1-52b3-4163-966a-460efca00d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667084563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2667084563
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1744362872
Short name T556
Test name
Test status
Simulation time 5837744197 ps
CPU time 8 seconds
Started Feb 28 04:25:07 PM PST 24
Finished Feb 28 04:25:15 PM PST 24
Peak memory 201116 kb
Host smart-eb52a8a8-2ad8-4cfb-93fe-bd591363e9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744362872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1744362872
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.50607537
Short name T471
Test name
Test status
Simulation time 170986301218 ps
CPU time 93.36 seconds
Started Feb 28 04:25:01 PM PST 24
Finished Feb 28 04:26:35 PM PST 24
Peak memory 201412 kb
Host smart-f66a94d5-9469-46f8-97e9-33cf53d09c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50607537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.50607537
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2239557528
Short name T166
Test name
Test status
Simulation time 66431913220 ps
CPU time 115.82 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:26:53 PM PST 24
Peak memory 209640 kb
Host smart-2a7f45b6-797b-4218-be86-221f551af190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239557528 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2239557528
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3291594176
Short name T784
Test name
Test status
Simulation time 465739444 ps
CPU time 0.81 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:24:58 PM PST 24
Peak memory 201092 kb
Host smart-d5340491-54c7-4329-a2e5-389549b4f76f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291594176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3291594176
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.237599171
Short name T538
Test name
Test status
Simulation time 159512302513 ps
CPU time 158.77 seconds
Started Feb 28 04:24:53 PM PST 24
Finished Feb 28 04:27:32 PM PST 24
Peak memory 201244 kb
Host smart-1b2af4ac-736a-4e67-9608-ca3b58272c59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237599171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.237599171
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1818472012
Short name T614
Test name
Test status
Simulation time 165350268069 ps
CPU time 203.6 seconds
Started Feb 28 04:25:14 PM PST 24
Finished Feb 28 04:28:37 PM PST 24
Peak memory 201464 kb
Host smart-e4bfaa15-37d8-4f0a-8102-7b27bfac5f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818472012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1818472012
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2626037696
Short name T760
Test name
Test status
Simulation time 324623407673 ps
CPU time 57.3 seconds
Started Feb 28 04:24:54 PM PST 24
Finished Feb 28 04:25:51 PM PST 24
Peak memory 201452 kb
Host smart-9285d899-1c72-4db5-8167-11748039bb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626037696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2626037696
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3952024378
Short name T332
Test name
Test status
Simulation time 335300970823 ps
CPU time 755.28 seconds
Started Feb 28 04:25:10 PM PST 24
Finished Feb 28 04:37:45 PM PST 24
Peak memory 201412 kb
Host smart-702aafb6-8b69-4ec5-862f-b7adc7e588c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952024378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3952024378
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.932207973
Short name T202
Test name
Test status
Simulation time 500090841145 ps
CPU time 1127.55 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:43:53 PM PST 24
Peak memory 201264 kb
Host smart-da14f573-8ddb-47e2-b1a2-80d5a14636f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932207973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.932207973
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3794293650
Short name T354
Test name
Test status
Simulation time 321440834508 ps
CPU time 141.43 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:27:22 PM PST 24
Peak memory 201388 kb
Host smart-3cb7f8e7-3ff5-46cf-9476-64204221a1a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794293650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3794293650
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3742765749
Short name T105
Test name
Test status
Simulation time 164953414610 ps
CPU time 24.79 seconds
Started Feb 28 04:25:19 PM PST 24
Finished Feb 28 04:25:44 PM PST 24
Peak memory 201404 kb
Host smart-0f8f916a-9e09-4437-ac89-e34fa5ae35cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742765749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3742765749
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3262630170
Short name T418
Test name
Test status
Simulation time 158256793191 ps
CPU time 36.08 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:25:48 PM PST 24
Peak memory 201400 kb
Host smart-8f7742d7-8703-4c5e-a9a8-b1a3b5b8b055
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262630170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3262630170
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4264509350
Short name T650
Test name
Test status
Simulation time 28110273280 ps
CPU time 9.06 seconds
Started Feb 28 04:25:07 PM PST 24
Finished Feb 28 04:25:16 PM PST 24
Peak memory 201204 kb
Host smart-7842daa1-3ef1-46f6-abd1-a8a762df758c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264509350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4264509350
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1922472374
Short name T456
Test name
Test status
Simulation time 3521728957 ps
CPU time 2.94 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:25:00 PM PST 24
Peak memory 201088 kb
Host smart-18179cc5-9fd3-4cb7-8ef5-df9b1f060306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922472374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1922472374
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1025834267
Short name T684
Test name
Test status
Simulation time 6027053943 ps
CPU time 3.82 seconds
Started Feb 28 04:25:10 PM PST 24
Finished Feb 28 04:25:14 PM PST 24
Peak memory 201120 kb
Host smart-d6046edf-e1d7-4c81-9681-03899afc3b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025834267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1025834267
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2301965412
Short name T167
Test name
Test status
Simulation time 496743640289 ps
CPU time 1121.81 seconds
Started Feb 28 04:24:48 PM PST 24
Finished Feb 28 04:43:30 PM PST 24
Peak memory 201380 kb
Host smart-29b7ef21-bd0d-474f-bf56-cdc28c9b98eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301965412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2301965412
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1093069126
Short name T527
Test name
Test status
Simulation time 509263505 ps
CPU time 0.87 seconds
Started Feb 28 04:25:09 PM PST 24
Finished Feb 28 04:25:10 PM PST 24
Peak memory 201116 kb
Host smart-5b30fe50-8688-4c86-be54-dc7e23ebe89c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093069126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1093069126
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3288977752
Short name T275
Test name
Test status
Simulation time 323973692342 ps
CPU time 736.57 seconds
Started Feb 28 04:25:14 PM PST 24
Finished Feb 28 04:37:30 PM PST 24
Peak memory 201484 kb
Host smart-794f15ae-e8df-492d-bb1a-2078343cc5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288977752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3288977752
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3535676069
Short name T146
Test name
Test status
Simulation time 159056408990 ps
CPU time 25.91 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:25:44 PM PST 24
Peak memory 201400 kb
Host smart-dd44bf91-5450-450f-89f8-33c9299fa7cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535676069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3535676069
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3136798950
Short name T602
Test name
Test status
Simulation time 495705008634 ps
CPU time 565.16 seconds
Started Feb 28 04:24:53 PM PST 24
Finished Feb 28 04:34:19 PM PST 24
Peak memory 201408 kb
Host smart-e725a314-7844-4592-879f-1c3a80f41c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136798950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3136798950
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2334289760
Short name T723
Test name
Test status
Simulation time 493298137339 ps
CPU time 272.99 seconds
Started Feb 28 04:25:09 PM PST 24
Finished Feb 28 04:29:42 PM PST 24
Peak memory 201384 kb
Host smart-1b85a5b8-00d1-4779-8035-3e59fde59d7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334289760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2334289760
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.46515533
Short name T65
Test name
Test status
Simulation time 163560646905 ps
CPU time 368.91 seconds
Started Feb 28 04:25:20 PM PST 24
Finished Feb 28 04:31:29 PM PST 24
Peak memory 201400 kb
Host smart-a63c516e-dfde-4cc6-b1ed-f671c8c5ef6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46515533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_w
akeup.46515533
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3440626234
Short name T689
Test name
Test status
Simulation time 162635976601 ps
CPU time 176.53 seconds
Started Feb 28 04:25:02 PM PST 24
Finished Feb 28 04:27:59 PM PST 24
Peak memory 201412 kb
Host smart-a5751bb9-89d8-492d-b23d-11464078fb0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440626234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3440626234
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1032669552
Short name T16
Test name
Test status
Simulation time 84216612151 ps
CPU time 362.42 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:31:21 PM PST 24
Peak memory 201768 kb
Host smart-2ca5ed0b-a45e-4a02-b33d-9ddbe593d739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032669552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1032669552
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3756142154
Short name T485
Test name
Test status
Simulation time 25023996476 ps
CPU time 16 seconds
Started Feb 28 04:25:15 PM PST 24
Finished Feb 28 04:25:31 PM PST 24
Peak memory 201160 kb
Host smart-00a13c9f-e71c-4c1b-835d-26a68937ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756142154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3756142154
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2878648418
Short name T718
Test name
Test status
Simulation time 4262626282 ps
CPU time 6.17 seconds
Started Feb 28 04:25:10 PM PST 24
Finished Feb 28 04:25:16 PM PST 24
Peak memory 201284 kb
Host smart-dc97e749-a121-4199-af35-992fbd1e8900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878648418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2878648418
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2882216796
Short name T742
Test name
Test status
Simulation time 6098223360 ps
CPU time 1.7 seconds
Started Feb 28 04:24:50 PM PST 24
Finished Feb 28 04:24:52 PM PST 24
Peak memory 201200 kb
Host smart-df89ed1e-6d6e-452c-8fdf-d6c44b0d28df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882216796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2882216796
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.303904706
Short name T541
Test name
Test status
Simulation time 433783359 ps
CPU time 1 seconds
Started Feb 28 04:25:19 PM PST 24
Finished Feb 28 04:25:20 PM PST 24
Peak memory 201212 kb
Host smart-6761e0fa-110f-4420-92fd-e8763f4a6a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303904706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.303904706
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3475823963
Short name T226
Test name
Test status
Simulation time 162578151716 ps
CPU time 377.65 seconds
Started Feb 28 04:25:06 PM PST 24
Finished Feb 28 04:31:25 PM PST 24
Peak memory 201536 kb
Host smart-cc540262-e539-46a9-9864-fd05412680b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475823963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3475823963
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3559501034
Short name T259
Test name
Test status
Simulation time 336064073599 ps
CPU time 719.5 seconds
Started Feb 28 04:25:16 PM PST 24
Finished Feb 28 04:37:16 PM PST 24
Peak memory 201464 kb
Host smart-395b8616-9ec4-4413-83e9-ac0668cefe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559501034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3559501034
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2670382754
Short name T140
Test name
Test status
Simulation time 334951985023 ps
CPU time 740.13 seconds
Started Feb 28 04:24:56 PM PST 24
Finished Feb 28 04:37:16 PM PST 24
Peak memory 201460 kb
Host smart-a9c8ab9e-fefb-4236-adfe-45d52297b828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670382754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2670382754
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.4056170807
Short name T438
Test name
Test status
Simulation time 165839048518 ps
CPU time 98.44 seconds
Started Feb 28 04:25:14 PM PST 24
Finished Feb 28 04:26:52 PM PST 24
Peak memory 201356 kb
Host smart-b0e6653f-8fd3-4c58-90c3-c41ba0e160c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056170807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.4056170807
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.243233903
Short name T313
Test name
Test status
Simulation time 157935968468 ps
CPU time 196.28 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:28:35 PM PST 24
Peak memory 201480 kb
Host smart-46222c28-1072-4788-9d8a-022a4edfcb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243233903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.243233903
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.4045451923
Short name T376
Test name
Test status
Simulation time 164241153175 ps
CPU time 413.73 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:31:54 PM PST 24
Peak memory 201508 kb
Host smart-4dffd107-59ed-4f16-9bb1-ba46978ce83f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045451923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.4045451923
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1480534044
Short name T540
Test name
Test status
Simulation time 339743840291 ps
CPU time 827.38 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:38:48 PM PST 24
Peak memory 201456 kb
Host smart-a4f003b5-cb2e-4ec9-983e-f55bad88bdc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480534044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1480534044
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3750198585
Short name T346
Test name
Test status
Simulation time 497611606102 ps
CPU time 315.41 seconds
Started Feb 28 04:24:55 PM PST 24
Finished Feb 28 04:30:11 PM PST 24
Peak memory 201396 kb
Host smart-76347567-9923-4a3b-949c-e67b18264068
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750198585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3750198585
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.345601664
Short name T577
Test name
Test status
Simulation time 90792221259 ps
CPU time 305.11 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:30:10 PM PST 24
Peak memory 201664 kb
Host smart-8cbc88e9-4256-4960-bf11-3d665e1ae432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345601664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.345601664
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.70287279
Short name T340
Test name
Test status
Simulation time 31668155326 ps
CPU time 37.82 seconds
Started Feb 28 04:25:14 PM PST 24
Finished Feb 28 04:25:51 PM PST 24
Peak memory 201100 kb
Host smart-16122835-95c4-413a-a647-ae5fd51280e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70287279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.70287279
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1717309566
Short name T732
Test name
Test status
Simulation time 4052308559 ps
CPU time 5.34 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:25:24 PM PST 24
Peak memory 201200 kb
Host smart-40a4dec1-d9af-449b-865e-093c1d775a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717309566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1717309566
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2102724616
Short name T739
Test name
Test status
Simulation time 6028994770 ps
CPU time 15.45 seconds
Started Feb 28 04:25:09 PM PST 24
Finished Feb 28 04:25:25 PM PST 24
Peak memory 201028 kb
Host smart-1e383246-c623-45e8-b071-515d46a97aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102724616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2102724616
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1721184555
Short name T575
Test name
Test status
Simulation time 401921185 ps
CPU time 0.82 seconds
Started Feb 28 04:25:06 PM PST 24
Finished Feb 28 04:25:07 PM PST 24
Peak memory 201100 kb
Host smart-389cde51-5ae1-4cff-a790-a691a0b20821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721184555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1721184555
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4207169096
Short name T677
Test name
Test status
Simulation time 166898147171 ps
CPU time 367.26 seconds
Started Feb 28 04:25:07 PM PST 24
Finished Feb 28 04:31:15 PM PST 24
Peak memory 201448 kb
Host smart-91b67889-8731-4ca3-9604-283f910a5c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207169096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4207169096
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.301640464
Short name T763
Test name
Test status
Simulation time 167096447113 ps
CPU time 101.08 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:26:47 PM PST 24
Peak memory 201412 kb
Host smart-960825f1-fe25-475a-bf6f-9d87a2630c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301640464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.301640464
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1819955609
Short name T738
Test name
Test status
Simulation time 499290915383 ps
CPU time 454.69 seconds
Started Feb 28 04:25:15 PM PST 24
Finished Feb 28 04:32:50 PM PST 24
Peak memory 201360 kb
Host smart-66a8474e-0faa-43a9-b962-a331058fc0d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819955609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1819955609
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.867963860
Short name T297
Test name
Test status
Simulation time 335620803074 ps
CPU time 745.87 seconds
Started Feb 28 04:25:14 PM PST 24
Finished Feb 28 04:37:40 PM PST 24
Peak memory 201396 kb
Host smart-f50917e8-4b02-4c07-b4a4-269bfb13385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867963860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.867963860
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1219333845
Short name T503
Test name
Test status
Simulation time 161668550717 ps
CPU time 374.34 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:31:19 PM PST 24
Peak memory 201384 kb
Host smart-2444c906-1b26-40f7-9bda-c0e6fbdc29e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219333845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1219333845
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.643156949
Short name T110
Test name
Test status
Simulation time 165508627264 ps
CPU time 190.92 seconds
Started Feb 28 04:25:14 PM PST 24
Finished Feb 28 04:28:25 PM PST 24
Peak memory 201488 kb
Host smart-cded9303-3894-4cd8-85ca-dc28d7420db5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643156949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.643156949
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3266890
Short name T512
Test name
Test status
Simulation time 166776396941 ps
CPU time 193.74 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:28:19 PM PST 24
Peak memory 201528 kb
Host smart-58841b0f-5d18-4391-931c-5243483cb290
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.ad
c_ctrl_filters_wakeup_fixed.3266890
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3276306628
Short name T648
Test name
Test status
Simulation time 105694771680 ps
CPU time 556.25 seconds
Started Feb 28 04:25:06 PM PST 24
Finished Feb 28 04:34:32 PM PST 24
Peak memory 201632 kb
Host smart-ee1cbc3f-5b68-47a2-b3f5-8ac1db129894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276306628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3276306628
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.466278940
Short name T501
Test name
Test status
Simulation time 46646222419 ps
CPU time 82.42 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:26:35 PM PST 24
Peak memory 201212 kb
Host smart-d4deb878-b122-4b99-a3da-0263a04f281c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466278940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.466278940
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3492896148
Short name T499
Test name
Test status
Simulation time 4971065160 ps
CPU time 3.65 seconds
Started Feb 28 04:25:01 PM PST 24
Finished Feb 28 04:25:05 PM PST 24
Peak memory 201196 kb
Host smart-322f10d9-6477-4b1f-b474-b88c3bc28cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492896148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3492896148
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.227369403
Short name T711
Test name
Test status
Simulation time 6127410133 ps
CPU time 4.55 seconds
Started Feb 28 04:25:07 PM PST 24
Finished Feb 28 04:25:12 PM PST 24
Peak memory 201176 kb
Host smart-148092e9-69ad-4497-949e-3820c7cfcf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227369403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.227369403
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.541879896
Short name T708
Test name
Test status
Simulation time 426333365741 ps
CPU time 944.61 seconds
Started Feb 28 04:25:03 PM PST 24
Finished Feb 28 04:40:47 PM PST 24
Peak memory 201352 kb
Host smart-73ec50be-4cd7-4051-b921-2c98ba8d204d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541879896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
541879896
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.995272894
Short name T579
Test name
Test status
Simulation time 363503371 ps
CPU time 1.32 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:25:01 PM PST 24
Peak memory 201144 kb
Host smart-f60d4ba1-f7d1-4d90-8611-32e7a7e3ba06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995272894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.995272894
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4199817894
Short name T787
Test name
Test status
Simulation time 166139859760 ps
CPU time 174.51 seconds
Started Feb 28 04:25:01 PM PST 24
Finished Feb 28 04:27:56 PM PST 24
Peak memory 201308 kb
Host smart-a23b27d0-3b47-49b4-ac24-e2e9cc53843c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199817894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4199817894
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2769213854
Short name T681
Test name
Test status
Simulation time 162557774666 ps
CPU time 398.14 seconds
Started Feb 28 04:25:09 PM PST 24
Finished Feb 28 04:31:48 PM PST 24
Peak memory 201472 kb
Host smart-eec45bd5-f302-4e9f-bfe6-fa79b94889d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769213854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2769213854
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3320898924
Short name T151
Test name
Test status
Simulation time 487142777985 ps
CPU time 154.81 seconds
Started Feb 28 04:25:02 PM PST 24
Finished Feb 28 04:27:37 PM PST 24
Peak memory 201420 kb
Host smart-54ea8899-e37d-41b0-b64f-107b2dcdbf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320898924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3320898924
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2489139106
Short name T645
Test name
Test status
Simulation time 324190703221 ps
CPU time 751.22 seconds
Started Feb 28 04:25:03 PM PST 24
Finished Feb 28 04:37:35 PM PST 24
Peak memory 201352 kb
Host smart-4832b953-3322-4655-968d-c51bcff9913c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489139106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2489139106
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.881295237
Short name T509
Test name
Test status
Simulation time 335868698654 ps
CPU time 367.55 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:31:20 PM PST 24
Peak memory 201408 kb
Host smart-e9e96722-4531-4527-a81c-042b7a4c2503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881295237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.881295237
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.824705427
Short name T720
Test name
Test status
Simulation time 165095292597 ps
CPU time 83.35 seconds
Started Feb 28 04:25:08 PM PST 24
Finished Feb 28 04:26:32 PM PST 24
Peak memory 201304 kb
Host smart-a347b525-6724-4441-aa27-65b2d4572ce0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=824705427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.824705427
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.506194895
Short name T759
Test name
Test status
Simulation time 495344585887 ps
CPU time 758.04 seconds
Started Feb 28 04:25:34 PM PST 24
Finished Feb 28 04:38:12 PM PST 24
Peak memory 201400 kb
Host smart-38c0436d-5842-4433-8b56-2658aa6818fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506194895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.506194895
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.797373930
Short name T529
Test name
Test status
Simulation time 87196722529 ps
CPU time 349.2 seconds
Started Feb 28 04:24:59 PM PST 24
Finished Feb 28 04:30:48 PM PST 24
Peak memory 201724 kb
Host smart-0eb20f11-f4f0-4afb-94a6-c2b94d84228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797373930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.797373930
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2424807661
Short name T66
Test name
Test status
Simulation time 40657162681 ps
CPU time 101.46 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:26:46 PM PST 24
Peak memory 201072 kb
Host smart-7f025d30-b8d3-41dd-a57a-2b7e77ed5a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424807661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2424807661
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4065002268
Short name T729
Test name
Test status
Simulation time 3785776671 ps
CPU time 2.93 seconds
Started Feb 28 04:25:07 PM PST 24
Finished Feb 28 04:25:11 PM PST 24
Peak memory 201144 kb
Host smart-b74e3499-3756-4377-ad6a-1e3629161e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065002268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4065002268
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1076262101
Short name T504
Test name
Test status
Simulation time 5972425074 ps
CPU time 7.18 seconds
Started Feb 28 04:25:16 PM PST 24
Finished Feb 28 04:25:23 PM PST 24
Peak memory 201196 kb
Host smart-b429c204-fdaa-40a5-8456-939dc420cbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076262101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1076262101
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3997961001
Short name T213
Test name
Test status
Simulation time 206154074964 ps
CPU time 239.54 seconds
Started Feb 28 04:25:17 PM PST 24
Finished Feb 28 04:29:17 PM PST 24
Peak memory 201372 kb
Host smart-ed4ef3be-18bb-46bd-891d-6dc5c9db4c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997961001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3997961001
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1722557288
Short name T52
Test name
Test status
Simulation time 37986917006 ps
CPU time 81.11 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:26:18 PM PST 24
Peak memory 210184 kb
Host smart-416c3aad-c901-42ea-8855-90f3ed32dff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722557288 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1722557288
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1163182337
Short name T722
Test name
Test status
Simulation time 436758531 ps
CPU time 0.91 seconds
Started Feb 28 04:25:11 PM PST 24
Finished Feb 28 04:25:12 PM PST 24
Peak memory 201072 kb
Host smart-9fbd2a0a-9c49-4b82-804f-245136d7391c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163182337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1163182337
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3416667317
Short name T699
Test name
Test status
Simulation time 162398578697 ps
CPU time 5.63 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:25:25 PM PST 24
Peak memory 201380 kb
Host smart-11cab697-fcee-48b5-80a7-a12efc1f08da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416667317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3416667317
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4103341997
Short name T555
Test name
Test status
Simulation time 490157502409 ps
CPU time 554.22 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:34:36 PM PST 24
Peak memory 201404 kb
Host smart-082b7be0-10b4-4a86-b1aa-3b9d5362e182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103341997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4103341997
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.826545043
Short name T640
Test name
Test status
Simulation time 329412397190 ps
CPU time 322.1 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:30:43 PM PST 24
Peak memory 201404 kb
Host smart-84e5d0e3-7441-496e-899a-2bf1a046279c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=826545043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.826545043
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1859873254
Short name T443
Test name
Test status
Simulation time 326535783189 ps
CPU time 765.77 seconds
Started Feb 28 04:25:06 PM PST 24
Finished Feb 28 04:37:53 PM PST 24
Peak memory 201356 kb
Host smart-eb8e9a9e-8c86-484f-874e-75a5a9463dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859873254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1859873254
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1948512084
Short name T586
Test name
Test status
Simulation time 162206584484 ps
CPU time 212.12 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:28:54 PM PST 24
Peak memory 201432 kb
Host smart-5991b708-c7c5-4cbb-9b81-f60da7cee7ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948512084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1948512084
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1353567378
Short name T638
Test name
Test status
Simulation time 169703913841 ps
CPU time 99.05 seconds
Started Feb 28 04:25:19 PM PST 24
Finished Feb 28 04:26:58 PM PST 24
Peak memory 201320 kb
Host smart-87ffafee-cf63-462d-ba3e-8c6aaf186199
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353567378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1353567378
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3121555690
Short name T679
Test name
Test status
Simulation time 328511050522 ps
CPU time 201.18 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:28:33 PM PST 24
Peak memory 201488 kb
Host smart-2f52ada5-a240-4ceb-a225-067434f08190
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121555690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3121555690
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3518877138
Short name T489
Test name
Test status
Simulation time 42805901922 ps
CPU time 98 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:26:50 PM PST 24
Peak memory 201192 kb
Host smart-f5c2015b-47f4-4652-9e8a-627416f7c1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518877138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3518877138
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2425895164
Short name T486
Test name
Test status
Simulation time 3540622279 ps
CPU time 8.14 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:25:27 PM PST 24
Peak memory 201216 kb
Host smart-5cac38cd-85ec-43b9-a4e1-603a18fb799e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425895164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2425895164
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.997355549
Short name T757
Test name
Test status
Simulation time 6119891356 ps
CPU time 4.71 seconds
Started Feb 28 04:25:23 PM PST 24
Finished Feb 28 04:25:28 PM PST 24
Peak memory 201036 kb
Host smart-27085ceb-c867-488b-a2f1-6d0611fe39fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997355549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.997355549
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3492783637
Short name T25
Test name
Test status
Simulation time 94394916582 ps
CPU time 160.02 seconds
Started Feb 28 04:25:22 PM PST 24
Finished Feb 28 04:28:02 PM PST 24
Peak memory 210176 kb
Host smart-aeea5b5d-1cd3-4ed9-99b9-1c69c37c6d86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492783637 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3492783637
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4143065243
Short name T695
Test name
Test status
Simulation time 578268869 ps
CPU time 0.76 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:25:19 PM PST 24
Peak memory 201048 kb
Host smart-33d0cc43-976d-4dc1-956b-275e95ab5e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143065243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4143065243
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3981422198
Short name T240
Test name
Test status
Simulation time 481375629489 ps
CPU time 1042.92 seconds
Started Feb 28 04:25:19 PM PST 24
Finished Feb 28 04:42:43 PM PST 24
Peak memory 201356 kb
Host smart-3c984f4f-031b-43d3-953d-80ad690f8786
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981422198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3981422198
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1941377428
Short name T728
Test name
Test status
Simulation time 165513422045 ps
CPU time 365.38 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:31:23 PM PST 24
Peak memory 201376 kb
Host smart-3f609c4b-9854-47c8-969c-8466aa1011d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941377428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1941377428
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1669109817
Short name T620
Test name
Test status
Simulation time 325891933367 ps
CPU time 388.11 seconds
Started Feb 28 04:25:23 PM PST 24
Finished Feb 28 04:31:51 PM PST 24
Peak memory 201324 kb
Host smart-872f9237-b5b0-4891-a4fd-c7b1e93a1bc6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669109817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1669109817
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3182811666
Short name T599
Test name
Test status
Simulation time 326444103344 ps
CPU time 170.08 seconds
Started Feb 28 04:25:15 PM PST 24
Finished Feb 28 04:28:05 PM PST 24
Peak memory 201400 kb
Host smart-bb30adb7-36da-4103-8861-ca12cff6c504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182811666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3182811666
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2492880031
Short name T387
Test name
Test status
Simulation time 501325851122 ps
CPU time 1129.24 seconds
Started Feb 28 04:25:17 PM PST 24
Finished Feb 28 04:44:17 PM PST 24
Peak memory 201392 kb
Host smart-0c3b374c-5366-490f-beab-671e5c4607bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492880031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2492880031
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3544221270
Short name T688
Test name
Test status
Simulation time 490144072376 ps
CPU time 267.57 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:29:49 PM PST 24
Peak memory 201368 kb
Host smart-cf2c42d3-9540-4cdc-9c08-4a13b05cd0af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544221270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3544221270
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4143906948
Short name T635
Test name
Test status
Simulation time 166695076465 ps
CPU time 168.11 seconds
Started Feb 28 04:25:01 PM PST 24
Finished Feb 28 04:27:54 PM PST 24
Peak memory 201464 kb
Host smart-8e3aa8c7-fcf7-4504-92cd-9d4de1da5da4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143906948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4143906948
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2934067710
Short name T545
Test name
Test status
Simulation time 88978122764 ps
CPU time 317.43 seconds
Started Feb 28 04:25:19 PM PST 24
Finished Feb 28 04:30:37 PM PST 24
Peak memory 201624 kb
Host smart-f558e767-2998-4d60-b826-6993618ae3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934067710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2934067710
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2272630993
Short name T604
Test name
Test status
Simulation time 25118031111 ps
CPU time 29.71 seconds
Started Feb 28 04:25:24 PM PST 24
Finished Feb 28 04:25:54 PM PST 24
Peak memory 201112 kb
Host smart-41bccf80-b435-4a4b-a45d-9880212d887a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272630993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2272630993
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1640410240
Short name T395
Test name
Test status
Simulation time 3200766666 ps
CPU time 2.34 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:25:21 PM PST 24
Peak memory 201140 kb
Host smart-cebe94f2-481c-427d-b999-2e318e6ae147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640410240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1640410240
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1989951968
Short name T472
Test name
Test status
Simulation time 5725917274 ps
CPU time 3.91 seconds
Started Feb 28 04:25:10 PM PST 24
Finished Feb 28 04:25:15 PM PST 24
Peak memory 201152 kb
Host smart-327bc110-73d2-4556-adc6-6a0cdc120b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989951968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1989951968
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4135338650
Short name T568
Test name
Test status
Simulation time 75273896389 ps
CPU time 274.92 seconds
Started Feb 28 04:25:22 PM PST 24
Finished Feb 28 04:29:57 PM PST 24
Peak memory 209996 kb
Host smart-0228d765-75ae-40dd-b8bf-bc2f39ad3fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135338650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4135338650
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2564762164
Short name T188
Test name
Test status
Simulation time 75987454702 ps
CPU time 166.33 seconds
Started Feb 28 04:25:03 PM PST 24
Finished Feb 28 04:27:49 PM PST 24
Peak memory 209680 kb
Host smart-763b51c8-73a6-4279-ab98-0827a9b8681c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564762164 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2564762164
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2370699212
Short name T372
Test name
Test status
Simulation time 427730989 ps
CPU time 1.5 seconds
Started Feb 28 04:25:17 PM PST 24
Finished Feb 28 04:25:19 PM PST 24
Peak memory 201036 kb
Host smart-0bb8dff5-2af3-45d7-8f6c-023aba16455e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370699212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2370699212
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1361891708
Short name T778
Test name
Test status
Simulation time 322620154461 ps
CPU time 782.59 seconds
Started Feb 28 04:25:15 PM PST 24
Finished Feb 28 04:38:17 PM PST 24
Peak memory 201276 kb
Host smart-d409d08e-7626-4aa7-8305-79fa0d44647d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361891708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1361891708
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4132913622
Short name T656
Test name
Test status
Simulation time 174996040744 ps
CPU time 378.46 seconds
Started Feb 28 04:25:28 PM PST 24
Finished Feb 28 04:31:47 PM PST 24
Peak memory 201416 kb
Host smart-24c18fc5-2c27-4687-8537-a299ed36cfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132913622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4132913622
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2961389713
Short name T482
Test name
Test status
Simulation time 166646457109 ps
CPU time 383.56 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:31:37 PM PST 24
Peak memory 201472 kb
Host smart-01e9e915-8ac8-4cb4-8583-bde847a4949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961389713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2961389713
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.364611302
Short name T108
Test name
Test status
Simulation time 336639734503 ps
CPU time 66.02 seconds
Started Feb 28 04:25:19 PM PST 24
Finished Feb 28 04:26:25 PM PST 24
Peak memory 201360 kb
Host smart-221a8d89-44aa-42d3-b92c-bd87c12a53fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=364611302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.364611302
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2680930136
Short name T704
Test name
Test status
Simulation time 489197208229 ps
CPU time 267.56 seconds
Started Feb 28 04:25:24 PM PST 24
Finished Feb 28 04:29:52 PM PST 24
Peak memory 201312 kb
Host smart-a0c09f38-6a9c-4012-8244-ff3d10fb8ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680930136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2680930136
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3995818120
Short name T345
Test name
Test status
Simulation time 324819068937 ps
CPU time 751.56 seconds
Started Feb 28 04:25:16 PM PST 24
Finished Feb 28 04:37:48 PM PST 24
Peak memory 201304 kb
Host smart-e11dae7b-3d3d-44f8-9a0c-66395890223a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995818120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3995818120
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.359539942
Short name T734
Test name
Test status
Simulation time 495616829756 ps
CPU time 1045.89 seconds
Started Feb 28 04:25:34 PM PST 24
Finished Feb 28 04:43:00 PM PST 24
Peak memory 201396 kb
Host smart-a8ff124e-dad6-480c-8719-25a20458c37f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359539942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.359539942
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2405632889
Short name T524
Test name
Test status
Simulation time 63700765090 ps
CPU time 218.51 seconds
Started Feb 28 04:24:58 PM PST 24
Finished Feb 28 04:28:39 PM PST 24
Peak memory 201724 kb
Host smart-cac4c5b2-7970-4e77-bbf4-36b24445949b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405632889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2405632889
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3848823485
Short name T389
Test name
Test status
Simulation time 31927612197 ps
CPU time 20.19 seconds
Started Feb 28 04:25:11 PM PST 24
Finished Feb 28 04:25:32 PM PST 24
Peak memory 201188 kb
Host smart-dd2cb3de-5958-4fc8-b396-c077d6132361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848823485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3848823485
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3680376234
Short name T386
Test name
Test status
Simulation time 2859471087 ps
CPU time 2.43 seconds
Started Feb 28 04:25:16 PM PST 24
Finished Feb 28 04:25:19 PM PST 24
Peak memory 201160 kb
Host smart-492c9f19-1c78-49f4-9a96-080836f5285e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680376234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3680376234
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3925369597
Short name T643
Test name
Test status
Simulation time 6103348960 ps
CPU time 4.17 seconds
Started Feb 28 04:25:08 PM PST 24
Finished Feb 28 04:25:13 PM PST 24
Peak memory 201104 kb
Host smart-594f3fed-6534-48d8-acce-197a9a842f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925369597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3925369597
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3842892928
Short name T61
Test name
Test status
Simulation time 72243157953 ps
CPU time 167.1 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:28:00 PM PST 24
Peak memory 210028 kb
Host smart-18bd5e16-0ec5-453d-83db-41ccacdf0333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842892928 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3842892928
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.890071021
Short name T737
Test name
Test status
Simulation time 443155486 ps
CPU time 0.86 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:24:46 PM PST 24
Peak memory 201140 kb
Host smart-0317ff62-796d-4088-acec-c6cdefaa4eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890071021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.890071021
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2492575601
Short name T780
Test name
Test status
Simulation time 530857793816 ps
CPU time 296.88 seconds
Started Feb 28 04:24:49 PM PST 24
Finished Feb 28 04:29:46 PM PST 24
Peak memory 201440 kb
Host smart-5635a3a1-f69c-4fdb-85cf-871f42c27d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492575601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2492575601
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.345144415
Short name T204
Test name
Test status
Simulation time 492357927269 ps
CPU time 944.92 seconds
Started Feb 28 04:24:34 PM PST 24
Finished Feb 28 04:40:19 PM PST 24
Peak memory 201384 kb
Host smart-f683ecea-70f5-48c8-af20-9121486e5ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345144415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.345144415
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.695603404
Short name T478
Test name
Test status
Simulation time 164531523095 ps
CPU time 365.06 seconds
Started Feb 28 04:24:33 PM PST 24
Finished Feb 28 04:30:38 PM PST 24
Peak memory 201428 kb
Host smart-a339002f-59ae-4bc6-a6c4-520fd8b8335e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=695603404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.695603404
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1601797256
Short name T589
Test name
Test status
Simulation time 159480053695 ps
CPU time 78.22 seconds
Started Feb 28 04:24:33 PM PST 24
Finished Feb 28 04:25:52 PM PST 24
Peak memory 201380 kb
Host smart-25d3d6a6-d9d9-48e7-acb0-6b5b61a2e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601797256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1601797256
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2329208228
Short name T367
Test name
Test status
Simulation time 493237623525 ps
CPU time 852.6 seconds
Started Feb 28 04:24:50 PM PST 24
Finished Feb 28 04:39:03 PM PST 24
Peak memory 201348 kb
Host smart-77aa277e-47cc-4811-8fa3-49b9c62b22e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329208228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2329208228
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1694718388
Short name T242
Test name
Test status
Simulation time 484755330387 ps
CPU time 974.45 seconds
Started Feb 28 04:24:28 PM PST 24
Finished Feb 28 04:40:42 PM PST 24
Peak memory 201368 kb
Host smart-dbb0f026-e85d-4567-a911-8f8fe0d9b188
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694718388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1694718388
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1855024315
Short name T578
Test name
Test status
Simulation time 487507879049 ps
CPU time 506 seconds
Started Feb 28 04:24:34 PM PST 24
Finished Feb 28 04:33:01 PM PST 24
Peak memory 201452 kb
Host smart-2571c246-20be-4cdc-8903-aa6016968547
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855024315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1855024315
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1839572737
Short name T549
Test name
Test status
Simulation time 106884043956 ps
CPU time 386.39 seconds
Started Feb 28 04:24:30 PM PST 24
Finished Feb 28 04:30:56 PM PST 24
Peak memory 201604 kb
Host smart-5e65c7e0-c363-4aff-9153-a6eb5d14c953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839572737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1839572737
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.439591113
Short name T420
Test name
Test status
Simulation time 32947870279 ps
CPU time 41.27 seconds
Started Feb 28 04:24:48 PM PST 24
Finished Feb 28 04:25:30 PM PST 24
Peak memory 201264 kb
Host smart-57ad0a4f-659c-4b10-be98-7fce29fd90ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439591113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.439591113
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1800560941
Short name T479
Test name
Test status
Simulation time 5156795540 ps
CPU time 3.85 seconds
Started Feb 28 04:24:47 PM PST 24
Finished Feb 28 04:24:52 PM PST 24
Peak memory 201044 kb
Host smart-994a36f2-6e7f-4631-bbd3-31a7822dd809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800560941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1800560941
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2833960556
Short name T49
Test name
Test status
Simulation time 4487222788 ps
CPU time 5.9 seconds
Started Feb 28 04:25:04 PM PST 24
Finished Feb 28 04:25:10 PM PST 24
Peak memory 216240 kb
Host smart-37d22bfe-796a-4830-9a92-443b9391d3ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833960556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2833960556
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3931088878
Short name T767
Test name
Test status
Simulation time 5746283493 ps
CPU time 14.96 seconds
Started Feb 28 04:24:44 PM PST 24
Finished Feb 28 04:25:00 PM PST 24
Peak memory 201116 kb
Host smart-7f2f2946-575d-4f6f-b16e-0ba71bdcb140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931088878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3931088878
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1757696170
Short name T383
Test name
Test status
Simulation time 358737465 ps
CPU time 1.15 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:25:19 PM PST 24
Peak memory 201092 kb
Host smart-7d3fabe0-1157-4f16-b975-776eadb5169a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757696170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1757696170
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1891157070
Short name T249
Test name
Test status
Simulation time 161504094761 ps
CPU time 47.29 seconds
Started Feb 28 04:25:19 PM PST 24
Finished Feb 28 04:26:06 PM PST 24
Peak memory 201392 kb
Host smart-47d12e5b-23a5-42da-8b48-88c7ae6ec6e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891157070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1891157070
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2403325322
Short name T111
Test name
Test status
Simulation time 334089926027 ps
CPU time 120.42 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:27:13 PM PST 24
Peak memory 201324 kb
Host smart-935393d1-5447-4404-8a61-d63910193bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403325322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2403325322
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.201213355
Short name T235
Test name
Test status
Simulation time 500233157386 ps
CPU time 522.35 seconds
Started Feb 28 04:25:31 PM PST 24
Finished Feb 28 04:34:13 PM PST 24
Peak memory 201284 kb
Host smart-991163e1-8ee1-4b81-ae2a-e1b5dab4dc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201213355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.201213355
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.697371595
Short name T344
Test name
Test status
Simulation time 495532202364 ps
CPU time 1158.81 seconds
Started Feb 28 04:25:07 PM PST 24
Finished Feb 28 04:44:27 PM PST 24
Peak memory 201344 kb
Host smart-ebd56b02-b36a-4dd2-a46a-cc65c3f2eb65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=697371595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.697371595
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2110008928
Short name T230
Test name
Test status
Simulation time 489637092302 ps
CPU time 943.74 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:40:56 PM PST 24
Peak memory 201300 kb
Host smart-2f41a861-cf5e-4493-8333-217e2485f921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110008928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2110008928
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1871770542
Short name T343
Test name
Test status
Simulation time 499373840176 ps
CPU time 295.93 seconds
Started Feb 28 04:25:23 PM PST 24
Finished Feb 28 04:30:19 PM PST 24
Peak memory 201368 kb
Host smart-cf2d69d1-00fd-4039-ba0b-8dd1cffeb1e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871770542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1871770542
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2944405302
Short name T654
Test name
Test status
Simulation time 329902827485 ps
CPU time 708.07 seconds
Started Feb 28 04:25:40 PM PST 24
Finished Feb 28 04:37:28 PM PST 24
Peak memory 201436 kb
Host smart-8d06830b-e0fe-465b-ad10-95b5b817d10b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944405302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2944405302
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1375539768
Short name T442
Test name
Test status
Simulation time 487656413393 ps
CPU time 275.93 seconds
Started Feb 28 04:25:25 PM PST 24
Finished Feb 28 04:30:01 PM PST 24
Peak memory 201316 kb
Host smart-e0b1fd54-123b-4ab4-97c9-9dffa22421e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375539768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1375539768
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.58691136
Short name T488
Test name
Test status
Simulation time 65964845988 ps
CPU time 283.98 seconds
Started Feb 28 04:25:15 PM PST 24
Finished Feb 28 04:29:59 PM PST 24
Peak memory 201752 kb
Host smart-765bf055-7ab5-49a6-93c0-2ca0dcbd3902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58691136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.58691136
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1239999097
Short name T68
Test name
Test status
Simulation time 33841608850 ps
CPU time 75.99 seconds
Started Feb 28 04:25:19 PM PST 24
Finished Feb 28 04:26:36 PM PST 24
Peak memory 201188 kb
Host smart-5feb8434-1cc6-474d-ad98-a9fdaaf04f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239999097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1239999097
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.517064746
Short name T570
Test name
Test status
Simulation time 2942248628 ps
CPU time 4.21 seconds
Started Feb 28 04:25:26 PM PST 24
Finished Feb 28 04:25:31 PM PST 24
Peak memory 201200 kb
Host smart-75f7fe9b-848c-47eb-ba2d-3f1b7c15b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517064746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.517064746
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2220606344
Short name T460
Test name
Test status
Simulation time 5781685270 ps
CPU time 14.25 seconds
Started Feb 28 04:25:07 PM PST 24
Finished Feb 28 04:25:21 PM PST 24
Peak memory 201200 kb
Host smart-f5a91b6c-da02-4fe3-a7b9-d403f45d6c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220606344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2220606344
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3827101157
Short name T155
Test name
Test status
Simulation time 97889022116 ps
CPU time 233.65 seconds
Started Feb 28 04:25:17 PM PST 24
Finished Feb 28 04:29:11 PM PST 24
Peak memory 218056 kb
Host smart-4018bf5a-06ee-48a3-a552-95d198d70120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827101157 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3827101157
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.735257853
Short name T756
Test name
Test status
Simulation time 322310233 ps
CPU time 0.96 seconds
Started Feb 28 04:25:35 PM PST 24
Finished Feb 28 04:25:36 PM PST 24
Peak memory 201196 kb
Host smart-5bbcd4f8-9e44-4651-b3ce-3c3955449e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735257853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.735257853
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3652344516
Short name T207
Test name
Test status
Simulation time 203755059595 ps
CPU time 39.22 seconds
Started Feb 28 04:25:14 PM PST 24
Finished Feb 28 04:25:54 PM PST 24
Peak memory 201380 kb
Host smart-2c5ecc65-23a4-4a50-bc3a-ae5cf5eec624
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652344516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3652344516
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1995618094
Short name T276
Test name
Test status
Simulation time 328202246153 ps
CPU time 227.83 seconds
Started Feb 28 04:25:17 PM PST 24
Finished Feb 28 04:29:05 PM PST 24
Peak memory 201456 kb
Host smart-0faa6f3e-61a3-4bb2-86f2-e78ddb63f462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995618094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1995618094
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3585274838
Short name T137
Test name
Test status
Simulation time 491663666060 ps
CPU time 286.04 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:30:04 PM PST 24
Peak memory 201428 kb
Host smart-6a913aaa-791e-4c4f-8a2f-9cb0ab3b8e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585274838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3585274838
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2958752529
Short name T439
Test name
Test status
Simulation time 492533745908 ps
CPU time 295.4 seconds
Started Feb 28 04:25:29 PM PST 24
Finished Feb 28 04:30:25 PM PST 24
Peak memory 201476 kb
Host smart-cdd425c2-2513-4ccf-9add-c083514d0ecc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958752529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2958752529
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.4188317366
Short name T239
Test name
Test status
Simulation time 329292378817 ps
CPU time 169.76 seconds
Started Feb 28 04:25:18 PM PST 24
Finished Feb 28 04:28:08 PM PST 24
Peak memory 201320 kb
Host smart-23d36e6f-a672-40e4-8fe9-e16a587bd546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188317366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4188317366
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.17888868
Short name T559
Test name
Test status
Simulation time 162788576887 ps
CPU time 394.96 seconds
Started Feb 28 04:25:30 PM PST 24
Finished Feb 28 04:32:05 PM PST 24
Peak memory 201288 kb
Host smart-afc45a46-401d-4f24-8f32-1b4ab41d8c6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=17888868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed
.17888868
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2955787273
Short name T145
Test name
Test status
Simulation time 326931159666 ps
CPU time 804.5 seconds
Started Feb 28 04:25:29 PM PST 24
Finished Feb 28 04:38:53 PM PST 24
Peak memory 201416 kb
Host smart-7c420b37-b0f9-412c-ac89-01423a3946b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955787273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2955787273
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.167427928
Short name T697
Test name
Test status
Simulation time 168551612802 ps
CPU time 92.09 seconds
Started Feb 28 04:25:15 PM PST 24
Finished Feb 28 04:26:47 PM PST 24
Peak memory 201280 kb
Host smart-54ded658-fef1-4e0d-b865-53d569504428
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167427928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.167427928
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1612752955
Short name T632
Test name
Test status
Simulation time 23535089646 ps
CPU time 11.6 seconds
Started Feb 28 04:25:32 PM PST 24
Finished Feb 28 04:25:43 PM PST 24
Peak memory 201200 kb
Host smart-f246bba1-2e5b-4778-8d38-ce25fe56e50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612752955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1612752955
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1648287623
Short name T774
Test name
Test status
Simulation time 3093662273 ps
CPU time 2.27 seconds
Started Feb 28 04:25:22 PM PST 24
Finished Feb 28 04:25:24 PM PST 24
Peak memory 201196 kb
Host smart-8f026c45-f966-4081-b080-6500e88c6fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648287623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1648287623
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.42043731
Short name T384
Test name
Test status
Simulation time 5645378507 ps
CPU time 12.78 seconds
Started Feb 28 04:25:20 PM PST 24
Finished Feb 28 04:25:34 PM PST 24
Peak memory 201184 kb
Host smart-8f6a5bac-1445-4df8-ac05-abd5fb04ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42043731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.42043731
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3961566886
Short name T198
Test name
Test status
Simulation time 526349107271 ps
CPU time 637.55 seconds
Started Feb 28 04:25:33 PM PST 24
Finished Feb 28 04:36:11 PM PST 24
Peak memory 201388 kb
Host smart-1000368c-172c-4c67-b1af-10644525bca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961566886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3961566886
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2626870172
Short name T189
Test name
Test status
Simulation time 63042075654 ps
CPU time 136.19 seconds
Started Feb 28 04:25:28 PM PST 24
Finished Feb 28 04:27:44 PM PST 24
Peak memory 210052 kb
Host smart-63295f47-8241-4d1e-a994-18e09081b686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626870172 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2626870172
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1907242664
Short name T42
Test name
Test status
Simulation time 459201814 ps
CPU time 1.65 seconds
Started Feb 28 04:25:32 PM PST 24
Finished Feb 28 04:25:34 PM PST 24
Peak memory 201136 kb
Host smart-cf2af502-5e8e-47de-a8cd-e305220153ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907242664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1907242664
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2921362732
Short name T248
Test name
Test status
Simulation time 166169446980 ps
CPU time 315.93 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:30:37 PM PST 24
Peak memory 201444 kb
Host smart-d15ae81a-0afe-4bbd-a9f1-6cff033b4c6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921362732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2921362732
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1193584817
Short name T696
Test name
Test status
Simulation time 164709595103 ps
CPU time 203.64 seconds
Started Feb 28 04:25:31 PM PST 24
Finished Feb 28 04:28:55 PM PST 24
Peak memory 201460 kb
Host smart-51902566-6657-40a4-82ed-27d3a03f05c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193584817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1193584817
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.442781557
Short name T755
Test name
Test status
Simulation time 498437759270 ps
CPU time 296.05 seconds
Started Feb 28 04:25:17 PM PST 24
Finished Feb 28 04:30:13 PM PST 24
Peak memory 201452 kb
Host smart-7f5893bd-1e08-4d9a-9a24-6bc4cde07971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442781557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.442781557
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3791999388
Short name T629
Test name
Test status
Simulation time 487060218899 ps
CPU time 151.28 seconds
Started Feb 28 04:25:27 PM PST 24
Finished Feb 28 04:27:59 PM PST 24
Peak memory 201392 kb
Host smart-efc455a9-3207-4072-8866-d590a96b600f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791999388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3791999388
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.53824162
Short name T59
Test name
Test status
Simulation time 168724902145 ps
CPU time 355.05 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:31:07 PM PST 24
Peak memory 201412 kb
Host smart-778607c2-1a00-49d8-9a93-5838593156bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53824162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.53824162
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.881934283
Short name T558
Test name
Test status
Simulation time 334523520592 ps
CPU time 183.76 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:28:25 PM PST 24
Peak memory 201464 kb
Host smart-1219ec4e-eb9c-4922-8a47-b50faaa841bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=881934283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.881934283
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2174587048
Short name T223
Test name
Test status
Simulation time 490598970658 ps
CPU time 539.69 seconds
Started Feb 28 04:25:09 PM PST 24
Finished Feb 28 04:34:09 PM PST 24
Peak memory 201460 kb
Host smart-905fd058-3dc1-473b-9d8d-b71fb46dfd70
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174587048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2174587048
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.749100560
Short name T428
Test name
Test status
Simulation time 332288966831 ps
CPU time 734.27 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:37:35 PM PST 24
Peak memory 201316 kb
Host smart-72fdd6f2-ab9d-4826-81fc-e90917cd8563
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749100560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.749100560
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2311650811
Short name T468
Test name
Test status
Simulation time 109183263744 ps
CPU time 354.62 seconds
Started Feb 28 04:25:39 PM PST 24
Finished Feb 28 04:31:34 PM PST 24
Peak memory 201696 kb
Host smart-d44aad73-5cbb-42fd-bbe1-99236bbae1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311650811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2311650811
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.707322139
Short name T657
Test name
Test status
Simulation time 33686473135 ps
CPU time 21.37 seconds
Started Feb 28 04:25:25 PM PST 24
Finished Feb 28 04:25:46 PM PST 24
Peak memory 201200 kb
Host smart-f265eb56-3028-4a8e-a02a-e0cbde3888f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707322139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.707322139
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2215171542
Short name T347
Test name
Test status
Simulation time 4239311790 ps
CPU time 10.79 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:25:47 PM PST 24
Peak memory 201200 kb
Host smart-3c685254-3ac6-48f7-8821-9b784796f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215171542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2215171542
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.455809296
Short name T402
Test name
Test status
Simulation time 5801197959 ps
CPU time 4.72 seconds
Started Feb 28 04:25:21 PM PST 24
Finished Feb 28 04:25:27 PM PST 24
Peak memory 201284 kb
Host smart-4050926d-0b7f-47c2-9fb6-8d40f3a74eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455809296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.455809296
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.891289439
Short name T2
Test name
Test status
Simulation time 116435369856 ps
CPU time 559.09 seconds
Started Feb 28 04:25:35 PM PST 24
Finished Feb 28 04:34:54 PM PST 24
Peak memory 209796 kb
Host smart-4799a534-ac2c-47b1-981b-4012861bd6d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891289439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
891289439
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.488731183
Short name T60
Test name
Test status
Simulation time 302547822382 ps
CPU time 68.03 seconds
Started Feb 28 04:25:35 PM PST 24
Finished Feb 28 04:26:43 PM PST 24
Peak memory 209588 kb
Host smart-6ad3f01c-7716-4793-afb6-3cca634764db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488731183 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.488731183
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3532506254
Short name T362
Test name
Test status
Simulation time 311560409 ps
CPU time 1.3 seconds
Started Feb 28 04:25:48 PM PST 24
Finished Feb 28 04:25:49 PM PST 24
Peak memory 201132 kb
Host smart-491e8bc9-f843-45bf-8b25-26a01cf8c49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532506254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3532506254
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.621210439
Short name T751
Test name
Test status
Simulation time 323970815180 ps
CPU time 732.32 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:37:54 PM PST 24
Peak memory 201444 kb
Host smart-043b7231-d585-4d10-9c12-77ce8cc86272
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621210439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.621210439
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3945489192
Short name T273
Test name
Test status
Simulation time 157622682114 ps
CPU time 178.6 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:28:43 PM PST 24
Peak memory 201376 kb
Host smart-f215cba0-6bb5-436e-b352-d8115df520f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945489192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3945489192
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3705322834
Short name T317
Test name
Test status
Simulation time 336273251247 ps
CPU time 375.61 seconds
Started Feb 28 04:25:45 PM PST 24
Finished Feb 28 04:32:01 PM PST 24
Peak memory 201388 kb
Host smart-293b49b7-768a-4409-9eaa-5307ffe1c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705322834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3705322834
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1446209509
Short name T378
Test name
Test status
Simulation time 492845729223 ps
CPU time 543.77 seconds
Started Feb 28 04:25:46 PM PST 24
Finished Feb 28 04:34:50 PM PST 24
Peak memory 201472 kb
Host smart-462de263-5a61-44fc-ac3b-72f8212a40d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446209509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1446209509
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3716839276
Short name T534
Test name
Test status
Simulation time 493874425217 ps
CPU time 1128.56 seconds
Started Feb 28 04:25:49 PM PST 24
Finished Feb 28 04:44:38 PM PST 24
Peak memory 201372 kb
Host smart-67d5fe3c-f838-4121-bdb9-709bb0172157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716839276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3716839276
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.64120218
Short name T649
Test name
Test status
Simulation time 170049005470 ps
CPU time 31.61 seconds
Started Feb 28 04:25:30 PM PST 24
Finished Feb 28 04:26:01 PM PST 24
Peak memory 201460 kb
Host smart-4ec0baa2-3549-4c12-a6b3-b3786e974598
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=64120218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed
.64120218
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1462720776
Short name T143
Test name
Test status
Simulation time 324427099017 ps
CPU time 783.73 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:38:46 PM PST 24
Peak memory 201528 kb
Host smart-39d68e1d-d717-429d-843e-d843454a64e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462720776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1462720776
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2725320652
Short name T574
Test name
Test status
Simulation time 329224426406 ps
CPU time 53.5 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:26:34 PM PST 24
Peak memory 201312 kb
Host smart-d82ccae2-1926-436e-bffc-528ffff3948a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725320652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2725320652
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.564845609
Short name T181
Test name
Test status
Simulation time 116876211888 ps
CPU time 460.88 seconds
Started Feb 28 04:25:27 PM PST 24
Finished Feb 28 04:33:08 PM PST 24
Peak memory 201692 kb
Host smart-591f7e84-8633-45ba-b558-6475bf23b541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564845609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.564845609
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2164686745
Short name T782
Test name
Test status
Simulation time 32058142777 ps
CPU time 76.88 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:26:58 PM PST 24
Peak memory 201132 kb
Host smart-7c2ff92c-2705-4b70-92ff-991cc0c1a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164686745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2164686745
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3042084727
Short name T610
Test name
Test status
Simulation time 5179446382 ps
CPU time 14.46 seconds
Started Feb 28 04:25:39 PM PST 24
Finished Feb 28 04:25:54 PM PST 24
Peak memory 201248 kb
Host smart-bad392af-c01f-4fbe-a2be-bcbdfe16c596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042084727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3042084727
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4170937821
Short name T502
Test name
Test status
Simulation time 5791581848 ps
CPU time 4.27 seconds
Started Feb 28 04:25:35 PM PST 24
Finished Feb 28 04:25:40 PM PST 24
Peak memory 201152 kb
Host smart-64a30b7a-fccc-4f48-89da-00e356e856c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170937821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4170937821
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.378517818
Short name T306
Test name
Test status
Simulation time 188963065959 ps
CPU time 455.62 seconds
Started Feb 28 04:25:34 PM PST 24
Finished Feb 28 04:33:10 PM PST 24
Peak memory 201364 kb
Host smart-1e5c2134-01d2-4ff5-afb7-b651f7183848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378517818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
378517818
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.912946210
Short name T307
Test name
Test status
Simulation time 33425870980 ps
CPU time 77.91 seconds
Started Feb 28 04:25:48 PM PST 24
Finished Feb 28 04:27:06 PM PST 24
Peak memory 201580 kb
Host smart-94fee50a-9a77-499f-9fa6-87bad45a705e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912946210 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.912946210
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.398935696
Short name T519
Test name
Test status
Simulation time 556587239 ps
CPU time 0.98 seconds
Started Feb 28 04:25:34 PM PST 24
Finished Feb 28 04:25:35 PM PST 24
Peak memory 201148 kb
Host smart-8b198dee-ce25-4f7f-ba61-a2febc27b7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398935696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.398935696
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2770434357
Short name T675
Test name
Test status
Simulation time 494129508617 ps
CPU time 303.1 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:30:42 PM PST 24
Peak memory 201380 kb
Host smart-edb07551-d2f9-4cd6-be7f-f3733b48f32e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770434357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2770434357
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4052721301
Short name T731
Test name
Test status
Simulation time 162862872230 ps
CPU time 94.34 seconds
Started Feb 28 04:25:45 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 201328 kb
Host smart-4782c5e9-f52a-4ec7-a136-fa3a215ee082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052721301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4052721301
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1099045133
Short name T475
Test name
Test status
Simulation time 165416066224 ps
CPU time 51.01 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:26:28 PM PST 24
Peak memory 201388 kb
Host smart-382510e6-f99e-40dd-a559-0fcc704507c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099045133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1099045133
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.511666815
Short name T135
Test name
Test status
Simulation time 488043659765 ps
CPU time 138.41 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:27:59 PM PST 24
Peak memory 201408 kb
Host smart-0e50e14e-1a99-4b6c-9df2-f9bad3b3c029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511666815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.511666815
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.865871957
Short name T683
Test name
Test status
Simulation time 159026178621 ps
CPU time 89.62 seconds
Started Feb 28 04:25:50 PM PST 24
Finished Feb 28 04:27:20 PM PST 24
Peak memory 201396 kb
Host smart-fd0f76a2-3ab0-4aa2-bf36-a6cd29460436
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=865871957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.865871957
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1017734617
Short name T113
Test name
Test status
Simulation time 500296930042 ps
CPU time 364.54 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:31:48 PM PST 24
Peak memory 201460 kb
Host smart-44690aaa-41c9-4920-82d1-1de3f35f6dd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017734617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1017734617
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.870762543
Short name T764
Test name
Test status
Simulation time 500140905086 ps
CPU time 287.56 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:30:30 PM PST 24
Peak memory 201372 kb
Host smart-29c620e5-e4dc-4d81-a7ba-324ec715e4fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870762543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.870762543
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1498988869
Short name T562
Test name
Test status
Simulation time 86364347714 ps
CPU time 302.4 seconds
Started Feb 28 04:25:39 PM PST 24
Finished Feb 28 04:30:41 PM PST 24
Peak memory 201780 kb
Host smart-017107eb-43ef-4549-aab7-44a0c0870bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498988869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1498988869
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1692889732
Short name T351
Test name
Test status
Simulation time 44941880195 ps
CPU time 13.4 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:25:52 PM PST 24
Peak memory 201148 kb
Host smart-6fa8d049-ebc8-46a6-b62c-3fd2b7010cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692889732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1692889732
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1439166600
Short name T480
Test name
Test status
Simulation time 4358392525 ps
CPU time 3.42 seconds
Started Feb 28 04:25:46 PM PST 24
Finished Feb 28 04:25:49 PM PST 24
Peak memory 201160 kb
Host smart-72232407-59af-4494-8f78-c1915f770c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439166600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1439166600
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2703666182
Short name T520
Test name
Test status
Simulation time 5752710051 ps
CPU time 6.31 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:25:48 PM PST 24
Peak memory 201196 kb
Host smart-db757659-40dd-4a33-bba2-25d9d9ad2d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703666182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2703666182
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.896858799
Short name T565
Test name
Test status
Simulation time 167124709827 ps
CPU time 91.84 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 201520 kb
Host smart-9ce2c08c-76b0-4669-b8d8-b95922f0f7d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896858799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
896858799
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1011264461
Short name T433
Test name
Test status
Simulation time 315871317 ps
CPU time 1.38 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:25:44 PM PST 24
Peak memory 201116 kb
Host smart-9f2fa090-e4c5-467f-8af8-f28bd159cfc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011264461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1011264461
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1257690427
Short name T646
Test name
Test status
Simulation time 347100836461 ps
CPU time 775.71 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:38:33 PM PST 24
Peak memory 201448 kb
Host smart-3fe0a022-5970-4be2-8da0-ee13d4585fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257690427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1257690427
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.967046048
Short name T714
Test name
Test status
Simulation time 164303922753 ps
CPU time 27.71 seconds
Started Feb 28 04:25:31 PM PST 24
Finished Feb 28 04:25:58 PM PST 24
Peak memory 201316 kb
Host smart-ef0146f3-236d-4f47-a708-02128ea052df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967046048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.967046048
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3832200847
Short name T621
Test name
Test status
Simulation time 333964196417 ps
CPU time 743.97 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:38:02 PM PST 24
Peak memory 201380 kb
Host smart-fb96a686-1a0b-4245-b312-6608a5d42ed6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832200847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3832200847
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.317372076
Short name T670
Test name
Test status
Simulation time 501740117072 ps
CPU time 587.49 seconds
Started Feb 28 04:25:45 PM PST 24
Finished Feb 28 04:35:33 PM PST 24
Peak memory 201336 kb
Host smart-e728ea67-4c72-42c4-a3ef-c2a6472b8088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317372076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.317372076
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2866085380
Short name T406
Test name
Test status
Simulation time 166911948509 ps
CPU time 107.52 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:27:25 PM PST 24
Peak memory 201448 kb
Host smart-ac69e166-b0a2-4566-8c80-08a153700dbb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866085380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2866085380
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.251854752
Short name T326
Test name
Test status
Simulation time 162682091026 ps
CPU time 358.99 seconds
Started Feb 28 04:25:28 PM PST 24
Finished Feb 28 04:31:28 PM PST 24
Peak memory 201352 kb
Host smart-2c1adf24-912f-43d6-8b89-4e7a05b283c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251854752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.251854752
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3915124351
Short name T628
Test name
Test status
Simulation time 492413956736 ps
CPU time 304.28 seconds
Started Feb 28 04:25:23 PM PST 24
Finished Feb 28 04:30:28 PM PST 24
Peak memory 201488 kb
Host smart-f02dc0eb-1c72-4e85-9456-3cfb7f216c0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915124351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3915124351
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2480806380
Short name T498
Test name
Test status
Simulation time 122987201733 ps
CPU time 680.67 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:36:58 PM PST 24
Peak memory 201652 kb
Host smart-b825b7c6-73df-41ff-85be-9633dd6536c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480806380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2480806380
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1737647744
Short name T10
Test name
Test status
Simulation time 31052702942 ps
CPU time 36.09 seconds
Started Feb 28 04:25:50 PM PST 24
Finished Feb 28 04:26:26 PM PST 24
Peak memory 201028 kb
Host smart-a16fc88c-b5ad-4540-83ff-f4b3372dffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737647744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1737647744
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3590546319
Short name T101
Test name
Test status
Simulation time 3173983483 ps
CPU time 3.64 seconds
Started Feb 28 04:25:36 PM PST 24
Finished Feb 28 04:25:40 PM PST 24
Peak memory 201196 kb
Host smart-021adf3c-2e48-44b5-8bf0-70c220b283d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590546319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3590546319
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.706774254
Short name T786
Test name
Test status
Simulation time 5714100214 ps
CPU time 13.65 seconds
Started Feb 28 04:25:36 PM PST 24
Finished Feb 28 04:25:50 PM PST 24
Peak memory 201144 kb
Host smart-6705a5aa-530e-4739-89c3-57693976c241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706774254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.706774254
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.4018274710
Short name T322
Test name
Test status
Simulation time 166030688612 ps
CPU time 202.86 seconds
Started Feb 28 04:25:35 PM PST 24
Finished Feb 28 04:28:58 PM PST 24
Peak memory 201524 kb
Host smart-232f16e0-3290-4fdc-8dd0-6d1d80b4a5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018274710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.4018274710
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.261083000
Short name T662
Test name
Test status
Simulation time 204404051367 ps
CPU time 229.6 seconds
Started Feb 28 04:25:26 PM PST 24
Finished Feb 28 04:29:15 PM PST 24
Peak memory 210032 kb
Host smart-292ee807-0244-40c4-a048-9ea772407756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261083000 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.261083000
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1731374581
Short name T611
Test name
Test status
Simulation time 400418731 ps
CPU time 1.54 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:25:38 PM PST 24
Peak memory 201148 kb
Host smart-5ea1bc3d-8406-4e93-a337-83a1afe35a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731374581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1731374581
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3137613368
Short name T243
Test name
Test status
Simulation time 166453853415 ps
CPU time 381.88 seconds
Started Feb 28 04:25:59 PM PST 24
Finished Feb 28 04:32:22 PM PST 24
Peak memory 201340 kb
Host smart-19085810-12b9-4c02-958e-cd80fefc0c79
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137613368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3137613368
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3126871290
Short name T246
Test name
Test status
Simulation time 534539526619 ps
CPU time 298.82 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:30:40 PM PST 24
Peak memory 201432 kb
Host smart-55df105e-a00f-4092-ab53-daf275e89502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126871290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3126871290
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2089213058
Short name T701
Test name
Test status
Simulation time 160863698251 ps
CPU time 144.09 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:28:06 PM PST 24
Peak memory 201368 kb
Host smart-b87505cf-c3a3-4c45-b182-a810109164ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089213058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2089213058
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3835260735
Short name T134
Test name
Test status
Simulation time 496373064060 ps
CPU time 64.28 seconds
Started Feb 28 04:25:48 PM PST 24
Finished Feb 28 04:26:53 PM PST 24
Peak memory 201384 kb
Host smart-b0b94704-cfe6-42b5-ac15-61e6d6669cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835260735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3835260735
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1180066873
Short name T8
Test name
Test status
Simulation time 159662479060 ps
CPU time 198.87 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:29:00 PM PST 24
Peak memory 201392 kb
Host smart-15425706-b3bd-400d-b940-96a41d6f217a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180066873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1180066873
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2026729872
Short name T266
Test name
Test status
Simulation time 504265568107 ps
CPU time 307.04 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:30:50 PM PST 24
Peak memory 201400 kb
Host smart-5f567c32-883a-46a7-8d1d-48761ee174f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026729872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2026729872
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2548042815
Short name T713
Test name
Test status
Simulation time 496937223092 ps
CPU time 258.45 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:29:57 PM PST 24
Peak memory 201392 kb
Host smart-346c46f6-c630-4ae5-abe5-318330fad2a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548042815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2548042815
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3301008908
Short name T170
Test name
Test status
Simulation time 87315205095 ps
CPU time 362.34 seconds
Started Feb 28 04:25:46 PM PST 24
Finished Feb 28 04:31:48 PM PST 24
Peak memory 201604 kb
Host smart-9d77a11d-1f53-4710-b75e-39242a313c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301008908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3301008908
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2578563992
Short name T566
Test name
Test status
Simulation time 34791908625 ps
CPU time 75.43 seconds
Started Feb 28 04:25:36 PM PST 24
Finished Feb 28 04:26:52 PM PST 24
Peak memory 201200 kb
Host smart-d82f1f53-1b06-47a0-a0f0-e17637fa3b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578563992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2578563992
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1827783987
Short name T765
Test name
Test status
Simulation time 3049381827 ps
CPU time 4.31 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:25:42 PM PST 24
Peak memory 201152 kb
Host smart-dfce997d-04b5-49a8-acda-c62b24a51c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827783987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1827783987
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4217558431
Short name T661
Test name
Test status
Simulation time 5905684400 ps
CPU time 8.45 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:25:50 PM PST 24
Peak memory 201028 kb
Host smart-e19f27d3-9edd-4dba-8271-9c80d58b0615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217558431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4217558431
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4036970773
Short name T164
Test name
Test status
Simulation time 112949799777 ps
CPU time 193.06 seconds
Started Feb 28 04:25:54 PM PST 24
Finished Feb 28 04:29:07 PM PST 24
Peak memory 217376 kb
Host smart-abc0393d-ae9b-4a59-960d-337aab0b8885
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036970773 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4036970773
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2485627679
Short name T388
Test name
Test status
Simulation time 324631935 ps
CPU time 0.8 seconds
Started Feb 28 04:25:53 PM PST 24
Finished Feb 28 04:25:54 PM PST 24
Peak memory 201172 kb
Host smart-57fe2e56-d80f-4dbe-b571-8acbbeb2ddf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485627679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2485627679
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1614507657
Short name T748
Test name
Test status
Simulation time 489952082208 ps
CPU time 176.02 seconds
Started Feb 28 04:25:35 PM PST 24
Finished Feb 28 04:28:31 PM PST 24
Peak memory 201424 kb
Host smart-30a061d3-044f-478a-87fb-d0147c191322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614507657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1614507657
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2584228783
Short name T132
Test name
Test status
Simulation time 334954249580 ps
CPU time 151.05 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:28:09 PM PST 24
Peak memory 201468 kb
Host smart-92605430-720a-417c-9d9a-1dff24465540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584228783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2584228783
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4123804797
Short name T349
Test name
Test status
Simulation time 333291127554 ps
CPU time 729.63 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:37:47 PM PST 24
Peak memory 201380 kb
Host smart-478014e0-b57b-4fea-be75-bafbd5a3fcd9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123804797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4123804797
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2850607737
Short name T530
Test name
Test status
Simulation time 322736065234 ps
CPU time 191.96 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:28:49 PM PST 24
Peak memory 201408 kb
Host smart-d4890cd3-4b6f-4a6b-8bad-141538503e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850607737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2850607737
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.279734304
Short name T775
Test name
Test status
Simulation time 332525677998 ps
CPU time 776.19 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:38:40 PM PST 24
Peak memory 201356 kb
Host smart-428c8295-7576-497d-a6a8-7169a3a7089d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=279734304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.279734304
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.34156404
Short name T271
Test name
Test status
Simulation time 328391087080 ps
CPU time 686.07 seconds
Started Feb 28 04:25:34 PM PST 24
Finished Feb 28 04:37:00 PM PST 24
Peak memory 201344 kb
Host smart-a95918e1-128b-461e-8979-8d759c9c4d16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34156404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_w
akeup.34156404
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.112489769
Short name T407
Test name
Test status
Simulation time 323324299557 ps
CPU time 758.73 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:38:17 PM PST 24
Peak memory 201328 kb
Host smart-35ca2dc5-692d-4972-8c41-9ce70567424f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112489769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.112489769
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3547136725
Short name T463
Test name
Test status
Simulation time 65984235464 ps
CPU time 371.72 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:31:54 PM PST 24
Peak memory 201792 kb
Host smart-920673b4-481b-4b53-9117-aa86b090902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547136725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3547136725
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3693126557
Short name T514
Test name
Test status
Simulation time 34540748362 ps
CPU time 79.9 seconds
Started Feb 28 04:25:39 PM PST 24
Finished Feb 28 04:26:59 PM PST 24
Peak memory 201124 kb
Host smart-ca00f5fb-e358-4097-a8ec-a2560eae7af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693126557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3693126557
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4163328022
Short name T655
Test name
Test status
Simulation time 2971446433 ps
CPU time 4.04 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:25:42 PM PST 24
Peak memory 201208 kb
Host smart-10cfb118-acc4-46ce-949f-be244daba21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163328022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4163328022
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1868436157
Short name T356
Test name
Test status
Simulation time 5596585780 ps
CPU time 4.17 seconds
Started Feb 28 04:25:39 PM PST 24
Finished Feb 28 04:25:48 PM PST 24
Peak memory 201168 kb
Host smart-44e79a3b-61c8-4b71-aa5e-c10f3521b38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868436157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1868436157
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2298353898
Short name T630
Test name
Test status
Simulation time 48524427772 ps
CPU time 116.57 seconds
Started Feb 28 04:25:59 PM PST 24
Finished Feb 28 04:27:56 PM PST 24
Peak memory 209920 kb
Host smart-848349b5-0841-4659-aa14-35018800fe4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298353898 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2298353898
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3233839572
Short name T637
Test name
Test status
Simulation time 431144861 ps
CPU time 1.61 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:25:43 PM PST 24
Peak memory 201212 kb
Host smart-89516cc6-3f04-46e0-abc9-671621d375cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233839572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3233839572
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2681673235
Short name T199
Test name
Test status
Simulation time 166714480568 ps
CPU time 396.08 seconds
Started Feb 28 04:25:36 PM PST 24
Finished Feb 28 04:32:12 PM PST 24
Peak memory 201344 kb
Host smart-baea4499-12c8-4f22-a1fd-3ac8b321b1ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681673235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2681673235
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1141323085
Short name T280
Test name
Test status
Simulation time 504251883394 ps
CPU time 1174.48 seconds
Started Feb 28 04:25:40 PM PST 24
Finished Feb 28 04:45:15 PM PST 24
Peak memory 201500 kb
Host smart-3aa0ba32-34a9-417d-99bc-0ce443371d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141323085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1141323085
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1007491600
Short name T318
Test name
Test status
Simulation time 324279405536 ps
CPU time 389.75 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:32:08 PM PST 24
Peak memory 201460 kb
Host smart-daf4574c-3da6-42f6-8cad-de8bf148f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007491600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1007491600
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2908450555
Short name T7
Test name
Test status
Simulation time 171380506198 ps
CPU time 410.35 seconds
Started Feb 28 04:25:36 PM PST 24
Finished Feb 28 04:32:26 PM PST 24
Peak memory 201416 kb
Host smart-029d2550-ca72-43e6-aa5c-d9f8e4ca0500
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908450555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2908450555
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.308880754
Short name T710
Test name
Test status
Simulation time 494469690889 ps
CPU time 1102.84 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:44:04 PM PST 24
Peak memory 201508 kb
Host smart-17f7aee1-a6d7-4b87-a510-42b829b80c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308880754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.308880754
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1329913241
Short name T401
Test name
Test status
Simulation time 328808130136 ps
CPU time 735.32 seconds
Started Feb 28 04:25:39 PM PST 24
Finished Feb 28 04:38:05 PM PST 24
Peak memory 201400 kb
Host smart-8a14bb7d-42a5-4854-8aba-0034d6658015
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329913241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1329913241
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2707287107
Short name T138
Test name
Test status
Simulation time 323805643553 ps
CPU time 205.23 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:29:08 PM PST 24
Peak memory 201552 kb
Host smart-2da0e94b-f346-46ea-8d5f-aeb65c72ec5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707287107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2707287107
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1646582839
Short name T341
Test name
Test status
Simulation time 483140481666 ps
CPU time 313.13 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:30:51 PM PST 24
Peak memory 201472 kb
Host smart-3b1ce337-2c05-4926-8bb6-09250705cc14
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646582839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1646582839
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1678979462
Short name T572
Test name
Test status
Simulation time 133363810726 ps
CPU time 638.27 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:36:22 PM PST 24
Peak memory 201732 kb
Host smart-33fd5592-a361-4df4-b91f-9ad087f1ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678979462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1678979462
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2789279545
Short name T682
Test name
Test status
Simulation time 39016183096 ps
CPU time 46.74 seconds
Started Feb 28 04:25:39 PM PST 24
Finished Feb 28 04:26:26 PM PST 24
Peak memory 201148 kb
Host smart-f87ddf68-fad9-4822-9715-2af41ec3442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789279545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2789279545
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1999756633
Short name T740
Test name
Test status
Simulation time 5685156084 ps
CPU time 7.95 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:25:45 PM PST 24
Peak memory 201176 kb
Host smart-3d52303b-404f-496e-938c-3140bafe772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999756633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1999756633
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.742541340
Short name T462
Test name
Test status
Simulation time 5985972024 ps
CPU time 3.55 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:25:41 PM PST 24
Peak memory 201204 kb
Host smart-7c1130ab-b287-4180-8239-1a83802f02f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742541340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.742541340
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1249457791
Short name T24
Test name
Test status
Simulation time 89436480099 ps
CPU time 98.24 seconds
Started Feb 28 04:25:39 PM PST 24
Finished Feb 28 04:27:17 PM PST 24
Peak memory 209944 kb
Host smart-0f130262-bc7f-49d4-97b0-149c31ffe5c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249457791 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1249457791
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1198763048
Short name T46
Test name
Test status
Simulation time 455315328 ps
CPU time 1.05 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:25:45 PM PST 24
Peak memory 201072 kb
Host smart-1df46e16-7a90-4b3f-bb6f-48ed9aaa78f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198763048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1198763048
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1695870189
Short name T200
Test name
Test status
Simulation time 326205009958 ps
CPU time 677.62 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:37:00 PM PST 24
Peak memory 201288 kb
Host smart-c3195498-fe6e-49b6-be1d-c1f9e826ef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695870189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1695870189
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3403247909
Short name T521
Test name
Test status
Simulation time 160664588849 ps
CPU time 106.44 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:27:30 PM PST 24
Peak memory 201388 kb
Host smart-90fba15f-2a6a-4624-a7db-f3ea8b0eb169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403247909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3403247909
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.4037718040
Short name T785
Test name
Test status
Simulation time 166159419594 ps
CPU time 201.95 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:29:03 PM PST 24
Peak memory 201396 kb
Host smart-8a8be1d3-1001-435e-8fd0-b0a6a9493924
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037718040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.4037718040
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1183359220
Short name T253
Test name
Test status
Simulation time 487877048893 ps
CPU time 294.9 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:30:38 PM PST 24
Peak memory 201360 kb
Host smart-8ef95f07-f436-4dfa-beb4-6aef27e42522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183359220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1183359220
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3852249172
Short name T548
Test name
Test status
Simulation time 162159090720 ps
CPU time 78.77 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:26:57 PM PST 24
Peak memory 201364 kb
Host smart-1430d4a3-a908-4ce7-a1dd-90892743a5c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852249172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3852249172
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3423426673
Short name T285
Test name
Test status
Simulation time 337605598418 ps
CPU time 204.78 seconds
Started Feb 28 04:25:49 PM PST 24
Finished Feb 28 04:29:13 PM PST 24
Peak memory 201312 kb
Host smart-239fba7f-6cb5-4a6f-9b39-d89d50db9c37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423426673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3423426673
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2330668316
Short name T619
Test name
Test status
Simulation time 494408846337 ps
CPU time 185.4 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:28:43 PM PST 24
Peak memory 201420 kb
Host smart-f1eb6bf2-a6f1-4cec-8bf9-3261025cae45
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330668316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2330668316
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1540830124
Short name T770
Test name
Test status
Simulation time 69287883761 ps
CPU time 302.32 seconds
Started Feb 28 04:25:53 PM PST 24
Finished Feb 28 04:30:56 PM PST 24
Peak memory 201712 kb
Host smart-f1e7f5e2-ebbd-4b62-b288-178b830a842e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540830124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1540830124
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.955848881
Short name T444
Test name
Test status
Simulation time 25856455991 ps
CPU time 23.5 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:26:05 PM PST 24
Peak memory 201212 kb
Host smart-6249b96b-9e78-480a-9966-85fcd0198059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955848881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.955848881
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2582574153
Short name T553
Test name
Test status
Simulation time 3962229023 ps
CPU time 5.33 seconds
Started Feb 28 04:25:47 PM PST 24
Finished Feb 28 04:25:53 PM PST 24
Peak memory 201216 kb
Host smart-257057d3-db66-4647-ad55-9fe9eb2e05d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582574153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2582574153
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1343980053
Short name T613
Test name
Test status
Simulation time 5821414745 ps
CPU time 6.23 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:25:50 PM PST 24
Peak memory 201116 kb
Host smart-eec6d271-af29-41e0-aef0-de6ff35b14d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343980053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1343980053
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.586559062
Short name T29
Test name
Test status
Simulation time 221349340918 ps
CPU time 885.86 seconds
Started Feb 28 04:25:35 PM PST 24
Finished Feb 28 04:40:21 PM PST 24
Peak memory 201720 kb
Host smart-ddded51e-801b-4a06-a12e-b124d6411a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586559062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
586559062
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1256514173
Short name T267
Test name
Test status
Simulation time 26604487309 ps
CPU time 40.49 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:26:18 PM PST 24
Peak memory 201936 kb
Host smart-bad5981a-3387-48f5-9541-0080949cc445
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256514173 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1256514173
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2129562600
Short name T516
Test name
Test status
Simulation time 436843105 ps
CPU time 0.84 seconds
Started Feb 28 04:24:46 PM PST 24
Finished Feb 28 04:24:47 PM PST 24
Peak memory 201136 kb
Host smart-ba5ee2b4-73cd-48f0-bd18-e0c6f19f1113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129562600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2129562600
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1842522458
Short name T289
Test name
Test status
Simulation time 178131349381 ps
CPU time 96.8 seconds
Started Feb 28 04:24:50 PM PST 24
Finished Feb 28 04:26:32 PM PST 24
Peak memory 201512 kb
Host smart-eddc30c1-9a2f-40c2-87fd-8e8fe6846f6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842522458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1842522458
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.879684246
Short name T758
Test name
Test status
Simulation time 164941430676 ps
CPU time 204.08 seconds
Started Feb 28 04:24:29 PM PST 24
Finished Feb 28 04:27:53 PM PST 24
Peak memory 201472 kb
Host smart-a2235033-7a9a-4e7f-8640-8ea5995345b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879684246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.879684246
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.324289526
Short name T745
Test name
Test status
Simulation time 498546836287 ps
CPU time 287.91 seconds
Started Feb 28 04:24:44 PM PST 24
Finished Feb 28 04:29:37 PM PST 24
Peak memory 201304 kb
Host smart-6d0523e5-1322-4465-804d-f79ad6f713ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=324289526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.324289526
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1872417524
Short name T717
Test name
Test status
Simulation time 164015474073 ps
CPU time 201.92 seconds
Started Feb 28 04:25:01 PM PST 24
Finished Feb 28 04:28:23 PM PST 24
Peak memory 201332 kb
Host smart-4d5f08bc-dc6a-44cb-ae50-cf3658bedaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872417524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1872417524
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3688455164
Short name T435
Test name
Test status
Simulation time 480760684819 ps
CPU time 1156.63 seconds
Started Feb 28 04:24:43 PM PST 24
Finished Feb 28 04:44:00 PM PST 24
Peak memory 201540 kb
Host smart-9115bbc1-e720-4227-868a-dc5fa00543d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688455164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3688455164
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2158710615
Short name T11
Test name
Test status
Simulation time 498298091273 ps
CPU time 1074.59 seconds
Started Feb 28 04:24:35 PM PST 24
Finished Feb 28 04:42:30 PM PST 24
Peak memory 201356 kb
Host smart-69cdf1ab-1bca-4a7b-b9f2-fd8f2e289a8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158710615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2158710615
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.4117304241
Short name T410
Test name
Test status
Simulation time 494844817056 ps
CPU time 67.59 seconds
Started Feb 28 04:25:12 PM PST 24
Finished Feb 28 04:26:20 PM PST 24
Peak memory 201384 kb
Host smart-4273bf23-6174-4b30-b833-ec8cd4b67c0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117304241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.4117304241
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.795538825
Short name T448
Test name
Test status
Simulation time 44404800864 ps
CPU time 99.76 seconds
Started Feb 28 04:24:36 PM PST 24
Finished Feb 28 04:26:16 PM PST 24
Peak memory 201240 kb
Host smart-770556d5-7a4b-4437-9029-ccbe016feb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795538825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.795538825
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1079548181
Short name T600
Test name
Test status
Simulation time 5357131996 ps
CPU time 7.45 seconds
Started Feb 28 04:24:51 PM PST 24
Finished Feb 28 04:24:58 PM PST 24
Peak memory 201204 kb
Host smart-054fbb18-b4ce-4fc1-8e2f-7d7c35440c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079548181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1079548181
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.4241465075
Short name T50
Test name
Test status
Simulation time 4373037977 ps
CPU time 3.1 seconds
Started Feb 28 04:24:41 PM PST 24
Finished Feb 28 04:24:44 PM PST 24
Peak memory 216132 kb
Host smart-ab170ac0-5ff8-48af-b973-fd914866a662
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241465075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.4241465075
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1951829249
Short name T703
Test name
Test status
Simulation time 6163295106 ps
CPU time 7.57 seconds
Started Feb 28 04:24:49 PM PST 24
Finished Feb 28 04:24:57 PM PST 24
Peak memory 201184 kb
Host smart-a7723dae-3f39-46e1-9e5e-28997709c9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951829249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1951829249
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1125708884
Short name T781
Test name
Test status
Simulation time 241505788925 ps
CPU time 749.45 seconds
Started Feb 28 04:24:37 PM PST 24
Finished Feb 28 04:37:07 PM PST 24
Peak memory 211304 kb
Host smart-40daa250-1308-4b6c-a35e-33a8cb687e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125708884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1125708884
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2104425812
Short name T310
Test name
Test status
Simulation time 216536049255 ps
CPU time 125.01 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:26:55 PM PST 24
Peak memory 210076 kb
Host smart-6e7518b3-fc1f-47d0-986a-567cf651c42a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104425812 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2104425812
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2460529100
Short name T392
Test name
Test status
Simulation time 537658059 ps
CPU time 0.89 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:25:45 PM PST 24
Peak memory 201128 kb
Host smart-9d855330-f8fb-4dda-be3b-7f28fd4ccdcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460529100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2460529100
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2529100558
Short name T563
Test name
Test status
Simulation time 168758020538 ps
CPU time 364.04 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:31:46 PM PST 24
Peak memory 201440 kb
Host smart-0c67a84b-2fe1-497e-be7d-9d1e034da511
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529100558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2529100558
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2478726212
Short name T319
Test name
Test status
Simulation time 337728619438 ps
CPU time 780.8 seconds
Started Feb 28 04:25:54 PM PST 24
Finished Feb 28 04:38:56 PM PST 24
Peak memory 201348 kb
Host smart-276bf1e6-e6dc-4976-bd90-7eadaaeebc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478726212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2478726212
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2992878205
Short name T721
Test name
Test status
Simulation time 491075864115 ps
CPU time 305.13 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:30:49 PM PST 24
Peak memory 201140 kb
Host smart-41bba3dc-3555-4a52-aea6-bddc34c8a50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992878205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2992878205
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3654343795
Short name T525
Test name
Test status
Simulation time 327933781533 ps
CPU time 747.11 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:38:19 PM PST 24
Peak memory 201400 kb
Host smart-69b63de0-4a05-4641-9f52-9e1180baa454
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654343795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3654343795
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1449780684
Short name T733
Test name
Test status
Simulation time 495090815597 ps
CPU time 570.9 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:35:12 PM PST 24
Peak memory 201412 kb
Host smart-201cfd70-0be9-4d5d-90b4-e2ac9534b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449780684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1449780684
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1603584055
Short name T609
Test name
Test status
Simulation time 322225640753 ps
CPU time 779.99 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:38:43 PM PST 24
Peak memory 201408 kb
Host smart-aa774ac5-fae8-43bf-9dd7-aca3a619cdfe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603584055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1603584055
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2993394881
Short name T673
Test name
Test status
Simulation time 169391534254 ps
CPU time 390.46 seconds
Started Feb 28 04:25:36 PM PST 24
Finished Feb 28 04:32:07 PM PST 24
Peak memory 201396 kb
Host smart-fc474e6c-1c97-4441-8c1c-72dae7b7d1ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993394881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2993394881
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3889954669
Short name T398
Test name
Test status
Simulation time 162490339376 ps
CPU time 401.43 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:32:40 PM PST 24
Peak memory 201376 kb
Host smart-9e1f59c5-7a98-4806-b89d-7c1e9b799d6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889954669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3889954669
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3913531553
Short name T187
Test name
Test status
Simulation time 71676817549 ps
CPU time 376.75 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:31:55 PM PST 24
Peak memory 201700 kb
Host smart-cca09c35-ac79-4c9e-8256-1b6f6738601f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913531553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3913531553
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3345075821
Short name T366
Test name
Test status
Simulation time 32346172752 ps
CPU time 76.55 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:27:01 PM PST 24
Peak memory 201204 kb
Host smart-8f0bc9cb-8999-4bd9-8d1b-45b8ec366bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345075821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3345075821
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3473016601
Short name T625
Test name
Test status
Simulation time 3326303327 ps
CPU time 2.52 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:25:44 PM PST 24
Peak memory 201124 kb
Host smart-2fb24dc3-6638-408d-879f-b0e387dfc8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473016601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3473016601
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3754145993
Short name T379
Test name
Test status
Simulation time 6055261590 ps
CPU time 16.45 seconds
Started Feb 28 04:25:46 PM PST 24
Finished Feb 28 04:26:03 PM PST 24
Peak memory 201284 kb
Host smart-e8fa344c-55e6-41fe-86fa-03371f76ac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754145993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3754145993
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2461363097
Short name T766
Test name
Test status
Simulation time 291903661397 ps
CPU time 687.2 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:37:09 PM PST 24
Peak memory 211804 kb
Host smart-26c7918f-46c2-4794-a61c-8b58f3c0976c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461363097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2461363097
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3237181563
Short name T38
Test name
Test status
Simulation time 94733018104 ps
CPU time 274.94 seconds
Started Feb 28 04:25:35 PM PST 24
Finished Feb 28 04:30:10 PM PST 24
Peak memory 211064 kb
Host smart-6a7b7bbe-0ba6-4b5a-acb0-299ba0d3866f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237181563 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3237181563
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.603307134
Short name T747
Test name
Test status
Simulation time 449523062 ps
CPU time 0.74 seconds
Started Feb 28 04:25:55 PM PST 24
Finished Feb 28 04:25:57 PM PST 24
Peak memory 201100 kb
Host smart-b7abf1bb-c755-4646-a7e8-a161b15a5b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603307134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.603307134
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.145971495
Short name T215
Test name
Test status
Simulation time 322154754271 ps
CPU time 62.08 seconds
Started Feb 28 04:25:36 PM PST 24
Finished Feb 28 04:26:38 PM PST 24
Peak memory 201352 kb
Host smart-9115691b-d46d-4fcb-9035-8a7f7064dc84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145971495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.145971495
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3770610753
Short name T571
Test name
Test status
Simulation time 168778858237 ps
CPU time 384.34 seconds
Started Feb 28 04:25:48 PM PST 24
Finished Feb 28 04:32:12 PM PST 24
Peak memory 201356 kb
Host smart-89a7e636-04a3-45dc-b0aa-e5f9b85ae3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770610753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3770610753
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3818935577
Short name T416
Test name
Test status
Simulation time 164804220852 ps
CPU time 105.42 seconds
Started Feb 28 04:25:53 PM PST 24
Finished Feb 28 04:27:39 PM PST 24
Peak memory 201480 kb
Host smart-f2c86d1b-ef18-4962-b9db-35c11acb9ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818935577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3818935577
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2053562662
Short name T484
Test name
Test status
Simulation time 327199479855 ps
CPU time 819.54 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:39:22 PM PST 24
Peak memory 201464 kb
Host smart-43165949-f2c0-4902-9880-2ee8bed320de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053562662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2053562662
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.874872284
Short name T141
Test name
Test status
Simulation time 158189940784 ps
CPU time 86.51 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:27:15 PM PST 24
Peak memory 201408 kb
Host smart-2370daa5-3d03-4cad-82f2-0a78773a5661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874872284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.874872284
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1022946386
Short name T511
Test name
Test status
Simulation time 335465599678 ps
CPU time 43.52 seconds
Started Feb 28 04:25:46 PM PST 24
Finished Feb 28 04:26:30 PM PST 24
Peak memory 201352 kb
Host smart-c300b6ec-78fa-46a4-ad3c-f6928b613907
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022946386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1022946386
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3177958244
Short name T546
Test name
Test status
Simulation time 504056891139 ps
CPU time 1119.61 seconds
Started Feb 28 04:25:40 PM PST 24
Finished Feb 28 04:44:20 PM PST 24
Peak memory 201396 kb
Host smart-c73f4d8a-1ee9-4ed0-8505-d174160e4b0d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177958244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3177958244
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.4124964269
Short name T788
Test name
Test status
Simulation time 74491825887 ps
CPU time 407.04 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:32:31 PM PST 24
Peak memory 201688 kb
Host smart-b853dd6b-ec15-45c7-8ac2-7561afabb1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124964269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.4124964269
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2827635925
Short name T436
Test name
Test status
Simulation time 25301611250 ps
CPU time 53.12 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:26:34 PM PST 24
Peak memory 201152 kb
Host smart-561a273c-ef97-4b0b-9ea1-7d690d1ea95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827635925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2827635925
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.239384584
Short name T660
Test name
Test status
Simulation time 3067069168 ps
CPU time 7 seconds
Started Feb 28 04:25:45 PM PST 24
Finished Feb 28 04:25:57 PM PST 24
Peak memory 201212 kb
Host smart-cf69883f-4d79-4fb9-bef8-9c0c890c7792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239384584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.239384584
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1718237068
Short name T424
Test name
Test status
Simulation time 5986045719 ps
CPU time 1.99 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:25:54 PM PST 24
Peak memory 201200 kb
Host smart-467f861f-6a9c-4ada-a2d3-1614c2fbea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718237068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1718237068
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3492832973
Short name T195
Test name
Test status
Simulation time 496880371232 ps
CPU time 563.94 seconds
Started Feb 28 04:25:51 PM PST 24
Finished Feb 28 04:35:15 PM PST 24
Peak memory 201420 kb
Host smart-bae10ac4-4c95-424e-b5f3-7c395f916e5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492832973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3492832973
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2188010724
Short name T72
Test name
Test status
Simulation time 51425009303 ps
CPU time 186.61 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:28:51 PM PST 24
Peak memory 218212 kb
Host smart-dc82088f-a91f-4c2a-b02b-eafe0c21393d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188010724 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2188010724
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.407232793
Short name T446
Test name
Test status
Simulation time 279751080 ps
CPU time 1.3 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:25:45 PM PST 24
Peak memory 200836 kb
Host smart-847d9708-7d8f-431e-9445-26a3bbc0c33a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407232793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.407232793
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1392938597
Short name T753
Test name
Test status
Simulation time 491761643383 ps
CPU time 68.32 seconds
Started Feb 28 04:25:54 PM PST 24
Finished Feb 28 04:27:03 PM PST 24
Peak memory 201368 kb
Host smart-2cc86729-8d0c-4e78-aaa7-c084c6fc6187
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392938597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1392938597
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2384942828
Short name T241
Test name
Test status
Simulation time 171582112770 ps
CPU time 107.55 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:27:31 PM PST 24
Peak memory 201444 kb
Host smart-b88d5e82-21db-4ff9-84f0-f978c92f2db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384942828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2384942828
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2812113798
Short name T203
Test name
Test status
Simulation time 490991623297 ps
CPU time 312.34 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:30:54 PM PST 24
Peak memory 201420 kb
Host smart-0d17d0b7-8630-47ca-962c-cec54e18cb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812113798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2812113798
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3382619118
Short name T465
Test name
Test status
Simulation time 491495059102 ps
CPU time 1132.55 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:44:45 PM PST 24
Peak memory 201436 kb
Host smart-821a55cb-f207-480a-a501-0c3d3e190604
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382619118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3382619118
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2085324594
Short name T119
Test name
Test status
Simulation time 495479893649 ps
CPU time 1177.97 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:45:30 PM PST 24
Peak memory 201320 kb
Host smart-526f0f9a-f28e-4a8e-b904-2abd043e17ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085324594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2085324594
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.14147567
Short name T124
Test name
Test status
Simulation time 330169658638 ps
CPU time 780.2 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:38:43 PM PST 24
Peak memory 201416 kb
Host smart-567cf3eb-d139-4571-baf5-3d78ca6e1dd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=14147567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed
.14147567
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.330821777
Short name T668
Test name
Test status
Simulation time 498004101845 ps
CPU time 1062.61 seconds
Started Feb 28 04:25:58 PM PST 24
Finished Feb 28 04:43:42 PM PST 24
Peak memory 201356 kb
Host smart-fafbef58-3c99-4fc0-be95-705cbcc59da7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330821777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.330821777
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3329618039
Short name T174
Test name
Test status
Simulation time 74560061311 ps
CPU time 361 seconds
Started Feb 28 04:25:40 PM PST 24
Finished Feb 28 04:31:41 PM PST 24
Peak memory 201748 kb
Host smart-f938aad3-00ac-47ec-bfe4-c491548c3091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329618039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3329618039
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.179309617
Short name T455
Test name
Test status
Simulation time 34973659687 ps
CPU time 69.07 seconds
Started Feb 28 04:25:51 PM PST 24
Finished Feb 28 04:27:01 PM PST 24
Peak memory 201168 kb
Host smart-39674a9b-e171-47cb-81a3-7f130543c3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179309617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.179309617
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2639096431
Short name T647
Test name
Test status
Simulation time 2950560055 ps
CPU time 2.58 seconds
Started Feb 28 04:25:35 PM PST 24
Finished Feb 28 04:25:38 PM PST 24
Peak memory 201168 kb
Host smart-c798dc79-009c-4959-9b9d-2203437b0ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639096431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2639096431
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3805904491
Short name T333
Test name
Test status
Simulation time 5590864480 ps
CPU time 7.39 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:25:51 PM PST 24
Peak memory 201136 kb
Host smart-f5317b86-0998-45d6-ae4d-aaf194d655fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805904491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3805904491
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2747529132
Short name T680
Test name
Test status
Simulation time 322419190123 ps
CPU time 142.05 seconds
Started Feb 28 04:25:59 PM PST 24
Finished Feb 28 04:28:22 PM PST 24
Peak memory 201464 kb
Host smart-a7d7aaec-0946-4867-a502-de4644225e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747529132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2747529132
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2874682057
Short name T596
Test name
Test status
Simulation time 364006545874 ps
CPU time 324.73 seconds
Started Feb 28 04:25:58 PM PST 24
Finished Feb 28 04:31:24 PM PST 24
Peak memory 210076 kb
Host smart-031ef6c7-b904-48d3-a3fd-7d8b1a70095d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874682057 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2874682057
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3356257176
Short name T458
Test name
Test status
Simulation time 412155653 ps
CPU time 1 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:26:00 PM PST 24
Peak memory 201132 kb
Host smart-df65dddf-8289-41fe-86ae-ec9d1c0b3908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356257176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3356257176
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3568590352
Short name T567
Test name
Test status
Simulation time 165511290068 ps
CPU time 402.19 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:32:26 PM PST 24
Peak memory 201468 kb
Host smart-3db2684a-6cb1-4876-97d7-9a6ea7aacbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568590352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3568590352
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.903479120
Short name T500
Test name
Test status
Simulation time 321611718278 ps
CPU time 192.3 seconds
Started Feb 28 04:25:40 PM PST 24
Finished Feb 28 04:28:52 PM PST 24
Peak memory 201440 kb
Host smart-2714b88f-3a25-49af-8e79-e427708e71ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903479120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.903479120
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3408662084
Short name T693
Test name
Test status
Simulation time 329732737059 ps
CPU time 817.09 seconds
Started Feb 28 04:25:48 PM PST 24
Finished Feb 28 04:39:25 PM PST 24
Peak memory 201376 kb
Host smart-671211ce-fb92-4e8e-8637-9dd6ae386b07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408662084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3408662084
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.985235588
Short name T148
Test name
Test status
Simulation time 489415852096 ps
CPU time 297.07 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:30:41 PM PST 24
Peak memory 201308 kb
Host smart-67865d36-e1e0-4907-a91c-8364c95f4869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985235588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.985235588
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1078608037
Short name T490
Test name
Test status
Simulation time 163327828514 ps
CPU time 123.7 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:27:48 PM PST 24
Peak memory 201376 kb
Host smart-ade33e45-68f3-46c3-a25e-88c3775e4533
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078608037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1078608037
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3294302368
Short name T773
Test name
Test status
Simulation time 171035232998 ps
CPU time 271.26 seconds
Started Feb 28 04:25:46 PM PST 24
Finished Feb 28 04:30:17 PM PST 24
Peak memory 201484 kb
Host smart-c7a3f408-29fb-409d-887a-d4bbd1a8edd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294302368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3294302368
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.4058438071
Short name T404
Test name
Test status
Simulation time 330358683881 ps
CPU time 727.34 seconds
Started Feb 28 04:25:53 PM PST 24
Finished Feb 28 04:38:00 PM PST 24
Peak memory 201264 kb
Host smart-672c12a3-6c0e-4327-90bc-e062e222f2fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058438071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.4058438071
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1625292348
Short name T172
Test name
Test status
Simulation time 117217635242 ps
CPU time 451.02 seconds
Started Feb 28 04:25:50 PM PST 24
Finished Feb 28 04:33:21 PM PST 24
Peak memory 201800 kb
Host smart-f03c0c20-a586-473d-86e5-bfa860c448e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625292348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1625292348
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2481280799
Short name T719
Test name
Test status
Simulation time 40980365307 ps
CPU time 88.49 seconds
Started Feb 28 04:25:49 PM PST 24
Finished Feb 28 04:27:18 PM PST 24
Peak memory 201056 kb
Host smart-5e1fbf2b-47cf-4c24-9aa2-f32a88d9336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481280799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2481280799
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.330330470
Short name T557
Test name
Test status
Simulation time 3097580868 ps
CPU time 2.11 seconds
Started Feb 28 04:25:40 PM PST 24
Finished Feb 28 04:25:43 PM PST 24
Peak memory 201260 kb
Host smart-e0ce98b4-b716-43a8-8ff8-b2e5092ec79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330330470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.330330470
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2227196191
Short name T537
Test name
Test status
Simulation time 5670944173 ps
CPU time 3.9 seconds
Started Feb 28 04:26:01 PM PST 24
Finished Feb 28 04:26:05 PM PST 24
Peak memory 201212 kb
Host smart-901773cd-5f9e-4da9-8ded-a8600fdff080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227196191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2227196191
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1364605057
Short name T659
Test name
Test status
Simulation time 337574710685 ps
CPU time 430.07 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:33:03 PM PST 24
Peak memory 201440 kb
Host smart-0ebf4fed-2148-47e0-aeb8-17bf9d20673a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364605057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1364605057
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.288506936
Short name T591
Test name
Test status
Simulation time 13193537512 ps
CPU time 8.04 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:25:52 PM PST 24
Peak memory 201572 kb
Host smart-bb467f96-38e0-44c8-ae79-e15513b1dfeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288506936 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.288506936
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.4257002052
Short name T43
Test name
Test status
Simulation time 528103140 ps
CPU time 0.88 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:25:43 PM PST 24
Peak memory 201076 kb
Host smart-43f20af2-f6ba-4627-9bc4-71aeae7dd161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257002052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.4257002052
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.347933515
Short name T116
Test name
Test status
Simulation time 324787227364 ps
CPU time 699.28 seconds
Started Feb 28 04:25:55 PM PST 24
Finished Feb 28 04:37:34 PM PST 24
Peak memory 201464 kb
Host smart-eecc8151-cb64-4564-a918-7b64e063b538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347933515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.347933515
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1800719391
Short name T339
Test name
Test status
Simulation time 318861052127 ps
CPU time 153.72 seconds
Started Feb 28 04:25:47 PM PST 24
Finished Feb 28 04:28:21 PM PST 24
Peak memory 201268 kb
Host smart-6294d460-69a6-49b8-aa7e-bcf43496ff5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800719391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1800719391
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.653213887
Short name T450
Test name
Test status
Simulation time 489254221204 ps
CPU time 1138.61 seconds
Started Feb 28 04:25:54 PM PST 24
Finished Feb 28 04:44:53 PM PST 24
Peak memory 201260 kb
Host smart-8d18be07-f397-4eea-8284-443647feb294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653213887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.653213887
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.278767538
Short name T431
Test name
Test status
Simulation time 322002198247 ps
CPU time 197.14 seconds
Started Feb 28 04:26:01 PM PST 24
Finished Feb 28 04:29:19 PM PST 24
Peak memory 201256 kb
Host smart-cb74e71c-4639-4718-8f62-eb73002855ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=278767538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.278767538
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3204546143
Short name T687
Test name
Test status
Simulation time 159707619951 ps
CPU time 101.37 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:27:25 PM PST 24
Peak memory 201388 kb
Host smart-6eb44812-1448-46cd-b291-d92ac0d24409
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204546143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3204546143
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3186561771
Short name T183
Test name
Test status
Simulation time 107772424238 ps
CPU time 400.93 seconds
Started Feb 28 04:25:37 PM PST 24
Finished Feb 28 04:32:18 PM PST 24
Peak memory 201560 kb
Host smart-ef3e21f6-2879-40f6-8e17-92fb821e8b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186561771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3186561771
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.740708651
Short name T469
Test name
Test status
Simulation time 36642143645 ps
CPU time 45.34 seconds
Started Feb 28 04:25:59 PM PST 24
Finished Feb 28 04:26:45 PM PST 24
Peak memory 201048 kb
Host smart-0396c492-6529-4d58-8841-466abf9d921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740708651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.740708651
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2847557894
Short name T724
Test name
Test status
Simulation time 4342891600 ps
CPU time 5.36 seconds
Started Feb 28 04:26:07 PM PST 24
Finished Feb 28 04:26:13 PM PST 24
Peak memory 201224 kb
Host smart-6eae99e7-5d3f-42b6-90cb-d80fa7c08454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847557894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2847557894
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3534926089
Short name T453
Test name
Test status
Simulation time 5767263588 ps
CPU time 5.86 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:25:50 PM PST 24
Peak memory 201164 kb
Host smart-65a1733b-d60a-4b0e-b4ba-e1d2029aeb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534926089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3534926089
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.133495474
Short name T144
Test name
Test status
Simulation time 357788856081 ps
CPU time 892.2 seconds
Started Feb 28 04:25:47 PM PST 24
Finished Feb 28 04:40:40 PM PST 24
Peak memory 201400 kb
Host smart-f51b0843-f3ff-40ce-a6a0-d7b8ee947d75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133495474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
133495474
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.4069378879
Short name T423
Test name
Test status
Simulation time 391757499 ps
CPU time 0.7 seconds
Started Feb 28 04:25:56 PM PST 24
Finished Feb 28 04:25:57 PM PST 24
Peak memory 201144 kb
Host smart-369b7f9c-63f6-411d-9ee1-22fc90b21962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069378879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.4069378879
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1085084157
Short name T205
Test name
Test status
Simulation time 497446362407 ps
CPU time 690.67 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:37:30 PM PST 24
Peak memory 201460 kb
Host smart-08477cc2-8b5a-494c-b0fd-8213a371911c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085084157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1085084157
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1108382823
Short name T316
Test name
Test status
Simulation time 166275621385 ps
CPU time 382.88 seconds
Started Feb 28 04:25:49 PM PST 24
Finished Feb 28 04:32:12 PM PST 24
Peak memory 201480 kb
Host smart-ab8c0f0e-86db-49a0-ab4f-9047892d0fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108382823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1108382823
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2532834714
Short name T338
Test name
Test status
Simulation time 329419083367 ps
CPU time 206.87 seconds
Started Feb 28 04:26:00 PM PST 24
Finished Feb 28 04:29:28 PM PST 24
Peak memory 201392 kb
Host smart-8e46c2eb-8d30-4292-adeb-c9f1bbae542a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532834714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2532834714
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1756357057
Short name T526
Test name
Test status
Simulation time 160650651558 ps
CPU time 353.81 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:31:38 PM PST 24
Peak memory 201464 kb
Host smart-5dfc48c5-1034-444c-96d9-eac5c6c3fb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756357057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1756357057
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.259921217
Short name T432
Test name
Test status
Simulation time 165405657514 ps
CPU time 49.75 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:26:32 PM PST 24
Peak memory 201380 kb
Host smart-947540cc-3a4b-44c8-b26f-b59cc95d72cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=259921217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.259921217
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2303006188
Short name T777
Test name
Test status
Simulation time 328992639085 ps
CPU time 139.71 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:28:01 PM PST 24
Peak memory 201484 kb
Host smart-aa626ae6-8272-4e72-9801-ba7df120b2e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303006188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2303006188
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2138025080
Short name T653
Test name
Test status
Simulation time 486266241578 ps
CPU time 574.45 seconds
Started Feb 28 04:26:03 PM PST 24
Finished Feb 28 04:35:38 PM PST 24
Peak memory 201352 kb
Host smart-e81944d8-cbf7-4a21-96a8-7585be62ad93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138025080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2138025080
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1786538685
Short name T186
Test name
Test status
Simulation time 75723678460 ps
CPU time 410.73 seconds
Started Feb 28 04:26:03 PM PST 24
Finished Feb 28 04:32:54 PM PST 24
Peak memory 201648 kb
Host smart-51962ff0-5c5a-425c-9e7d-f6251977bf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786538685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1786538685
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2442028784
Short name T106
Test name
Test status
Simulation time 31334365130 ps
CPU time 12.09 seconds
Started Feb 28 04:25:55 PM PST 24
Finished Feb 28 04:26:08 PM PST 24
Peak memory 201200 kb
Host smart-26ef070a-152a-415f-8eba-e1688bfefc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442028784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2442028784
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.4039472231
Short name T374
Test name
Test status
Simulation time 4782894745 ps
CPU time 9.61 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:25:54 PM PST 24
Peak memory 201052 kb
Host smart-b02562d0-d75e-4653-87f6-8e6923dcfba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039472231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.4039472231
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3248983749
Short name T741
Test name
Test status
Simulation time 5818205866 ps
CPU time 3.63 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:26:02 PM PST 24
Peak memory 201052 kb
Host smart-7860c8fe-27a5-4fb9-a305-95d4218edbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248983749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3248983749
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1914717830
Short name T672
Test name
Test status
Simulation time 322866105800 ps
CPU time 780.23 seconds
Started Feb 28 04:26:04 PM PST 24
Finished Feb 28 04:39:05 PM PST 24
Peak memory 201372 kb
Host smart-4c5e985a-2265-4942-857e-d5d297e1dd86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914717830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1914717830
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3704874457
Short name T158
Test name
Test status
Simulation time 55117537899 ps
CPU time 199.93 seconds
Started Feb 28 04:26:01 PM PST 24
Finished Feb 28 04:29:21 PM PST 24
Peak memory 210040 kb
Host smart-d7f338f8-a725-42aa-a697-bb2a167dc929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704874457 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3704874457
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3857229071
Short name T481
Test name
Test status
Simulation time 458512276 ps
CPU time 1.55 seconds
Started Feb 28 04:25:50 PM PST 24
Finished Feb 28 04:25:52 PM PST 24
Peak memory 201032 kb
Host smart-0b0a408a-8b2c-460a-b8a6-68d146e7805f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857229071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3857229071
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1354074564
Short name T595
Test name
Test status
Simulation time 167926483448 ps
CPU time 385.92 seconds
Started Feb 28 04:25:59 PM PST 24
Finished Feb 28 04:32:26 PM PST 24
Peak memory 201452 kb
Host smart-a9f97445-0123-467d-a042-fb18bef76cd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354074564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1354074564
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2159649127
Short name T690
Test name
Test status
Simulation time 168067835558 ps
CPU time 211.99 seconds
Started Feb 28 04:26:05 PM PST 24
Finished Feb 28 04:29:38 PM PST 24
Peak memory 201524 kb
Host smart-5c913995-dffa-4009-9bf3-89798f97c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159649127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2159649127
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1301885197
Short name T220
Test name
Test status
Simulation time 161228403312 ps
CPU time 99.31 seconds
Started Feb 28 04:26:01 PM PST 24
Finished Feb 28 04:27:41 PM PST 24
Peak memory 201380 kb
Host smart-c64d7792-185b-4359-be7c-13576211cbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301885197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1301885197
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3958984481
Short name T550
Test name
Test status
Simulation time 326913855920 ps
CPU time 748.92 seconds
Started Feb 28 04:25:38 PM PST 24
Finished Feb 28 04:38:07 PM PST 24
Peak memory 201396 kb
Host smart-aab52f8d-6d86-42e9-b44c-1827dcadec27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958984481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3958984481
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2003332270
Short name T67
Test name
Test status
Simulation time 168134232142 ps
CPU time 193.68 seconds
Started Feb 28 04:26:03 PM PST 24
Finished Feb 28 04:29:17 PM PST 24
Peak memory 201424 kb
Host smart-734ecf00-1fb9-4b43-9bc9-61c40edc22f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003332270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2003332270
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.788083578
Short name T663
Test name
Test status
Simulation time 163808416184 ps
CPU time 189.34 seconds
Started Feb 28 04:25:45 PM PST 24
Finished Feb 28 04:28:54 PM PST 24
Peak memory 201396 kb
Host smart-90f8ce88-6da1-48a3-87a7-2dafc490a730
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=788083578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.788083578
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1377375754
Short name T743
Test name
Test status
Simulation time 168819589163 ps
CPU time 218.26 seconds
Started Feb 28 04:26:00 PM PST 24
Finished Feb 28 04:29:39 PM PST 24
Peak memory 201468 kb
Host smart-7bd1382a-4bb2-4858-9d7b-19116c9e0936
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377375754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1377375754
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4165412695
Short name T624
Test name
Test status
Simulation time 170326239589 ps
CPU time 196.52 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:29:15 PM PST 24
Peak memory 201320 kb
Host smart-9f260a1e-dc36-4914-94fe-a4ecfeeb7b9f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165412695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4165412695
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1137224346
Short name T185
Test name
Test status
Simulation time 125186646686 ps
CPU time 409.78 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:32:48 PM PST 24
Peak memory 201732 kb
Host smart-59ffb1a8-2107-437a-b19e-961e4f3014c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137224346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1137224346
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2879414734
Short name T477
Test name
Test status
Simulation time 33191617963 ps
CPU time 37.79 seconds
Started Feb 28 04:25:46 PM PST 24
Finished Feb 28 04:26:24 PM PST 24
Peak memory 201116 kb
Host smart-1addb7ae-adef-45de-b687-2edbceb76fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879414734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2879414734
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1905641315
Short name T393
Test name
Test status
Simulation time 4636027583 ps
CPU time 11.72 seconds
Started Feb 28 04:25:56 PM PST 24
Finished Feb 28 04:26:09 PM PST 24
Peak memory 201096 kb
Host smart-808fb8e3-139a-46cd-8af9-0c4500546783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905641315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1905641315
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3840640256
Short name T369
Test name
Test status
Simulation time 6164544591 ps
CPU time 7.3 seconds
Started Feb 28 04:26:03 PM PST 24
Finished Feb 28 04:26:11 PM PST 24
Peak memory 201048 kb
Host smart-9c18912f-2e86-4888-85a7-9f6e515c8abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840640256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3840640256
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.695696231
Short name T279
Test name
Test status
Simulation time 366681131547 ps
CPU time 712.34 seconds
Started Feb 28 04:25:59 PM PST 24
Finished Feb 28 04:37:52 PM PST 24
Peak memory 201352 kb
Host smart-aa2b9229-0cf9-4586-b0d2-168294fc9e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695696231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
695696231
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3041345331
Short name T623
Test name
Test status
Simulation time 28380087489 ps
CPU time 25.52 seconds
Started Feb 28 04:25:50 PM PST 24
Finished Feb 28 04:26:15 PM PST 24
Peak memory 201364 kb
Host smart-5c9ef1cb-cab1-4118-85f0-45377839f9aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041345331 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3041345331
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3568581768
Short name T412
Test name
Test status
Simulation time 545231654 ps
CPU time 0.9 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:25:45 PM PST 24
Peak memory 201072 kb
Host smart-cc0001f7-1a1a-4ed6-85cd-1c7c3f59ed17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568581768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3568581768
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4174205027
Short name T218
Test name
Test status
Simulation time 165131680800 ps
CPU time 203.11 seconds
Started Feb 28 04:26:04 PM PST 24
Finished Feb 28 04:29:27 PM PST 24
Peak memory 201356 kb
Host smart-e5ab94c5-df0d-4ffe-b710-c3a4e987351d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174205027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4174205027
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3025519563
Short name T219
Test name
Test status
Simulation time 169866100213 ps
CPU time 197.06 seconds
Started Feb 28 04:25:48 PM PST 24
Finished Feb 28 04:29:05 PM PST 24
Peak memory 201372 kb
Host smart-fd858875-c06a-4805-968f-40a2e846079a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025519563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3025519563
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2109044894
Short name T357
Test name
Test status
Simulation time 327539971958 ps
CPU time 187.92 seconds
Started Feb 28 04:25:47 PM PST 24
Finished Feb 28 04:28:55 PM PST 24
Peak memory 201380 kb
Host smart-d64523a3-37f1-4ca7-b942-5f06cd0d65bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109044894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2109044894
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.279270479
Short name T776
Test name
Test status
Simulation time 491482982959 ps
CPU time 615.87 seconds
Started Feb 28 04:25:53 PM PST 24
Finished Feb 28 04:36:09 PM PST 24
Peak memory 201372 kb
Host smart-fd9f9d15-a713-410e-9289-d5ab510386a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279270479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.279270479
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2924283479
Short name T371
Test name
Test status
Simulation time 326349947867 ps
CPU time 201.24 seconds
Started Feb 28 04:25:41 PM PST 24
Finished Feb 28 04:29:03 PM PST 24
Peak memory 201316 kb
Host smart-e9ac8c0a-3ec3-4bee-949e-e13cb1195c72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924283479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2924283479
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2226914658
Short name T749
Test name
Test status
Simulation time 499045539005 ps
CPU time 599.83 seconds
Started Feb 28 04:25:44 PM PST 24
Finished Feb 28 04:35:44 PM PST 24
Peak memory 201288 kb
Host smart-c58a649c-9bda-4fb7-a04f-19122dc2c25a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226914658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2226914658
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3073569166
Short name T636
Test name
Test status
Simulation time 484280608646 ps
CPU time 286.56 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:30:53 PM PST 24
Peak memory 201288 kb
Host smart-bbef915b-006b-4bc1-8a6c-25fc8ab86c7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073569166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3073569166
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4085857148
Short name T606
Test name
Test status
Simulation time 126797241290 ps
CPU time 640.63 seconds
Started Feb 28 04:25:58 PM PST 24
Finished Feb 28 04:36:40 PM PST 24
Peak memory 201708 kb
Host smart-2bc36128-a6b7-4b8b-bc08-fa80073af3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085857148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4085857148
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2217273192
Short name T615
Test name
Test status
Simulation time 30447357132 ps
CPU time 73.81 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:26:56 PM PST 24
Peak memory 201104 kb
Host smart-16cc7b21-4503-44a9-a591-ed94e917415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217273192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2217273192
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2682720331
Short name T337
Test name
Test status
Simulation time 4703343932 ps
CPU time 1.47 seconds
Started Feb 28 04:26:00 PM PST 24
Finished Feb 28 04:26:03 PM PST 24
Peak memory 201292 kb
Host smart-408abb0d-88d9-4c85-998c-24ca80156e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682720331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2682720331
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.874159922
Short name T506
Test name
Test status
Simulation time 5967483785 ps
CPU time 4.7 seconds
Started Feb 28 04:25:48 PM PST 24
Finished Feb 28 04:25:53 PM PST 24
Peak memory 201084 kb
Host smart-fb52b076-89c3-474f-a384-9ae67a71b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874159922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.874159922
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.160371883
Short name T26
Test name
Test status
Simulation time 283788242083 ps
CPU time 484.13 seconds
Started Feb 28 04:25:49 PM PST 24
Finished Feb 28 04:33:54 PM PST 24
Peak memory 209884 kb
Host smart-c22d7332-10f7-44e8-a237-5de6bd60f509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160371883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
160371883
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3483487053
Short name T750
Test name
Test status
Simulation time 83310011145 ps
CPU time 105.38 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:27:44 PM PST 24
Peak memory 210060 kb
Host smart-9a307ab9-564a-4d22-a0b4-ed2929ad2bd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483487053 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3483487053
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2575116812
Short name T377
Test name
Test status
Simulation time 340004421 ps
CPU time 0.95 seconds
Started Feb 28 04:26:09 PM PST 24
Finished Feb 28 04:26:10 PM PST 24
Peak memory 201024 kb
Host smart-d7f2c600-edf5-4b0c-ae3c-bf7336fcda9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575116812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2575116812
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.531888433
Short name T569
Test name
Test status
Simulation time 497791865528 ps
CPU time 160.13 seconds
Started Feb 28 04:26:07 PM PST 24
Finished Feb 28 04:28:48 PM PST 24
Peak memory 201284 kb
Host smart-6ec8f8b6-6f37-4d59-ac0b-1efef1a57251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531888433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.531888433
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.17606809
Short name T396
Test name
Test status
Simulation time 159597703615 ps
CPU time 387.27 seconds
Started Feb 28 04:25:55 PM PST 24
Finished Feb 28 04:32:23 PM PST 24
Peak memory 201248 kb
Host smart-4b15249b-5462-48a9-98c2-54ecf062c1ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt
_fixed.17606809
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.323633614
Short name T658
Test name
Test status
Simulation time 331402779414 ps
CPU time 341.71 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:31:40 PM PST 24
Peak memory 201484 kb
Host smart-4ff5b8ba-1e84-41a9-9b08-edc3b2ef8845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323633614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.323633614
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2524034686
Short name T601
Test name
Test status
Simulation time 168004675279 ps
CPU time 169.52 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:28:56 PM PST 24
Peak memory 201468 kb
Host smart-e32ca8ba-669b-43d1-ab23-1dcfcbb9ceb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524034686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2524034686
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1879062391
Short name T103
Test name
Test status
Simulation time 328581422483 ps
CPU time 364.17 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:31:57 PM PST 24
Peak memory 201320 kb
Host smart-2ccfa219-5440-421a-8cd1-526e2843ed33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879062391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1879062391
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.4164855334
Short name T608
Test name
Test status
Simulation time 169829318783 ps
CPU time 102.9 seconds
Started Feb 28 04:25:56 PM PST 24
Finished Feb 28 04:27:39 PM PST 24
Peak memory 201492 kb
Host smart-5417da4a-48a0-4c92-a2a5-cb6e21107aaf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164855334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.4164855334
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.739187161
Short name T583
Test name
Test status
Simulation time 92546096086 ps
CPU time 295.35 seconds
Started Feb 28 04:25:58 PM PST 24
Finished Feb 28 04:30:55 PM PST 24
Peak memory 201676 kb
Host smart-cc341c42-4e5e-4c40-b7eb-80262cc3bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739187161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.739187161
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1702591215
Short name T515
Test name
Test status
Simulation time 43035243703 ps
CPU time 53.52 seconds
Started Feb 28 04:25:57 PM PST 24
Finished Feb 28 04:26:52 PM PST 24
Peak memory 201260 kb
Host smart-166a5c21-c83c-4e34-ac7b-78b03c786533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702591215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1702591215
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2793473110
Short name T353
Test name
Test status
Simulation time 2712262536 ps
CPU time 7.07 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:26:13 PM PST 24
Peak memory 201124 kb
Host smart-c51811d2-2792-4912-806d-7fc7342eaa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793473110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2793473110
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1698591300
Short name T685
Test name
Test status
Simulation time 6199992798 ps
CPU time 4.36 seconds
Started Feb 28 04:25:54 PM PST 24
Finished Feb 28 04:25:59 PM PST 24
Peak memory 201144 kb
Host smart-03472428-760d-4a79-8362-d35279a43c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698591300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1698591300
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2516034722
Short name T706
Test name
Test status
Simulation time 126406235541 ps
CPU time 555.01 seconds
Started Feb 28 04:25:54 PM PST 24
Finished Feb 28 04:35:10 PM PST 24
Peak memory 201764 kb
Host smart-1e1b6f5b-d547-459b-83c5-a77eeb2a10a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516034722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2516034722
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.784574082
Short name T163
Test name
Test status
Simulation time 93350622450 ps
CPU time 83.23 seconds
Started Feb 28 04:25:43 PM PST 24
Finished Feb 28 04:27:06 PM PST 24
Peak memory 209980 kb
Host smart-9cffd5d7-b0ac-4090-a304-7e1fa64de2c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784574082 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.784574082
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4114164443
Short name T342
Test name
Test status
Simulation time 284901753 ps
CPU time 1.28 seconds
Started Feb 28 04:26:11 PM PST 24
Finished Feb 28 04:26:12 PM PST 24
Peak memory 201100 kb
Host smart-dd477a72-7126-490d-bc1e-0d0a25f54743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114164443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4114164443
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.902467433
Short name T104
Test name
Test status
Simulation time 164236898789 ps
CPU time 133.6 seconds
Started Feb 28 04:25:56 PM PST 24
Finished Feb 28 04:28:10 PM PST 24
Peak memory 201452 kb
Host smart-21d4ec42-0aec-4a5b-b44d-da0e11bd7688
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902467433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.902467433
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2861922110
Short name T237
Test name
Test status
Simulation time 483840073980 ps
CPU time 1174.61 seconds
Started Feb 28 04:26:08 PM PST 24
Finished Feb 28 04:45:43 PM PST 24
Peak memory 201436 kb
Host smart-a180fd70-c48f-4ba7-a22c-1295e6e44fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861922110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2861922110
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.4010864250
Short name T533
Test name
Test status
Simulation time 328460856889 ps
CPU time 780 seconds
Started Feb 28 04:26:03 PM PST 24
Finished Feb 28 04:39:04 PM PST 24
Peak memory 201356 kb
Host smart-e913d5db-290b-4ef8-bb6b-90b8fc6897be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010864250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.4010864250
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3957957209
Short name T573
Test name
Test status
Simulation time 162626238623 ps
CPU time 94.51 seconds
Started Feb 28 04:25:42 PM PST 24
Finished Feb 28 04:27:27 PM PST 24
Peak memory 201428 kb
Host smart-e3b3b7d8-78d5-4dd2-aa41-9ad6c6092159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957957209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3957957209
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.874134736
Short name T531
Test name
Test status
Simulation time 491522452121 ps
CPU time 1139.48 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:45:06 PM PST 24
Peak memory 201400 kb
Host smart-874e0783-eb41-4bd8-a730-cb367f4f0365
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=874134736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.874134736
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1076475862
Short name T257
Test name
Test status
Simulation time 486572029195 ps
CPU time 1120.24 seconds
Started Feb 28 04:26:02 PM PST 24
Finished Feb 28 04:44:43 PM PST 24
Peak memory 201420 kb
Host smart-19c62c83-e02d-4a72-8205-5cb021f8ddc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076475862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1076475862
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1526907927
Short name T493
Test name
Test status
Simulation time 495948287545 ps
CPU time 1008.13 seconds
Started Feb 28 04:26:05 PM PST 24
Finished Feb 28 04:42:54 PM PST 24
Peak memory 201488 kb
Host smart-209caf36-6422-4960-a825-7ec836ec54b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526907927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1526907927
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1854509509
Short name T746
Test name
Test status
Simulation time 104763451352 ps
CPU time 508.91 seconds
Started Feb 28 04:26:08 PM PST 24
Finished Feb 28 04:34:37 PM PST 24
Peak memory 201776 kb
Host smart-1ea5b260-1827-428b-b8ed-07864be29402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854509509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1854509509
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1970713094
Short name T585
Test name
Test status
Simulation time 37117265419 ps
CPU time 23.02 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:26:30 PM PST 24
Peak memory 201120 kb
Host smart-d39ee7f0-29cc-46f1-8430-5f25512c8b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970713094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1970713094
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.4161697429
Short name T441
Test name
Test status
Simulation time 3893206616 ps
CPU time 3.57 seconds
Started Feb 28 04:25:59 PM PST 24
Finished Feb 28 04:26:04 PM PST 24
Peak memory 201108 kb
Host smart-2a190f94-8ea0-4005-8f94-3c3bb7b15911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161697429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4161697429
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2956161693
Short name T451
Test name
Test status
Simulation time 6175433269 ps
CPU time 2.63 seconds
Started Feb 28 04:25:58 PM PST 24
Finished Feb 28 04:26:03 PM PST 24
Peak memory 201132 kb
Host smart-be1e57e1-a908-47aa-8d14-d6c462d148aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956161693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2956161693
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.434143913
Short name T288
Test name
Test status
Simulation time 539350163613 ps
CPU time 1340.71 seconds
Started Feb 28 04:26:00 PM PST 24
Finished Feb 28 04:48:22 PM PST 24
Peak memory 201288 kb
Host smart-83b36c7b-dde2-42c8-a59a-895fd1455446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434143913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
434143913
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1834388700
Short name T358
Test name
Test status
Simulation time 483653142 ps
CPU time 1.15 seconds
Started Feb 28 04:24:48 PM PST 24
Finished Feb 28 04:24:50 PM PST 24
Peak memory 201028 kb
Host smart-02fcaa5a-74d4-4648-a4b9-4704a843ed08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834388700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1834388700
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.516555202
Short name T209
Test name
Test status
Simulation time 168682554322 ps
CPU time 9.11 seconds
Started Feb 28 04:24:39 PM PST 24
Finished Feb 28 04:24:48 PM PST 24
Peak memory 201308 kb
Host smart-2a1cd4dc-a932-4434-81e9-fbbafc10c961
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516555202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.516555202
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1833260484
Short name T102
Test name
Test status
Simulation time 321636666862 ps
CPU time 200.19 seconds
Started Feb 28 04:24:29 PM PST 24
Finished Feb 28 04:27:49 PM PST 24
Peak memory 201460 kb
Host smart-944bac70-04a6-4b5c-9b89-68e577c4d126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833260484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1833260484
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3422543655
Short name T365
Test name
Test status
Simulation time 483244429039 ps
CPU time 310.73 seconds
Started Feb 28 04:25:06 PM PST 24
Finished Feb 28 04:30:17 PM PST 24
Peak memory 201368 kb
Host smart-cb7745eb-46be-40dd-9f1c-49afa4923d6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422543655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3422543655
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.837906106
Short name T303
Test name
Test status
Simulation time 317240573193 ps
CPU time 369.29 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:30:55 PM PST 24
Peak memory 201340 kb
Host smart-2e95a233-4703-4fee-a6fe-95be55ec6c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837906106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.837906106
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3751438131
Short name T564
Test name
Test status
Simulation time 491412845355 ps
CPU time 209.58 seconds
Started Feb 28 04:24:40 PM PST 24
Finished Feb 28 04:28:10 PM PST 24
Peak memory 201452 kb
Host smart-757cfffb-5af0-4441-94cf-0c238f8dffe7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751438131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3751438131
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.584488004
Short name T281
Test name
Test status
Simulation time 165346129302 ps
CPU time 111.71 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:26:52 PM PST 24
Peak memory 201544 kb
Host smart-501c7706-bef2-425e-9ff0-02d02eadba73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584488004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.584488004
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3016387268
Short name T492
Test name
Test status
Simulation time 161771343906 ps
CPU time 87.36 seconds
Started Feb 28 04:24:52 PM PST 24
Finished Feb 28 04:26:20 PM PST 24
Peak memory 201388 kb
Host smart-ac9abdcf-a606-49e2-b177-75f94dc31c3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016387268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3016387268
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.319178763
Short name T173
Test name
Test status
Simulation time 86230992917 ps
CPU time 402.86 seconds
Started Feb 28 04:24:53 PM PST 24
Finished Feb 28 04:31:36 PM PST 24
Peak memory 201640 kb
Host smart-000822aa-9347-427a-b748-5a073e4205a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319178763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.319178763
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3793465948
Short name T335
Test name
Test status
Simulation time 26445428405 ps
CPU time 14.96 seconds
Started Feb 28 04:24:59 PM PST 24
Finished Feb 28 04:25:14 PM PST 24
Peak memory 201196 kb
Host smart-30904510-1ea8-4c5a-8d12-3f2b2dd4acc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793465948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3793465948
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2058504178
Short name T547
Test name
Test status
Simulation time 3287303787 ps
CPU time 4.54 seconds
Started Feb 28 04:24:35 PM PST 24
Finished Feb 28 04:24:40 PM PST 24
Peak memory 201240 kb
Host smart-f8a7cb9a-510d-40ff-a71d-2c767c1ee55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058504178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2058504178
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1032216852
Short name T14
Test name
Test status
Simulation time 7860572377 ps
CPU time 9.94 seconds
Started Feb 28 04:24:48 PM PST 24
Finished Feb 28 04:24:59 PM PST 24
Peak memory 217344 kb
Host smart-2d9dc87f-8a6c-4aad-a0b0-b8842b14f7e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032216852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1032216852
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.109802400
Short name T334
Test name
Test status
Simulation time 5597817187 ps
CPU time 12.48 seconds
Started Feb 28 04:24:51 PM PST 24
Finished Feb 28 04:25:03 PM PST 24
Peak memory 201120 kb
Host smart-e910dba2-a274-4539-a026-60bf6973752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109802400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.109802400
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.11933113
Short name T179
Test name
Test status
Simulation time 627223045283 ps
CPU time 1768.26 seconds
Started Feb 28 04:24:55 PM PST 24
Finished Feb 28 04:54:24 PM PST 24
Peak memory 212432 kb
Host smart-bfb467d1-d09c-4b1f-96b8-ca9a23c7af78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11933113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.11933113
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1898897830
Short name T39
Test name
Test status
Simulation time 251050011889 ps
CPU time 195.11 seconds
Started Feb 28 04:24:46 PM PST 24
Finished Feb 28 04:28:02 PM PST 24
Peak memory 210036 kb
Host smart-f79130fb-6bca-4c85-af72-387b607db043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898897830 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1898897830
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1504006627
Short name T702
Test name
Test status
Simulation time 520269548 ps
CPU time 0.86 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:26:08 PM PST 24
Peak memory 201076 kb
Host smart-85c7385e-3698-4ac5-99a7-a57da62a807f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504006627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1504006627
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.737150155
Short name T726
Test name
Test status
Simulation time 167060665467 ps
CPU time 394.1 seconds
Started Feb 28 04:26:02 PM PST 24
Finished Feb 28 04:32:37 PM PST 24
Peak memory 201348 kb
Host smart-265da8de-5c6e-4380-9247-35ec7574c212
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737150155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.737150155
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.309492543
Short name T691
Test name
Test status
Simulation time 337880479831 ps
CPU time 92.54 seconds
Started Feb 28 04:26:04 PM PST 24
Finished Feb 28 04:27:37 PM PST 24
Peak memory 201384 kb
Host smart-af6e51f6-1c47-4f5d-a623-ab108844ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309492543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.309492543
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2188859735
Short name T669
Test name
Test status
Simulation time 330389474099 ps
CPU time 181.56 seconds
Started Feb 28 04:26:09 PM PST 24
Finished Feb 28 04:29:10 PM PST 24
Peak memory 201488 kb
Host smart-08a403d3-28a1-4b08-890e-84c3d9c0b2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188859735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2188859735
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2063941182
Short name T430
Test name
Test status
Simulation time 510371791000 ps
CPU time 361.24 seconds
Started Feb 28 04:26:05 PM PST 24
Finished Feb 28 04:32:07 PM PST 24
Peak memory 201460 kb
Host smart-4779cc70-ce66-4aa5-9efa-f01f26a1adf1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063941182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2063941182
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1331825468
Short name T309
Test name
Test status
Simulation time 344135164885 ps
CPU time 783.42 seconds
Started Feb 28 04:26:00 PM PST 24
Finished Feb 28 04:39:05 PM PST 24
Peak memory 201468 kb
Host smart-59a9f0f9-f63a-4fd7-b848-acb15f505d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331825468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1331825468
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1066932748
Short name T594
Test name
Test status
Simulation time 488504002809 ps
CPU time 581.94 seconds
Started Feb 28 04:26:05 PM PST 24
Finished Feb 28 04:35:48 PM PST 24
Peak memory 201452 kb
Host smart-ea4b2371-91ed-4060-9338-1bb17b3a4f55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066932748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1066932748
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3875779603
Short name T678
Test name
Test status
Simulation time 325351491142 ps
CPU time 187.52 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:29:14 PM PST 24
Peak memory 201400 kb
Host smart-049a6ab8-914d-49c6-8876-601d2c26db97
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875779603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3875779603
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2396900058
Short name T542
Test name
Test status
Simulation time 131260922230 ps
CPU time 729.75 seconds
Started Feb 28 04:26:00 PM PST 24
Finished Feb 28 04:38:10 PM PST 24
Peak memory 201732 kb
Host smart-1c156774-1c83-4333-9ac3-913dbbdeda60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396900058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2396900058
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4034990764
Short name T762
Test name
Test status
Simulation time 22399836163 ps
CPU time 11.24 seconds
Started Feb 28 04:26:05 PM PST 24
Finished Feb 28 04:26:17 PM PST 24
Peak memory 201204 kb
Host smart-4cd4fd8c-537e-49aa-b900-381018d8b7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034990764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4034990764
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3931200261
Short name T470
Test name
Test status
Simulation time 3331926701 ps
CPU time 8.21 seconds
Started Feb 28 04:26:10 PM PST 24
Finished Feb 28 04:26:18 PM PST 24
Peak memory 201144 kb
Host smart-7e6bcbc9-5404-4343-932d-ed39cd168a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931200261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3931200261
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2133407274
Short name T394
Test name
Test status
Simulation time 5906213127 ps
CPU time 8.04 seconds
Started Feb 28 04:26:03 PM PST 24
Finished Feb 28 04:26:12 PM PST 24
Peak memory 201112 kb
Host smart-88dd83ac-632d-4ecd-ba47-237a33ce5aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133407274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2133407274
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.79680357
Short name T272
Test name
Test status
Simulation time 176504829166 ps
CPU time 25.15 seconds
Started Feb 28 04:25:59 PM PST 24
Finished Feb 28 04:26:25 PM PST 24
Peak memory 201472 kb
Host smart-3491b71d-ef3c-4ed2-9305-e51bbf5edd73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79680357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.79680357
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2635100599
Short name T159
Test name
Test status
Simulation time 15654503402 ps
CPU time 36.31 seconds
Started Feb 28 04:26:05 PM PST 24
Finished Feb 28 04:26:42 PM PST 24
Peak memory 201592 kb
Host smart-902f41be-42a7-4e5e-b1fe-002c13e62255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635100599 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2635100599
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3543135025
Short name T44
Test name
Test status
Simulation time 346235782 ps
CPU time 0.85 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:26:08 PM PST 24
Peak memory 201216 kb
Host smart-60b2a5b4-496f-4836-b9e1-85c8b972a684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543135025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3543135025
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.24691644
Short name T779
Test name
Test status
Simulation time 328504372935 ps
CPU time 381.17 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:32:27 PM PST 24
Peak memory 201304 kb
Host smart-61375250-f7f2-4d75-9c3d-d2e61b709b63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24691644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gatin
g.24691644
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1120195201
Short name T264
Test name
Test status
Simulation time 492397186851 ps
CPU time 582.22 seconds
Started Feb 28 04:25:55 PM PST 24
Finished Feb 28 04:35:37 PM PST 24
Peak memory 201476 kb
Host smart-ebc53ff7-bc40-4195-b1fb-5978cd8b7413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120195201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1120195201
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.340145451
Short name T761
Test name
Test status
Simulation time 165521709822 ps
CPU time 38.81 seconds
Started Feb 28 04:26:00 PM PST 24
Finished Feb 28 04:26:40 PM PST 24
Peak memory 201408 kb
Host smart-ab381e44-bb82-43ad-9535-e2519f43da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340145451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.340145451
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3232274660
Short name T692
Test name
Test status
Simulation time 493578229514 ps
CPU time 1145.39 seconds
Started Feb 28 04:26:01 PM PST 24
Finished Feb 28 04:45:07 PM PST 24
Peak memory 201384 kb
Host smart-925c3426-73ff-4fad-bf1c-6c06fa0a6a83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232274660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3232274660
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1341949168
Short name T295
Test name
Test status
Simulation time 491472226970 ps
CPU time 318.21 seconds
Started Feb 28 04:26:01 PM PST 24
Finished Feb 28 04:31:20 PM PST 24
Peak memory 201568 kb
Host smart-f87afcfd-5954-40e6-8e9b-3f468d62f005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341949168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1341949168
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2575536632
Short name T666
Test name
Test status
Simulation time 163034158324 ps
CPU time 207.62 seconds
Started Feb 28 04:26:03 PM PST 24
Finished Feb 28 04:29:30 PM PST 24
Peak memory 201268 kb
Host smart-b061a5c3-17aa-4423-afe8-eb2fb9ea1784
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575536632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2575536632
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.168118597
Short name T752
Test name
Test status
Simulation time 335018280434 ps
CPU time 370.3 seconds
Started Feb 28 04:26:13 PM PST 24
Finished Feb 28 04:32:24 PM PST 24
Peak memory 201388 kb
Host smart-8532b164-8e24-4e8c-9286-51be1d8aca16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168118597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.168118597
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3743637074
Short name T348
Test name
Test status
Simulation time 165550407270 ps
CPU time 389.75 seconds
Started Feb 28 04:26:04 PM PST 24
Finished Feb 28 04:32:34 PM PST 24
Peak memory 201392 kb
Host smart-188e61c7-eeee-4eee-8027-379984af35e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743637074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3743637074
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.790413635
Short name T674
Test name
Test status
Simulation time 102271642068 ps
CPU time 344.09 seconds
Started Feb 28 04:26:05 PM PST 24
Finished Feb 28 04:31:50 PM PST 24
Peak memory 201588 kb
Host smart-4a62c42e-33e2-4207-ac35-3f0ae44e1434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790413635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.790413635
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2055686695
Short name T495
Test name
Test status
Simulation time 20621161439 ps
CPU time 12.52 seconds
Started Feb 28 04:26:04 PM PST 24
Finished Feb 28 04:26:16 PM PST 24
Peak memory 201124 kb
Host smart-3a58a17c-c055-4eef-bb3f-2614cdcf7345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055686695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2055686695
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1080997824
Short name T397
Test name
Test status
Simulation time 4254675445 ps
CPU time 5.27 seconds
Started Feb 28 04:26:02 PM PST 24
Finished Feb 28 04:26:08 PM PST 24
Peak memory 201188 kb
Host smart-8eaa1bf0-b0de-4e71-a83a-327b9ad3c8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080997824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1080997824
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.561958011
Short name T459
Test name
Test status
Simulation time 5622265183 ps
CPU time 7.37 seconds
Started Feb 28 04:26:09 PM PST 24
Finished Feb 28 04:26:17 PM PST 24
Peak memory 201124 kb
Host smart-2db210cb-ad6b-4608-a028-356692f990b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561958011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.561958011
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2102433919
Short name T426
Test name
Test status
Simulation time 291637590 ps
CPU time 1.28 seconds
Started Feb 28 04:26:11 PM PST 24
Finished Feb 28 04:26:12 PM PST 24
Peak memory 201104 kb
Host smart-9c0f2d68-1b31-42e4-adec-21e213c26ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102433919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2102433919
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1670514183
Short name T117
Test name
Test status
Simulation time 326474086077 ps
CPU time 756.02 seconds
Started Feb 28 04:26:02 PM PST 24
Finished Feb 28 04:38:38 PM PST 24
Peak memory 201496 kb
Host smart-015a4ac9-0bca-4146-999c-29604dc751b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670514183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1670514183
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2527093708
Short name T694
Test name
Test status
Simulation time 336108179596 ps
CPU time 407.59 seconds
Started Feb 28 04:26:14 PM PST 24
Finished Feb 28 04:33:02 PM PST 24
Peak memory 201428 kb
Host smart-432f892d-b62b-4162-80f7-b104d2c6aae7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527093708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2527093708
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4273694915
Short name T131
Test name
Test status
Simulation time 490910970020 ps
CPU time 1096.11 seconds
Started Feb 28 04:26:04 PM PST 24
Finished Feb 28 04:44:21 PM PST 24
Peak memory 201456 kb
Host smart-ccdfad28-67ae-4b8a-aa5e-a7294860561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273694915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4273694915
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.412526060
Short name T715
Test name
Test status
Simulation time 322946240785 ps
CPU time 213.16 seconds
Started Feb 28 04:26:09 PM PST 24
Finished Feb 28 04:29:42 PM PST 24
Peak memory 201308 kb
Host smart-d9225a83-6fac-4f13-a272-d46fdf79f095
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412526060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.412526060
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2588433187
Short name T315
Test name
Test status
Simulation time 171198037942 ps
CPU time 50.64 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:27:09 PM PST 24
Peak memory 201376 kb
Host smart-ab5496d5-f30a-49d0-a6ef-d920d4c706d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588433187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2588433187
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1169427051
Short name T686
Test name
Test status
Simulation time 170043096485 ps
CPU time 263.77 seconds
Started Feb 28 04:26:08 PM PST 24
Finished Feb 28 04:30:32 PM PST 24
Peak memory 201392 kb
Host smart-4a9ef585-a4fd-4641-938f-1070a4287118
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169427051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1169427051
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2603401535
Short name T57
Test name
Test status
Simulation time 34987898808 ps
CPU time 12.35 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:26:30 PM PST 24
Peak memory 201164 kb
Host smart-fbf4f818-1b05-478f-aeeb-f94ed1bfb8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603401535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2603401535
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1408671444
Short name T373
Test name
Test status
Simulation time 2783139944 ps
CPU time 3.9 seconds
Started Feb 28 04:37:08 PM PST 24
Finished Feb 28 04:37:12 PM PST 24
Peak memory 200936 kb
Host smart-e85ebde7-ef7e-468a-9f18-1cc6ae5d46cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408671444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1408671444
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.4064475437
Short name T9
Test name
Test status
Simulation time 5806750446 ps
CPU time 2.73 seconds
Started Feb 28 04:26:06 PM PST 24
Finished Feb 28 04:26:09 PM PST 24
Peak memory 201124 kb
Host smart-d3cc6a70-9292-427c-881d-798c2fe7249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064475437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.4064475437
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1824513466
Short name T709
Test name
Test status
Simulation time 175326284142 ps
CPU time 407.95 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:33:06 PM PST 24
Peak memory 201368 kb
Host smart-73cf0e1a-2955-4252-ab42-a04afa54636d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824513466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1824513466
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2665881915
Short name T651
Test name
Test status
Simulation time 230340578312 ps
CPU time 311.22 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:31:29 PM PST 24
Peak memory 210064 kb
Host smart-690e55ad-fcbd-4524-8144-95c7b634418d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665881915 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2665881915
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2773132026
Short name T597
Test name
Test status
Simulation time 414434820 ps
CPU time 0.81 seconds
Started Feb 28 04:37:08 PM PST 24
Finished Feb 28 04:37:09 PM PST 24
Peak memory 200848 kb
Host smart-ac8826e7-cf1a-4b21-8784-0dc0c20dfe9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773132026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2773132026
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1470541294
Short name T580
Test name
Test status
Simulation time 497268088587 ps
CPU time 318.39 seconds
Started Feb 28 04:26:13 PM PST 24
Finished Feb 28 04:31:32 PM PST 24
Peak memory 201468 kb
Host smart-1909403a-a239-4a45-a7b7-d02dec8e87ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470541294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1470541294
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.726206531
Short name T287
Test name
Test status
Simulation time 162098203252 ps
CPU time 35.91 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:26:54 PM PST 24
Peak memory 201460 kb
Host smart-c16054a0-57d4-4c45-8c50-271e0f7310a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726206531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.726206531
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3393535875
Short name T107
Test name
Test status
Simulation time 495313862519 ps
CPU time 151.09 seconds
Started Feb 28 04:26:05 PM PST 24
Finished Feb 28 04:28:37 PM PST 24
Peak memory 201480 kb
Host smart-c0f79c98-77cf-4191-981a-65b1a62ef183
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393535875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3393535875
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1303507671
Short name T284
Test name
Test status
Simulation time 330501095936 ps
CPU time 748.79 seconds
Started Feb 28 04:26:14 PM PST 24
Finished Feb 28 04:38:43 PM PST 24
Peak memory 201392 kb
Host smart-aac520b4-c114-418c-b147-efa60734500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303507671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1303507671
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2737387559
Short name T429
Test name
Test status
Simulation time 161453741733 ps
CPU time 344.07 seconds
Started Feb 28 04:26:17 PM PST 24
Finished Feb 28 04:32:01 PM PST 24
Peak memory 201360 kb
Host smart-8f6dec5b-2e94-4241-a3ba-d28dc2e42d34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737387559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2737387559
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.706846517
Short name T466
Test name
Test status
Simulation time 165808442817 ps
CPU time 189.12 seconds
Started Feb 28 04:26:13 PM PST 24
Finished Feb 28 04:29:23 PM PST 24
Peak memory 201436 kb
Host smart-523bc5b5-ec88-44bd-a551-a3e2c074da0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706846517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.706846517
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2354147557
Short name T517
Test name
Test status
Simulation time 108380938719 ps
CPU time 525.1 seconds
Started Feb 28 04:26:09 PM PST 24
Finished Feb 28 04:34:55 PM PST 24
Peak memory 201660 kb
Host smart-1b40ec69-8608-4a53-acc5-665e0376f2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354147557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2354147557
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1555695262
Short name T382
Test name
Test status
Simulation time 45499978045 ps
CPU time 98.62 seconds
Started Feb 28 04:34:25 PM PST 24
Finished Feb 28 04:36:04 PM PST 24
Peak memory 201176 kb
Host smart-1d299038-9c36-4f31-a1aa-1c8586a9322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555695262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1555695262
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3433502762
Short name T518
Test name
Test status
Simulation time 3234326604 ps
CPU time 2.62 seconds
Started Feb 28 04:26:08 PM PST 24
Finished Feb 28 04:26:11 PM PST 24
Peak memory 201288 kb
Host smart-417a9d87-8b34-43b3-91f6-f465fde51dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433502762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3433502762
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.70026307
Short name T510
Test name
Test status
Simulation time 5908512427 ps
CPU time 3.88 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:26:22 PM PST 24
Peak memory 201172 kb
Host smart-513fd3e5-558a-4ac3-be0b-66e1322ff1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70026307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.70026307
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3904222325
Short name T505
Test name
Test status
Simulation time 408235686009 ps
CPU time 431.58 seconds
Started Feb 28 04:26:15 PM PST 24
Finished Feb 28 04:33:28 PM PST 24
Peak memory 201680 kb
Host smart-6c11b998-a02b-4a4a-8d9e-a8aa5ee2c982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904222325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3904222325
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.4293049087
Short name T62
Test name
Test status
Simulation time 582150562290 ps
CPU time 252.79 seconds
Started Feb 28 04:26:09 PM PST 24
Finished Feb 28 04:30:22 PM PST 24
Peak memory 217432 kb
Host smart-81ae5338-319b-4c0c-81df-5770438b910a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293049087 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.4293049087
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1415034089
Short name T631
Test name
Test status
Simulation time 379217038 ps
CPU time 1.04 seconds
Started Feb 28 04:26:13 PM PST 24
Finished Feb 28 04:26:14 PM PST 24
Peak memory 201060 kb
Host smart-690fceae-e0e7-44db-89c0-9890845615ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415034089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1415034089
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1033350089
Short name T415
Test name
Test status
Simulation time 334348182051 ps
CPU time 390.98 seconds
Started Feb 28 04:26:09 PM PST 24
Finished Feb 28 04:32:40 PM PST 24
Peak memory 201360 kb
Host smart-f238b1d2-caeb-45b3-b869-1a293ef5b09a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033350089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1033350089
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.426309296
Short name T120
Test name
Test status
Simulation time 489650495996 ps
CPU time 632.14 seconds
Started Feb 28 04:26:10 PM PST 24
Finished Feb 28 04:36:43 PM PST 24
Peak memory 201440 kb
Host smart-f1501da8-41cc-45ac-ad34-11bed0490c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426309296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.426309296
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.796258804
Short name T576
Test name
Test status
Simulation time 486814489444 ps
CPU time 308.29 seconds
Started Feb 28 04:26:16 PM PST 24
Finished Feb 28 04:31:25 PM PST 24
Peak memory 201364 kb
Host smart-657e8c4e-082d-48eb-8492-e31da2590b7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=796258804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.796258804
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3557683938
Short name T269
Test name
Test status
Simulation time 330140046772 ps
CPU time 708.1 seconds
Started Feb 28 04:26:13 PM PST 24
Finished Feb 28 04:38:02 PM PST 24
Peak memory 201368 kb
Host smart-d00b3982-e65c-4854-855e-94e0e2e6db49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557683938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3557683938
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1449917925
Short name T789
Test name
Test status
Simulation time 325964780202 ps
CPU time 675.26 seconds
Started Feb 28 04:26:12 PM PST 24
Finished Feb 28 04:37:28 PM PST 24
Peak memory 201396 kb
Host smart-e2230815-558b-45af-95ff-97cf361b5fa8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449917925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1449917925
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2908441990
Short name T705
Test name
Test status
Simulation time 120703469501 ps
CPU time 579.21 seconds
Started Feb 28 04:26:15 PM PST 24
Finished Feb 28 04:35:55 PM PST 24
Peak memory 201580 kb
Host smart-8ee22092-b58b-4afb-9683-b6a3122a8a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908441990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2908441990
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1710026584
Short name T536
Test name
Test status
Simulation time 45568485137 ps
CPU time 103.26 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:28:02 PM PST 24
Peak memory 201260 kb
Host smart-f3da5ae5-deae-43a4-ac8d-7e426ba6e822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710026584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1710026584
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.104753455
Short name T454
Test name
Test status
Simulation time 5529129247 ps
CPU time 4.1 seconds
Started Feb 28 04:36:52 PM PST 24
Finished Feb 28 04:36:57 PM PST 24
Peak memory 199700 kb
Host smart-e7f7fe93-4438-48e8-80bd-cad3cffd4d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104753455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.104753455
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.830869822
Short name T464
Test name
Test status
Simulation time 5739941415 ps
CPU time 13.34 seconds
Started Feb 28 04:26:11 PM PST 24
Finished Feb 28 04:26:25 PM PST 24
Peak memory 201152 kb
Host smart-df67429a-6dfa-4985-bbad-cbc0741a96d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830869822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.830869822
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.4088870425
Short name T73
Test name
Test status
Simulation time 55095259611 ps
CPU time 118.04 seconds
Started Feb 28 04:26:15 PM PST 24
Finished Feb 28 04:28:14 PM PST 24
Peak memory 201940 kb
Host smart-5cb9afd2-29cf-410d-afad-b0277b077cb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088870425 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.4088870425
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.484135154
Short name T652
Test name
Test status
Simulation time 335105372 ps
CPU time 1.46 seconds
Started Feb 28 04:26:17 PM PST 24
Finished Feb 28 04:26:19 PM PST 24
Peak memory 201224 kb
Host smart-be692982-3db2-4a5e-831d-7b099736e3fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484135154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.484135154
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3100269577
Short name T128
Test name
Test status
Simulation time 339858388827 ps
CPU time 159.96 seconds
Started Feb 28 04:26:12 PM PST 24
Finished Feb 28 04:28:52 PM PST 24
Peak memory 201304 kb
Host smart-a3212174-25ab-4e29-93ab-dfe58c737de5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100269577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3100269577
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.656905393
Short name T730
Test name
Test status
Simulation time 167505934259 ps
CPU time 380.21 seconds
Started Feb 28 04:26:15 PM PST 24
Finished Feb 28 04:32:36 PM PST 24
Peak memory 201552 kb
Host smart-aa7cecda-5e51-462c-a590-5d909bfd32c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656905393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.656905393
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3875755139
Short name T251
Test name
Test status
Simulation time 328036772512 ps
CPU time 747.14 seconds
Started Feb 28 04:26:11 PM PST 24
Finished Feb 28 04:38:39 PM PST 24
Peak memory 201308 kb
Host smart-f4c211a2-ff91-4d1f-b9aa-acc2eefd21bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875755139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3875755139
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.276548679
Short name T522
Test name
Test status
Simulation time 165458729902 ps
CPU time 204.38 seconds
Started Feb 28 04:26:15 PM PST 24
Finished Feb 28 04:29:40 PM PST 24
Peak memory 201404 kb
Host smart-25f7afd4-d445-4ff4-af9c-0b2d05f0b7da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=276548679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.276548679
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3751154083
Short name T735
Test name
Test status
Simulation time 501853780178 ps
CPU time 355.09 seconds
Started Feb 28 04:26:08 PM PST 24
Finished Feb 28 04:32:04 PM PST 24
Peak memory 201372 kb
Host smart-2034f688-ddfc-4fdf-ac51-0cc167056e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751154083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3751154083
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.79566461
Short name T411
Test name
Test status
Simulation time 157921892188 ps
CPU time 374.38 seconds
Started Feb 28 04:26:10 PM PST 24
Finished Feb 28 04:32:25 PM PST 24
Peak memory 201368 kb
Host smart-591f1407-afaa-49ca-a994-c2b5b85b8637
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=79566461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed
.79566461
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2991620259
Short name T627
Test name
Test status
Simulation time 170570541591 ps
CPU time 415.29 seconds
Started Feb 28 04:26:11 PM PST 24
Finished Feb 28 04:33:06 PM PST 24
Peak memory 201384 kb
Host smart-b521ef69-69ae-4a83-a901-d89cc0363125
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991620259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2991620259
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1491919241
Short name T633
Test name
Test status
Simulation time 330964238887 ps
CPU time 795.35 seconds
Started Feb 28 04:26:19 PM PST 24
Finished Feb 28 04:39:35 PM PST 24
Peak memory 201496 kb
Host smart-fb6cf1ed-06e5-4326-8308-0876b2de2e99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491919241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1491919241
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1128714930
Short name T582
Test name
Test status
Simulation time 105199923736 ps
CPU time 519.37 seconds
Started Feb 28 04:26:21 PM PST 24
Finished Feb 28 04:35:01 PM PST 24
Peak memory 201736 kb
Host smart-0e33806b-e8e5-41b7-a2b5-6b499e7d71c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128714930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1128714930
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3292724932
Short name T403
Test name
Test status
Simulation time 44946183583 ps
CPU time 102.16 seconds
Started Feb 28 04:36:52 PM PST 24
Finished Feb 28 04:38:35 PM PST 24
Peak memory 199808 kb
Host smart-7efebc98-bdd7-44b5-a3bd-9d56f3f0401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292724932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3292724932
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2349676175
Short name T368
Test name
Test status
Simulation time 4511999212 ps
CPU time 6.35 seconds
Started Feb 28 04:36:52 PM PST 24
Finished Feb 28 04:36:59 PM PST 24
Peak memory 199496 kb
Host smart-d988107d-f5b8-4f39-be2f-db397ba3ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349676175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2349676175
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1132275707
Short name T414
Test name
Test status
Simulation time 6119437374 ps
CPU time 8.03 seconds
Started Feb 28 04:26:14 PM PST 24
Finished Feb 28 04:26:22 PM PST 24
Peak memory 201160 kb
Host smart-0259fd43-0b9e-428a-94ef-d95c0a2a303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132275707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1132275707
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1387339059
Short name T265
Test name
Test status
Simulation time 533551787135 ps
CPU time 1172.09 seconds
Started Feb 28 04:26:19 PM PST 24
Finished Feb 28 04:45:52 PM PST 24
Peak memory 201404 kb
Host smart-727cbf54-406f-444e-bf46-7a0db8130a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387339059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1387339059
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1054050593
Short name T539
Test name
Test status
Simulation time 412070635 ps
CPU time 1.11 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:26:19 PM PST 24
Peak memory 201096 kb
Host smart-c99a163e-a2a5-42d4-aadc-3cab8bfecad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054050593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1054050593
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.945347034
Short name T254
Test name
Test status
Simulation time 331748320113 ps
CPU time 194.51 seconds
Started Feb 28 04:26:22 PM PST 24
Finished Feb 28 04:29:36 PM PST 24
Peak memory 201500 kb
Host smart-e8da6c9e-1d80-497a-8360-ff891771bdc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945347034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.945347034
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2241518039
Short name T323
Test name
Test status
Simulation time 488979879647 ps
CPU time 590.4 seconds
Started Feb 28 04:26:19 PM PST 24
Finished Feb 28 04:36:10 PM PST 24
Peak memory 201416 kb
Host smart-c866c696-3c33-4084-9b65-ce9025d7e00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241518039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2241518039
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3597445670
Short name T302
Test name
Test status
Simulation time 165345584878 ps
CPU time 239.49 seconds
Started Feb 28 04:26:20 PM PST 24
Finished Feb 28 04:30:20 PM PST 24
Peak memory 201324 kb
Host smart-24a7adca-aab5-4fd4-a23f-2ef735785aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597445670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3597445670
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2537426241
Short name T126
Test name
Test status
Simulation time 483360980117 ps
CPU time 1112.31 seconds
Started Feb 28 04:26:25 PM PST 24
Finished Feb 28 04:44:58 PM PST 24
Peak memory 201384 kb
Host smart-7ecdd837-896e-4422-ae1f-d3f911abf187
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537426241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2537426241
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2925562368
Short name T13
Test name
Test status
Simulation time 169289730648 ps
CPU time 397.64 seconds
Started Feb 28 04:26:16 PM PST 24
Finished Feb 28 04:32:54 PM PST 24
Peak memory 201364 kb
Host smart-3a1a8425-77e5-4ebf-b6f4-9819c0b311e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925562368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2925562368
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3260208462
Short name T1
Test name
Test status
Simulation time 477456348315 ps
CPU time 223.43 seconds
Started Feb 28 04:26:17 PM PST 24
Finished Feb 28 04:30:01 PM PST 24
Peak memory 201384 kb
Host smart-3a8721b2-8e1e-4635-88de-b41f0c50e323
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260208462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3260208462
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1828592889
Short name T291
Test name
Test status
Simulation time 494752258892 ps
CPU time 1153.68 seconds
Started Feb 28 04:26:22 PM PST 24
Finished Feb 28 04:45:36 PM PST 24
Peak memory 201524 kb
Host smart-96b893c2-c938-4e30-bee2-6fb657363e2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828592889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1828592889
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.235017069
Short name T449
Test name
Test status
Simulation time 493168783630 ps
CPU time 280.45 seconds
Started Feb 28 04:26:19 PM PST 24
Finished Feb 28 04:31:00 PM PST 24
Peak memory 201404 kb
Host smart-41ed7bd1-5296-48a6-95e6-5dbaa1c2f2ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235017069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.235017069
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1131044263
Short name T184
Test name
Test status
Simulation time 80613484001 ps
CPU time 322.21 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:31:41 PM PST 24
Peak memory 201796 kb
Host smart-c1b9192a-175c-4dc9-9475-df54df6368ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131044263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1131044263
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1762157551
Short name T497
Test name
Test status
Simulation time 31292105031 ps
CPU time 17.43 seconds
Started Feb 28 04:26:17 PM PST 24
Finished Feb 28 04:26:34 PM PST 24
Peak memory 201160 kb
Host smart-3c163417-2ddf-45f7-bf8c-bf734cc195df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762157551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1762157551
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2615583087
Short name T772
Test name
Test status
Simulation time 5706356934 ps
CPU time 13.16 seconds
Started Feb 28 04:26:17 PM PST 24
Finished Feb 28 04:26:30 PM PST 24
Peak memory 201164 kb
Host smart-e8d96574-13bf-4a67-bf96-9e4a26096ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615583087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2615583087
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3130764237
Short name T491
Test name
Test status
Simulation time 5990255938 ps
CPU time 4.4 seconds
Started Feb 28 04:26:18 PM PST 24
Finished Feb 28 04:26:22 PM PST 24
Peak memory 201148 kb
Host smart-64e18f0c-940c-43f6-999d-388b86918150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130764237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3130764237
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3384668610
Short name T744
Test name
Test status
Simulation time 172878707023 ps
CPU time 174.63 seconds
Started Feb 28 04:36:52 PM PST 24
Finished Feb 28 04:39:48 PM PST 24
Peak memory 199732 kb
Host smart-d461fec6-ad0a-459a-9232-f16cc828e264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384668610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3384668610
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2464349348
Short name T63
Test name
Test status
Simulation time 196674983705 ps
CPU time 231.07 seconds
Started Feb 28 04:26:16 PM PST 24
Finished Feb 28 04:30:08 PM PST 24
Peak memory 201536 kb
Host smart-75d70bae-3af2-4ee5-a258-b343999dbeb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464349348 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2464349348
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3325368193
Short name T427
Test name
Test status
Simulation time 483006673 ps
CPU time 0.81 seconds
Started Feb 28 04:26:25 PM PST 24
Finished Feb 28 04:26:26 PM PST 24
Peak memory 201108 kb
Host smart-0a0972d5-6a85-4dd7-9ea4-d62dff4004d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325368193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3325368193
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.186632281
Short name T325
Test name
Test status
Simulation time 487643518461 ps
CPU time 285.17 seconds
Started Feb 28 04:26:21 PM PST 24
Finished Feb 28 04:31:06 PM PST 24
Peak memory 201476 kb
Host smart-1ea4df91-ed5c-4c1a-bb38-eb928acb9400
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186632281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.186632281
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3117671139
Short name T133
Test name
Test status
Simulation time 489420351088 ps
CPU time 1157.16 seconds
Started Feb 28 04:26:19 PM PST 24
Finished Feb 28 04:45:37 PM PST 24
Peak memory 201484 kb
Host smart-3eafab57-5b36-4dd1-adbe-e290ff3db84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117671139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3117671139
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1540295309
Short name T274
Test name
Test status
Simulation time 325622235945 ps
CPU time 120.97 seconds
Started Feb 28 04:26:24 PM PST 24
Finished Feb 28 04:28:25 PM PST 24
Peak memory 201428 kb
Host smart-7696f6f8-97f1-412f-b7f9-3e6a1e0e0592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540295309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1540295309
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.69011906
Short name T612
Test name
Test status
Simulation time 492772507071 ps
CPU time 396.55 seconds
Started Feb 28 04:26:23 PM PST 24
Finished Feb 28 04:33:00 PM PST 24
Peak memory 201508 kb
Host smart-b11b17b5-7d16-4c1b-99f8-dbdcda8d9f26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=69011906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt
_fixed.69011906
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3443010532
Short name T231
Test name
Test status
Simulation time 159071216487 ps
CPU time 379.09 seconds
Started Feb 28 04:26:20 PM PST 24
Finished Feb 28 04:32:40 PM PST 24
Peak memory 201484 kb
Host smart-21741693-1675-4453-81fb-e54eaa32e2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443010532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3443010532
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3967169568
Short name T483
Test name
Test status
Simulation time 496073677555 ps
CPU time 1249.93 seconds
Started Feb 28 04:26:23 PM PST 24
Finished Feb 28 04:47:13 PM PST 24
Peak memory 201312 kb
Host smart-285b941f-0af7-4e08-820a-0327e8c375e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967169568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3967169568
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2748421746
Short name T224
Test name
Test status
Simulation time 332835742828 ps
CPU time 790.92 seconds
Started Feb 28 04:26:22 PM PST 24
Finished Feb 28 04:39:33 PM PST 24
Peak memory 201396 kb
Host smart-9e3ca44e-b310-47cc-9ae3-1ee96483f5ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748421746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2748421746
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2783969167
Short name T667
Test name
Test status
Simulation time 100699002644 ps
CPU time 554.4 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:35:41 PM PST 24
Peak memory 201632 kb
Host smart-b4f25ce3-d9ef-4f9f-9d7d-8e83659803ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783969167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2783969167
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3836311653
Short name T370
Test name
Test status
Simulation time 30131099934 ps
CPU time 69.79 seconds
Started Feb 28 04:30:35 PM PST 24
Finished Feb 28 04:31:45 PM PST 24
Peak memory 200848 kb
Host smart-1d887caf-dfb5-4a6f-b3ca-1fb9bbd02624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836311653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3836311653
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2137887469
Short name T405
Test name
Test status
Simulation time 4911759820 ps
CPU time 8.21 seconds
Started Feb 28 04:26:28 PM PST 24
Finished Feb 28 04:26:37 PM PST 24
Peak memory 201200 kb
Host smart-50dd4cba-f368-4134-aeb3-3bef63e43f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137887469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2137887469
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1403710870
Short name T422
Test name
Test status
Simulation time 5850619210 ps
CPU time 4.32 seconds
Started Feb 28 04:26:22 PM PST 24
Finished Feb 28 04:26:27 PM PST 24
Peak memory 201120 kb
Host smart-a28038ce-ea80-4f19-9cc6-c1a0501fb33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403710870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1403710870
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1686663809
Short name T584
Test name
Test status
Simulation time 175653410827 ps
CPU time 387.16 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:32:53 PM PST 24
Peak memory 201464 kb
Host smart-1f3c6b13-2b7a-40a4-9b14-03bc7637bc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686663809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1686663809
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3910515329
Short name T162
Test name
Test status
Simulation time 214433102495 ps
CPU time 151.94 seconds
Started Feb 28 04:26:25 PM PST 24
Finished Feb 28 04:28:57 PM PST 24
Peak memory 210092 kb
Host smart-9aae0c35-6899-4527-8162-0c64a0b8b182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910515329 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3910515329
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4109478713
Short name T587
Test name
Test status
Simulation time 409180766 ps
CPU time 1.52 seconds
Started Feb 28 04:30:36 PM PST 24
Finished Feb 28 04:30:39 PM PST 24
Peak memory 201028 kb
Host smart-e9fcaa61-4edd-47ad-a018-a11e215927dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109478713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4109478713
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3040286337
Short name T308
Test name
Test status
Simulation time 328520895151 ps
CPU time 829.05 seconds
Started Feb 28 04:30:35 PM PST 24
Finished Feb 28 04:44:25 PM PST 24
Peak memory 201084 kb
Host smart-7f9cc740-57a5-45fc-9adc-c480d14aa69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040286337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3040286337
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2158595767
Short name T588
Test name
Test status
Simulation time 327997992148 ps
CPU time 361.06 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:32:28 PM PST 24
Peak memory 201252 kb
Host smart-6484039f-d435-4b41-95b9-41be0dd23f0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158595767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2158595767
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3275711123
Short name T457
Test name
Test status
Simulation time 322245633374 ps
CPU time 410.24 seconds
Started Feb 28 04:26:25 PM PST 24
Finished Feb 28 04:33:15 PM PST 24
Peak memory 201452 kb
Host smart-a2b4848f-5160-4db9-810b-558be4861b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275711123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3275711123
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.4138806462
Short name T6
Test name
Test status
Simulation time 164628071407 ps
CPU time 189.78 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:29:35 PM PST 24
Peak memory 201416 kb
Host smart-d8cc873b-ea2d-420e-881e-105f6efacd6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138806462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.4138806462
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2468403732
Short name T425
Test name
Test status
Simulation time 330073116958 ps
CPU time 205.05 seconds
Started Feb 28 04:26:27 PM PST 24
Finished Feb 28 04:29:52 PM PST 24
Peak memory 201396 kb
Host smart-b4389992-6435-4ae4-a867-c364b7d464d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468403732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2468403732
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.866191378
Short name T552
Test name
Test status
Simulation time 91724250221 ps
CPU time 484.83 seconds
Started Feb 28 04:26:30 PM PST 24
Finished Feb 28 04:34:36 PM PST 24
Peak memory 201816 kb
Host smart-b422d112-3af6-41ad-8a77-1d2f8c7fc7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866191378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.866191378
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2518234030
Short name T355
Test name
Test status
Simulation time 43448398261 ps
CPU time 52.3 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 201264 kb
Host smart-e9f80686-d0fd-4eab-8190-42015cfcc63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518234030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2518234030
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1128042249
Short name T622
Test name
Test status
Simulation time 4149580330 ps
CPU time 3.3 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:26:29 PM PST 24
Peak memory 201168 kb
Host smart-f18980dc-bea3-4405-a8f6-732b6549da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128042249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1128042249
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.4100188910
Short name T440
Test name
Test status
Simulation time 6022143860 ps
CPU time 14.38 seconds
Started Feb 28 04:26:28 PM PST 24
Finished Feb 28 04:26:43 PM PST 24
Peak memory 201128 kb
Host smart-8fbcb023-687b-43a1-b133-cd9bd23231b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100188910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.4100188910
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.534679662
Short name T232
Test name
Test status
Simulation time 328904297442 ps
CPU time 772.6 seconds
Started Feb 28 04:26:29 PM PST 24
Finished Feb 28 04:39:22 PM PST 24
Peak memory 201388 kb
Host smart-c2b942c6-69cc-4f25-90ce-e9591ce2d075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534679662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
534679662
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2065307068
Short name T160
Test name
Test status
Simulation time 143253047874 ps
CPU time 133.99 seconds
Started Feb 28 04:26:29 PM PST 24
Finished Feb 28 04:28:45 PM PST 24
Peak memory 209828 kb
Host smart-4230870b-2c38-44f3-993d-c1ca5d6ad1e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065307068 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2065307068
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2471626325
Short name T45
Test name
Test status
Simulation time 482948725 ps
CPU time 0.95 seconds
Started Feb 28 04:26:30 PM PST 24
Finished Feb 28 04:26:33 PM PST 24
Peak memory 201172 kb
Host smart-83083d9b-cc93-4558-8b71-556244b1a4b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471626325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2471626325
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.178545590
Short name T192
Test name
Test status
Simulation time 492291407946 ps
CPU time 755.77 seconds
Started Feb 28 04:26:30 PM PST 24
Finished Feb 28 04:39:08 PM PST 24
Peak memory 201328 kb
Host smart-857714c6-f244-4383-9b9d-32eca8107657
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178545590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.178545590
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2166711813
Short name T320
Test name
Test status
Simulation time 337085940199 ps
CPU time 565.37 seconds
Started Feb 28 04:26:36 PM PST 24
Finished Feb 28 04:36:02 PM PST 24
Peak memory 201244 kb
Host smart-871b4863-f468-41f7-9a7f-414d9020c811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166711813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2166711813
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2787174354
Short name T487
Test name
Test status
Simulation time 165024280492 ps
CPU time 102.51 seconds
Started Feb 28 04:26:27 PM PST 24
Finished Feb 28 04:28:10 PM PST 24
Peak memory 201368 kb
Host smart-5a2e5edc-efe0-479d-8134-68febb79aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787174354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2787174354
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.720933162
Short name T221
Test name
Test status
Simulation time 164080582742 ps
CPU time 251.29 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:30:37 PM PST 24
Peak memory 201280 kb
Host smart-959b9852-fa7c-4bdd-8b9e-150bb471be9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=720933162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.720933162
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2473752915
Short name T56
Test name
Test status
Simulation time 504640529389 ps
CPU time 635.13 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:37:01 PM PST 24
Peak memory 201408 kb
Host smart-2a039b65-d430-4f6d-9d00-39dbdd5b3d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473752915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2473752915
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1908613243
Short name T452
Test name
Test status
Simulation time 487543643062 ps
CPU time 264.66 seconds
Started Feb 28 04:26:28 PM PST 24
Finished Feb 28 04:30:53 PM PST 24
Peak memory 201348 kb
Host smart-096b0828-d042-4236-bc3d-002f632eafde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908613243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1908613243
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2224506773
Short name T147
Test name
Test status
Simulation time 487310270825 ps
CPU time 292.12 seconds
Started Feb 28 04:30:36 PM PST 24
Finished Feb 28 04:35:30 PM PST 24
Peak memory 201340 kb
Host smart-ea84b3e1-8271-466d-b801-436ebc696ab7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224506773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2224506773
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.648038963
Short name T605
Test name
Test status
Simulation time 493709578678 ps
CPU time 272.74 seconds
Started Feb 28 04:26:27 PM PST 24
Finished Feb 28 04:31:00 PM PST 24
Peak memory 201392 kb
Host smart-a8d391c6-f916-4033-9cbb-5fa4feb9a491
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648038963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.648038963
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2388443820
Short name T191
Test name
Test status
Simulation time 86600456691 ps
CPU time 306.42 seconds
Started Feb 28 04:26:29 PM PST 24
Finished Feb 28 04:31:37 PM PST 24
Peak memory 201708 kb
Host smart-62939011-36a3-4d53-a3e5-974f82f74b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388443820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2388443820
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1480932918
Short name T417
Test name
Test status
Simulation time 28216822989 ps
CPU time 64.66 seconds
Started Feb 28 04:26:32 PM PST 24
Finished Feb 28 04:27:37 PM PST 24
Peak memory 201060 kb
Host smart-61b423f1-2fc4-4eac-8d11-ff363b96a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480932918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1480932918
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3715501074
Short name T523
Test name
Test status
Simulation time 3526332147 ps
CPU time 3.63 seconds
Started Feb 28 04:26:31 PM PST 24
Finished Feb 28 04:26:35 PM PST 24
Peak memory 201240 kb
Host smart-08fed28a-052a-4f29-8d6a-6027bb97d0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715501074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3715501074
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2730393085
Short name T727
Test name
Test status
Simulation time 5681597381 ps
CPU time 4.22 seconds
Started Feb 28 04:26:26 PM PST 24
Finished Feb 28 04:26:30 PM PST 24
Peak memory 201084 kb
Host smart-ce733266-ae6a-42f2-8a7d-9f1c1d0a34c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730393085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2730393085
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2513079856
Short name T169
Test name
Test status
Simulation time 106957879873 ps
CPU time 560.51 seconds
Started Feb 28 04:26:29 PM PST 24
Finished Feb 28 04:35:50 PM PST 24
Peak memory 201712 kb
Host smart-436b0087-b161-439d-8a55-28229df42a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513079856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2513079856
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3568567650
Short name T592
Test name
Test status
Simulation time 21161559917 ps
CPU time 50.72 seconds
Started Feb 28 04:26:36 PM PST 24
Finished Feb 28 04:27:27 PM PST 24
Peak memory 209468 kb
Host smart-2f2fdd33-4669-4516-9b39-d34b57ddf1b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568567650 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3568567650
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2635480245
Short name T434
Test name
Test status
Simulation time 360085936 ps
CPU time 0.71 seconds
Started Feb 28 04:25:04 PM PST 24
Finished Feb 28 04:25:05 PM PST 24
Peak memory 201120 kb
Host smart-bb116eb6-ad7f-4700-9ff2-941a97d3eb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635480245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2635480245
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3079025194
Short name T754
Test name
Test status
Simulation time 162399805638 ps
CPU time 178.67 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:28:12 PM PST 24
Peak memory 201412 kb
Host smart-ba0536a7-0669-4c34-aa84-f4b9f493c607
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079025194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3079025194
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3178662038
Short name T473
Test name
Test status
Simulation time 167532877877 ps
CPU time 119.66 seconds
Started Feb 28 04:24:56 PM PST 24
Finished Feb 28 04:26:56 PM PST 24
Peak memory 201460 kb
Host smart-3980a1b0-ab5c-46f9-9a4b-58ea3b7ade13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178662038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3178662038
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3819782809
Short name T212
Test name
Test status
Simulation time 164871305878 ps
CPU time 37.3 seconds
Started Feb 28 04:24:50 PM PST 24
Finished Feb 28 04:25:28 PM PST 24
Peak memory 201480 kb
Host smart-0f74dd0e-6e8d-40ff-8deb-d279b0f9fe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819782809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3819782809
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3340466778
Short name T671
Test name
Test status
Simulation time 334961786353 ps
CPU time 199.27 seconds
Started Feb 28 04:24:36 PM PST 24
Finished Feb 28 04:27:56 PM PST 24
Peak memory 201460 kb
Host smart-7fac537d-93b2-4d01-9f0b-efc7eb317b4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340466778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3340466778
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3014136020
Short name T114
Test name
Test status
Simulation time 490895125469 ps
CPU time 287.58 seconds
Started Feb 28 04:24:37 PM PST 24
Finished Feb 28 04:29:25 PM PST 24
Peak memory 201396 kb
Host smart-09c42990-9495-4861-bd96-63e059a5174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014136020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3014136020
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1349383943
Short name T419
Test name
Test status
Simulation time 495538126867 ps
CPU time 68.21 seconds
Started Feb 28 04:24:46 PM PST 24
Finished Feb 28 04:25:54 PM PST 24
Peak memory 201384 kb
Host smart-e49493da-5cd4-4be7-87c5-fa79501c68b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349383943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1349383943
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1489112137
Short name T301
Test name
Test status
Simulation time 495497549444 ps
CPU time 1117.85 seconds
Started Feb 28 04:25:08 PM PST 24
Finished Feb 28 04:43:46 PM PST 24
Peak memory 201480 kb
Host smart-e99ad6fc-1d39-4a6a-af84-366fbe18b87b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489112137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1489112137
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.290623122
Short name T19
Test name
Test status
Simulation time 486124350267 ps
CPU time 565.89 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:34:11 PM PST 24
Peak memory 201536 kb
Host smart-f2c17512-1cdc-401e-a4f1-bccdd1470944
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290623122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.290623122
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1387940030
Short name T554
Test name
Test status
Simulation time 99726568826 ps
CPU time 378.47 seconds
Started Feb 28 04:24:51 PM PST 24
Finished Feb 28 04:31:10 PM PST 24
Peak memory 201604 kb
Host smart-12b367a3-998c-467e-b4f3-86dd4300e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387940030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1387940030
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.94623380
Short name T391
Test name
Test status
Simulation time 36714803465 ps
CPU time 43.4 seconds
Started Feb 28 04:24:48 PM PST 24
Finished Feb 28 04:25:33 PM PST 24
Peak memory 201148 kb
Host smart-92f07a3a-2cbd-4ff7-a19b-e217f80d719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94623380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.94623380
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3537289464
Short name T22
Test name
Test status
Simulation time 5088887149 ps
CPU time 10.67 seconds
Started Feb 28 04:24:50 PM PST 24
Finished Feb 28 04:25:01 PM PST 24
Peak memory 201160 kb
Host smart-204de7c4-4e57-4479-ad44-c09a94eae936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537289464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3537289464
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1650096986
Short name T390
Test name
Test status
Simulation time 6059791110 ps
CPU time 13.95 seconds
Started Feb 28 04:24:53 PM PST 24
Finished Feb 28 04:25:07 PM PST 24
Peak memory 201168 kb
Host smart-ad62be11-4531-42ce-90b6-9eac6750e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650096986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1650096986
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2170582692
Short name T30
Test name
Test status
Simulation time 327149509743 ps
CPU time 176.4 seconds
Started Feb 28 04:24:56 PM PST 24
Finished Feb 28 04:27:53 PM PST 24
Peak memory 210024 kb
Host smart-b9748e1a-e8ca-4749-8dca-f4a063f20d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170582692 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2170582692
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3296803001
Short name T359
Test name
Test status
Simulation time 353773379 ps
CPU time 1.49 seconds
Started Feb 28 04:24:47 PM PST 24
Finished Feb 28 04:24:49 PM PST 24
Peak memory 201052 kb
Host smart-4b3347af-fa7a-4b4a-9813-0c2e4f2d5138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296803001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3296803001
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1368966665
Short name T154
Test name
Test status
Simulation time 487765162839 ps
CPU time 568.8 seconds
Started Feb 28 04:24:44 PM PST 24
Finished Feb 28 04:34:13 PM PST 24
Peak memory 201356 kb
Host smart-b59d9edc-992f-43be-b27a-8390ec81039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368966665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1368966665
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1076243794
Short name T560
Test name
Test status
Simulation time 327365834012 ps
CPU time 827.77 seconds
Started Feb 28 04:24:51 PM PST 24
Finished Feb 28 04:38:39 PM PST 24
Peak memory 201360 kb
Host smart-cd01adfa-4338-45f1-95a5-804ea5e37386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076243794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1076243794
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2368996494
Short name T292
Test name
Test status
Simulation time 164086493939 ps
CPU time 94.22 seconds
Started Feb 28 04:24:52 PM PST 24
Finished Feb 28 04:26:27 PM PST 24
Peak memory 201404 kb
Host smart-4fc98fd6-d001-44bb-be63-f4016aac3801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368996494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2368996494
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3342339975
Short name T409
Test name
Test status
Simulation time 323039951544 ps
CPU time 708.72 seconds
Started Feb 28 04:24:55 PM PST 24
Finished Feb 28 04:36:44 PM PST 24
Peak memory 201280 kb
Host smart-cf83323d-e049-4078-a56c-bd7ea06f1982
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342339975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3342339975
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1343415388
Short name T270
Test name
Test status
Simulation time 507845663187 ps
CPU time 631.18 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:35:31 PM PST 24
Peak memory 201336 kb
Host smart-d7ed2e58-ac4c-455a-b33d-793556c4f01b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343415388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1343415388
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.739388575
Short name T641
Test name
Test status
Simulation time 166998592535 ps
CPU time 44.12 seconds
Started Feb 28 04:24:38 PM PST 24
Finished Feb 28 04:25:23 PM PST 24
Peak memory 201404 kb
Host smart-d2f9a30b-2c66-4c5c-b6d1-555627264511
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739388575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.739388575
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3461627033
Short name T634
Test name
Test status
Simulation time 91338778780 ps
CPU time 473.3 seconds
Started Feb 28 04:25:03 PM PST 24
Finished Feb 28 04:32:56 PM PST 24
Peak memory 201768 kb
Host smart-2a44e477-4137-43ed-b164-86bcca9a86e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461627033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3461627033
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3180179948
Short name T494
Test name
Test status
Simulation time 22936619033 ps
CPU time 55.42 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:25:41 PM PST 24
Peak memory 201200 kb
Host smart-8f50ec6c-9fed-4fe1-abe1-79e513e2b640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180179948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3180179948
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.111932141
Short name T768
Test name
Test status
Simulation time 3528220006 ps
CPU time 2.7 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:25:00 PM PST 24
Peak memory 201112 kb
Host smart-dfb7e303-864b-4dd3-91ca-e2b4a8868f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111932141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.111932141
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3155868282
Short name T561
Test name
Test status
Simulation time 5827204646 ps
CPU time 3.77 seconds
Started Feb 28 04:24:51 PM PST 24
Finished Feb 28 04:24:56 PM PST 24
Peak memory 201172 kb
Host smart-ba94f014-3f59-4595-8411-c8626797f89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155868282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3155868282
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.277984156
Short name T385
Test name
Test status
Simulation time 310919488 ps
CPU time 0.91 seconds
Started Feb 28 04:24:47 PM PST 24
Finished Feb 28 04:24:49 PM PST 24
Peak memory 201204 kb
Host smart-6618675b-813d-48e8-addd-61ced564637d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277984156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.277984156
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.111500032
Short name T771
Test name
Test status
Simulation time 334592615828 ps
CPU time 799.81 seconds
Started Feb 28 04:25:04 PM PST 24
Finished Feb 28 04:38:24 PM PST 24
Peak memory 201364 kb
Host smart-c9c3ae6e-7cf3-4eb8-a833-caec1f4ea6e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111500032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.111500032
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.4051617720
Short name T535
Test name
Test status
Simulation time 158945273253 ps
CPU time 101.9 seconds
Started Feb 28 04:24:49 PM PST 24
Finished Feb 28 04:26:31 PM PST 24
Peak memory 201452 kb
Host smart-f5625d4c-3626-47c9-b7f1-c381f153ed05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051617720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.4051617720
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.908195606
Short name T712
Test name
Test status
Simulation time 164402908881 ps
CPU time 363.97 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:30:49 PM PST 24
Peak memory 201384 kb
Host smart-878ec4ac-030c-4c01-80e8-356d3ad6057a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=908195606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.908195606
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2683227197
Short name T115
Test name
Test status
Simulation time 326716215142 ps
CPU time 133.32 seconds
Started Feb 28 04:24:50 PM PST 24
Finished Feb 28 04:27:03 PM PST 24
Peak memory 201316 kb
Host smart-9463d93a-8d1a-43a6-a838-f0012751d1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683227197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2683227197
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1542029207
Short name T581
Test name
Test status
Simulation time 161563021383 ps
CPU time 34.87 seconds
Started Feb 28 04:24:34 PM PST 24
Finished Feb 28 04:25:10 PM PST 24
Peak memory 201428 kb
Host smart-8bd8cc38-6ec6-4e5a-9161-9c62db9bbdd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542029207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1542029207
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.274235084
Short name T642
Test name
Test status
Simulation time 340590284337 ps
CPU time 806.7 seconds
Started Feb 28 04:25:14 PM PST 24
Finished Feb 28 04:38:40 PM PST 24
Peak memory 201420 kb
Host smart-e46f139f-16f7-4278-a72e-dddd917b16ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274235084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.274235084
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1221259375
Short name T380
Test name
Test status
Simulation time 161183724574 ps
CPU time 189.4 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:28:07 PM PST 24
Peak memory 201356 kb
Host smart-60776477-27d1-40f7-a1ac-49032bb11d5d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221259375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1221259375
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.386633015
Short name T532
Test name
Test status
Simulation time 118275139743 ps
CPU time 575.98 seconds
Started Feb 28 04:24:54 PM PST 24
Finished Feb 28 04:34:31 PM PST 24
Peak memory 201636 kb
Host smart-e2cabfc2-3b07-41d8-8a52-6c88ce2d5b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386633015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.386633015
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4218374275
Short name T508
Test name
Test status
Simulation time 32137994628 ps
CPU time 16.14 seconds
Started Feb 28 04:24:59 PM PST 24
Finished Feb 28 04:25:15 PM PST 24
Peak memory 201184 kb
Host smart-0c3c7e5d-08b7-449a-9ea3-ae1042bdd904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218374275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4218374275
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3079292772
Short name T360
Test name
Test status
Simulation time 3227602211 ps
CPU time 4.29 seconds
Started Feb 28 04:24:48 PM PST 24
Finished Feb 28 04:24:53 PM PST 24
Peak memory 201216 kb
Host smart-f1b27119-1544-4f44-9647-cc51c376e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079292772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3079292772
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.13270768
Short name T707
Test name
Test status
Simulation time 5793034334 ps
CPU time 2.32 seconds
Started Feb 28 04:24:51 PM PST 24
Finished Feb 28 04:24:53 PM PST 24
Peak memory 201108 kb
Host smart-26fe63d8-c293-438a-8f3a-a91e1e43a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13270768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.13270768
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2811588043
Short name T447
Test name
Test status
Simulation time 362343193121 ps
CPU time 411.6 seconds
Started Feb 28 04:25:01 PM PST 24
Finished Feb 28 04:31:53 PM PST 24
Peak memory 201324 kb
Host smart-af92806f-ddbe-4c5a-9a9d-66d0058d3919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811588043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2811588043
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1242728207
Short name T593
Test name
Test status
Simulation time 507491407 ps
CPU time 1.69 seconds
Started Feb 28 04:24:49 PM PST 24
Finished Feb 28 04:24:51 PM PST 24
Peak memory 201100 kb
Host smart-bcc71037-3469-4674-a9d7-cd51649d25b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242728207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1242728207
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3484585356
Short name T150
Test name
Test status
Simulation time 491867046744 ps
CPU time 280.28 seconds
Started Feb 28 04:24:49 PM PST 24
Finished Feb 28 04:29:30 PM PST 24
Peak memory 201440 kb
Host smart-815065c4-970c-42ff-a502-04b4e7ce73b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484585356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3484585356
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2962341737
Short name T626
Test name
Test status
Simulation time 488805300153 ps
CPU time 384.96 seconds
Started Feb 28 04:24:53 PM PST 24
Finished Feb 28 04:31:18 PM PST 24
Peak memory 201392 kb
Host smart-2309bc59-e72a-4ccc-ba36-c1d1e0ce39d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962341737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2962341737
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3051540735
Short name T664
Test name
Test status
Simulation time 320389719046 ps
CPU time 734.59 seconds
Started Feb 28 04:24:55 PM PST 24
Finished Feb 28 04:37:10 PM PST 24
Peak memory 201440 kb
Host smart-749109df-7887-43eb-a820-46ae154b0efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051540735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3051540735
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2772074354
Short name T467
Test name
Test status
Simulation time 162013617770 ps
CPU time 107.36 seconds
Started Feb 28 04:24:43 PM PST 24
Finished Feb 28 04:26:31 PM PST 24
Peak memory 201412 kb
Host smart-6b95eb64-f132-4ef9-b76d-f500f92fdb3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772074354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2772074354
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.854440635
Short name T665
Test name
Test status
Simulation time 494389158892 ps
CPU time 1122.79 seconds
Started Feb 28 04:24:47 PM PST 24
Finished Feb 28 04:43:30 PM PST 24
Peak memory 201388 kb
Host smart-77d85617-84b3-4b33-b95e-4e9e017acb64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854440635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.854440635
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1346828334
Short name T551
Test name
Test status
Simulation time 83402271810 ps
CPU time 364.51 seconds
Started Feb 28 04:24:55 PM PST 24
Finished Feb 28 04:31:00 PM PST 24
Peak memory 201676 kb
Host smart-74f6b9b9-f670-4daf-89fb-018ace60cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346828334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1346828334
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3216708021
Short name T336
Test name
Test status
Simulation time 41363219973 ps
CPU time 44.41 seconds
Started Feb 28 04:24:51 PM PST 24
Finished Feb 28 04:25:36 PM PST 24
Peak memory 201128 kb
Host smart-dc15ba4f-f9dc-4e36-946b-d4da9310e578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216708021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3216708021
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2906139778
Short name T364
Test name
Test status
Simulation time 4931468676 ps
CPU time 6.71 seconds
Started Feb 28 04:24:59 PM PST 24
Finished Feb 28 04:25:06 PM PST 24
Peak memory 201164 kb
Host smart-1e6f6b4a-8dc1-4f01-b2bc-940a64c7a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906139778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2906139778
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2703469792
Short name T331
Test name
Test status
Simulation time 5727543619 ps
CPU time 14.66 seconds
Started Feb 28 04:24:45 PM PST 24
Finished Feb 28 04:25:00 PM PST 24
Peak memory 201068 kb
Host smart-909db700-36df-448f-b7bf-9ebb2df5f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703469792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2703469792
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2258044944
Short name T312
Test name
Test status
Simulation time 174735995650 ps
CPU time 432.21 seconds
Started Feb 28 04:25:04 PM PST 24
Finished Feb 28 04:32:17 PM PST 24
Peak memory 201412 kb
Host smart-5366c2eb-f810-4a19-ac19-678226d147e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258044944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2258044944
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1923809886
Short name T234
Test name
Test status
Simulation time 321456448718 ps
CPU time 256.2 seconds
Started Feb 28 04:24:51 PM PST 24
Finished Feb 28 04:29:08 PM PST 24
Peak memory 210008 kb
Host smart-29f9bb89-87bb-473b-9f54-5ee79a2a3821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923809886 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1923809886
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2547864728
Short name T399
Test name
Test status
Simulation time 428254925 ps
CPU time 0.83 seconds
Started Feb 28 04:25:10 PM PST 24
Finished Feb 28 04:25:11 PM PST 24
Peak memory 201108 kb
Host smart-b1ca9717-1a03-4312-94e4-f93a4cd7944d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547864728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2547864728
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.188971411
Short name T282
Test name
Test status
Simulation time 511528404826 ps
CPU time 828.38 seconds
Started Feb 28 04:25:00 PM PST 24
Finished Feb 28 04:38:49 PM PST 24
Peak memory 201404 kb
Host smart-8ec2d687-4c39-4016-a3f8-9251bd1b1478
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188971411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.188971411
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2600564904
Short name T156
Test name
Test status
Simulation time 336508008164 ps
CPU time 367.14 seconds
Started Feb 28 04:25:03 PM PST 24
Finished Feb 28 04:31:11 PM PST 24
Peak memory 201388 kb
Host smart-d94176d6-f119-4b42-bf34-08fdb331f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600564904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2600564904
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1680132995
Short name T769
Test name
Test status
Simulation time 165164704215 ps
CPU time 106.86 seconds
Started Feb 28 04:24:48 PM PST 24
Finished Feb 28 04:26:35 PM PST 24
Peak memory 201352 kb
Host smart-9425db2e-3c09-4f9e-b5dc-753bf47f1492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680132995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1680132995
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2623750557
Short name T543
Test name
Test status
Simulation time 325240932547 ps
CPU time 187.03 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:28:12 PM PST 24
Peak memory 201404 kb
Host smart-2d4ce652-f6d6-499a-ac57-359bd3efb720
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623750557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2623750557
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.279521168
Short name T783
Test name
Test status
Simulation time 489236124269 ps
CPU time 542.78 seconds
Started Feb 28 04:25:01 PM PST 24
Finished Feb 28 04:34:04 PM PST 24
Peak memory 201404 kb
Host smart-27e1a0b2-c8ca-4685-b8e1-4e7b9e8dd782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279521168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.279521168
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.230432591
Short name T408
Test name
Test status
Simulation time 488117910203 ps
CPU time 264.48 seconds
Started Feb 28 04:25:08 PM PST 24
Finished Feb 28 04:29:33 PM PST 24
Peak memory 201312 kb
Host smart-a1b7a8ce-493e-4f3a-bb1b-b1d905c62a77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=230432591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.230432591
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2934215652
Short name T109
Test name
Test status
Simulation time 163164366886 ps
CPU time 23 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:25:36 PM PST 24
Peak memory 201340 kb
Host smart-576a1ba0-d9b2-4b22-b953-e91909467a71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934215652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2934215652
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4076825454
Short name T182
Test name
Test status
Simulation time 108855005548 ps
CPU time 428.78 seconds
Started Feb 28 04:25:13 PM PST 24
Finished Feb 28 04:32:22 PM PST 24
Peak memory 201744 kb
Host smart-ebeb461c-acf6-4943-9eb3-821d0bb179a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076825454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4076825454
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3370796328
Short name T716
Test name
Test status
Simulation time 43524378844 ps
CPU time 34.56 seconds
Started Feb 28 04:25:20 PM PST 24
Finished Feb 28 04:25:55 PM PST 24
Peak memory 201268 kb
Host smart-759d1628-afff-4664-b838-4441c7ee8486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370796328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3370796328
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2711898899
Short name T676
Test name
Test status
Simulation time 5335795965 ps
CPU time 13.45 seconds
Started Feb 28 04:24:57 PM PST 24
Finished Feb 28 04:25:11 PM PST 24
Peak memory 201200 kb
Host smart-4168408d-22aa-435d-b3cd-3533400e245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711898899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2711898899
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3689894616
Short name T461
Test name
Test status
Simulation time 5703821224 ps
CPU time 1.7 seconds
Started Feb 28 04:24:48 PM PST 24
Finished Feb 28 04:24:51 PM PST 24
Peak memory 201192 kb
Host smart-95e0daea-65cb-48f8-968f-2f9eb7703c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689894616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3689894616
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.887135969
Short name T513
Test name
Test status
Simulation time 170882857012 ps
CPU time 60.72 seconds
Started Feb 28 04:25:05 PM PST 24
Finished Feb 28 04:26:06 PM PST 24
Peak memory 201256 kb
Host smart-c2dcf775-04bf-4f37-9e5b-cdf841c5afec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887135969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.887135969
Directory /workspace/9.adc_ctrl_stress_all/latest
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