Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6584	1			T3	20		T8	64		T9	48
testmodes[AdcCtrlTestmodeNormal]	5258	1			T2	2		T5	3		T8	61
testmodes[AdcCtrlTestmodeLowpower]	5315	1			T1	2		T4	3		T6	17
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3522	1			T3	19		T8	24		T9	12
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1685	1			T8	12		T9	16		T18	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1268	1			T8	28		T9	19		T18	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1678	1			T8	17		T9	18		T18	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1940	1			T2	1		T5	2		T8	22
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1304	1			T8	22		T9	13		T18	8
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1279	1			T8	23		T9	18		T18	8
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1289	1			T8	27		T9	14		T13	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2498	1			T1	1		T4	2		T6	16